regs.h File Reference

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Defines
#define	__REGS_H__   1
#define	DATA_FLASH_BASE_BASE   (0x00000000u)
#define	DATA_FLASH_BASE_END   (0x0001FFFFu)
#define	DATA_FLASH_BASE_SIZE   (DATA_FLASH_BASE_END - DATA_FLASH_BASE_BASE + 1)
#define	DATA_FLASH_BASE   (0x08000000u)
#define	DATA_FLASH_END   (0x0801FFFFu)
#define	DATA_FLASH_SIZE   (DATA_FLASH_END - DATA_FLASH_BASE + 1)
#define	DATA_BIG_INFO_BASE_BASE   (0x00000000u)
#define	DATA_BIG_INFO_BASE_END   (0x000007FFu)
#define	DATA_BIG_INFO_BASE_SIZE   (DATA_BIG_INFO_BASE_END - DATA_BIG_INFO_BASE_BASE + 1)
#define	DATA_BIG_INFO_BASE   (0x08040000u)
#define	DATA_BIG_INFO_END   (0x080407FFu)
#define	DATA_BIG_INFO_SIZE   (DATA_BIG_INFO_END - DATA_BIG_INFO_BASE + 1)
#define	DATA_SMALL_INFO_BASE   (0x08040800u)
#define	DATA_SMALL_INFO_END   (0x080409FFu)
#define	DATA_SMALL_INFO_SIZE   (DATA_SMALL_INFO_END - DATA_SMALL_INFO_BASE + 1)
#define	DATA_SRAM_BASE   (0x20000000u)
#define	DATA_SRAM_END   (0x20001FFFu)
#define	DATA_SRAM_SIZE   (DATA_SRAM_END - DATA_SRAM_BASE + 1)
#define	DATA_CM_HV_BASE   (0x40000000u)
#define	DATA_CM_HV_END   (0x40000044u)
#define	DATA_CM_HV_SIZE   (DATA_CM_HV_END - DATA_CM_HV_BASE + 1)
#define	HV_SPARE   *((volatile int32u *)0x40000000u)
#define	HV_SPARE_REG   *((volatile int32u *)0x40000000u)
#define	HV_SPARE_ADDR   (0x40000000u)
#define	HV_SPARE_RESET   (0x00000000u)
#define	HV_SPARE_HV_SPARE   (0x000000FFu)
#define	HV_SPARE_HV_SPARE_MASK   (0x000000FFu)
#define	HV_SPARE_HV_SPARE_BIT   (0)
#define	HV_SPARE_HV_SPARE_BITS   (8)
#define	EVENT_CTRL   *((volatile int32u *)0x40000004u)
#define	EVENT_CTRL_REG   *((volatile int32u *)0x40000004u)
#define	EVENT_CTRL_ADDR   (0x40000004u)
#define	EVENT_CTRL_RESET   (0x00000000u)
#define	LV_FREEZE   (0x00000002u)
#define	LV_FREEZE_MASK   (0x00000002u)
#define	LV_FREEZE_BIT   (1)
#define	LV_FREEZE_BITS   (1)
#define	SLEEPTMR_CLKEN   *((volatile int32u *)0x40000008u)
#define	SLEEPTMR_CLKEN_REG   *((volatile int32u *)0x40000008u)
#define	SLEEPTMR_CLKEN_ADDR   (0x40000008u)
#define	SLEEPTMR_CLKEN_RESET   (0x00000002u)
#define	SLEEPTMR_CLK10KEN   (0x00000002u)
#define	SLEEPTMR_CLK10KEN_MASK   (0x00000002u)
#define	SLEEPTMR_CLK10KEN_BIT   (1)
#define	SLEEPTMR_CLK10KEN_BITS   (1)
#define	SLEEPTMR_CLK32KEN   (0x00000001u)
#define	SLEEPTMR_CLK32KEN_MASK   (0x00000001u)
#define	SLEEPTMR_CLK32KEN_BIT   (0)
#define	SLEEPTMR_CLK32KEN_BITS   (1)
#define	CLKRC_TUNE   *((volatile int32u *)0x4000000Cu)
#define	CLKRC_TUNE_REG   *((volatile int32u *)0x4000000Cu)
#define	CLKRC_TUNE_ADDR   (0x4000000Cu)
#define	CLKRC_TUNE_RESET   (0x00000000u)
#define	CLKRC_TUNE_FIELD   (0x0000000Fu)
#define	CLKRC_TUNE_FIELD_MASK   (0x0000000Fu)
#define	CLKRC_TUNE_FIELD_BIT   (0)
#define	CLKRC_TUNE_FIELD_BITS   (4)
#define	CLK1K_CAL   *((volatile int32u *)0x40000010u)
#define	CLK1K_CAL_REG   *((volatile int32u *)0x40000010u)
#define	CLK1K_CAL_ADDR   (0x40000010u)
#define	CLK1K_CAL_RESET   (0x00005000u)
#define	CLK1K_INTEGER   (0x0000F800u)
#define	CLK1K_INTEGER_MASK   (0x0000F800u)
#define	CLK1K_INTEGER_BIT   (11)
#define	CLK1K_INTEGER_BITS   (5)
#define	CLK1K_FRACTIONAL   (0x000007FFu)
#define	CLK1K_FRACTIONAL_MASK   (0x000007FFu)
#define	CLK1K_FRACTIONAL_BIT   (0)
#define	CLK1K_FRACTIONAL_BITS   (11)
#define	REGEN_DSLEEP   *((volatile int32u *)0x40000014u)
#define	REGEN_DSLEEP_REG   *((volatile int32u *)0x40000014u)
#define	REGEN_DSLEEP_ADDR   (0x40000014u)
#define	REGEN_DSLEEP_RESET   (0x00000001u)
#define	REGEN_DSLEEP_FIELD   (0x00000001u)
#define	REGEN_DSLEEP_FIELD_MASK   (0x00000001u)
#define	REGEN_DSLEEP_FIELD_BIT   (0)
#define	REGEN_DSLEEP_FIELD_BITS   (1)
#define	VREG   *((volatile int32u *)0x40000018u)
#define	VREG_REG   *((volatile int32u *)0x40000018u)
#define	VREG_ADDR   (0x40000018u)
#define	VREG_RESET   (0x00000207u)
#define	VREG_VREF_EN   (0x00008000u)
#define	VREG_VREF_EN_MASK   (0x00008000u)
#define	VREG_VREF_EN_BIT   (15)
#define	VREG_VREF_EN_BITS   (1)
#define	VREG_VREF_TEST   (0x00004000u)
#define	VREG_VREF_TEST_MASK   (0x00004000u)
#define	VREG_VREF_TEST_BIT   (14)
#define	VREG_VREF_TEST_BITS   (1)
#define	VREG_VREG_1V8_EN   (0x00000800u)
#define	VREG_VREG_1V8_EN_MASK   (0x00000800u)
#define	VREG_VREG_1V8_EN_BIT   (11)
#define	VREG_VREG_1V8_EN_BITS   (1)
#define	VREG_VREG_1V8_TEST   (0x00000400u)
#define	VREG_VREG_1V8_TEST_MASK   (0x00000400u)
#define	VREG_VREG_1V8_TEST_BIT   (10)
#define	VREG_VREG_1V8_TEST_BITS   (1)
#define	VREG_VREG_1V8_TRIM   (0x00000380u)
#define	VREG_VREG_1V8_TRIM_MASK   (0x00000380u)
#define	VREG_VREG_1V8_TRIM_BIT   (7)
#define	VREG_VREG_1V8_TRIM_BITS   (3)
#define	VREG_VREG_1V2_EN   (0x00000010u)
#define	VREG_VREG_1V2_EN_MASK   (0x00000010u)
#define	VREG_VREG_1V2_EN_BIT   (4)
#define	VREG_VREG_1V2_EN_BITS   (1)
#define	VREG_VREG_1V2_TEST   (0x00000008u)
#define	VREG_VREG_1V2_TEST_MASK   (0x00000008u)
#define	VREG_VREG_1V2_TEST_BIT   (3)
#define	VREG_VREG_1V2_TEST_BITS   (1)
#define	VREG_VREG_1V2_TRIM   (0x00000007u)
#define	VREG_VREG_1V2_TRIM_MASK   (0x00000007u)
#define	VREG_VREG_1V2_TRIM_BIT   (0)
#define	VREG_VREG_1V2_TRIM_BITS   (3)
#define	WAKE_SEL   *((volatile int32u *)0x40000020u)
#define	WAKE_SEL_REG   *((volatile int32u *)0x40000020u)
#define	WAKE_SEL_ADDR   (0x40000020u)
#define	WAKE_SEL_RESET   (0x00000200u)
#define	WAKE_CSYSPWRUPREQ   (0x00000200u)
#define	WAKE_CSYSPWRUPREQ_MASK   (0x00000200u)
#define	WAKE_CSYSPWRUPREQ_BIT   (9)
#define	WAKE_CSYSPWRUPREQ_BITS   (1)
#define	WAKE_CDBGPWRUPREQ   (0x00000100u)
#define	WAKE_CDBGPWRUPREQ_MASK   (0x00000100u)
#define	WAKE_CDBGPWRUPREQ_BIT   (8)
#define	WAKE_CDBGPWRUPREQ_BITS   (1)
#define	WAKE_WAKE_CORE   (0x00000080u)
#define	WAKE_WAKE_CORE_MASK   (0x00000080u)
#define	WAKE_WAKE_CORE_BIT   (7)
#define	WAKE_WAKE_CORE_BITS   (1)
#define	WAKE_SLEEPTMRWRAP   (0x00000040u)
#define	WAKE_SLEEPTMRWRAP_MASK   (0x00000040u)
#define	WAKE_SLEEPTMRWRAP_BIT   (6)
#define	WAKE_SLEEPTMRWRAP_BITS   (1)
#define	WAKE_SLEEPTMRCMPB   (0x00000020u)
#define	WAKE_SLEEPTMRCMPB_MASK   (0x00000020u)
#define	WAKE_SLEEPTMRCMPB_BIT   (5)
#define	WAKE_SLEEPTMRCMPB_BITS   (1)
#define	WAKE_SLEEPTMRCMPA   (0x00000010u)
#define	WAKE_SLEEPTMRCMPA_MASK   (0x00000010u)
#define	WAKE_SLEEPTMRCMPA_BIT   (4)
#define	WAKE_SLEEPTMRCMPA_BITS   (1)
#define	WAKE_IRQD   (0x00000008u)
#define	WAKE_IRQD_MASK   (0x00000008u)
#define	WAKE_IRQD_BIT   (3)
#define	WAKE_IRQD_BITS   (1)
#define	WAKE_SC2   (0x00000004u)
#define	WAKE_SC2_MASK   (0x00000004u)
#define	WAKE_SC2_BIT   (2)
#define	WAKE_SC2_BITS   (1)
#define	WAKE_SC1   (0x00000002u)
#define	WAKE_SC1_MASK   (0x00000002u)
#define	WAKE_SC1_BIT   (1)
#define	WAKE_SC1_BITS   (1)
#define	GPIO_WAKE   (0x00000001u)
#define	GPIO_WAKE_MASK   (0x00000001u)
#define	GPIO_WAKE_BIT   (0)
#define	GPIO_WAKE_BITS   (1)
#define	WAKE_CORE   *((volatile int32u *)0x40000024u)
#define	WAKE_CORE_REG   *((volatile int32u *)0x40000024u)
#define	WAKE_CORE_ADDR   (0x40000024u)
#define	WAKE_CORE_RESET   (0x00000000u)
#define	WAKE_CORE_FIELD   (0x00000020u)
#define	WAKE_CORE_FIELD_MASK   (0x00000020u)
#define	WAKE_CORE_FIELD_BIT   (5)
#define	WAKE_CORE_FIELD_BITS   (1)
#define	PWRUP_EVENT   *((volatile int32u *)0x40000028u)
#define	PWRUP_EVENT_REG   *((volatile int32u *)0x40000028u)
#define	PWRUP_EVENT_ADDR   (0x40000028u)
#define	PWRUP_EVENT_RESET   (0x00000000u)
#define	PWRUP_CSYSPWRUPREQ   (0x00000200u)
#define	PWRUP_CSYSPWRUPREQ_MASK   (0x00000200u)
#define	PWRUP_CSYSPWRUPREQ_BIT   (9)
#define	PWRUP_CSYSPWRUPREQ_BITS   (1)
#define	PWRUP_CDBGPWRUPREQ   (0x00000100u)
#define	PWRUP_CDBGPWRUPREQ_MASK   (0x00000100u)
#define	PWRUP_CDBGPWRUPREQ_BIT   (8)
#define	PWRUP_CDBGPWRUPREQ_BITS   (1)
#define	PWRUP_WAKECORE   (0x00000080u)
#define	PWRUP_WAKECORE_MASK   (0x00000080u)
#define	PWRUP_WAKECORE_BIT   (7)
#define	PWRUP_WAKECORE_BITS   (1)
#define	PWRUP_SLEEPTMRWRAP   (0x00000040u)
#define	PWRUP_SLEEPTMRWRAP_MASK   (0x00000040u)
#define	PWRUP_SLEEPTMRWRAP_BIT   (6)
#define	PWRUP_SLEEPTMRWRAP_BITS   (1)
#define	PWRUP_SLEEPTMRCOMPB   (0x00000020u)
#define	PWRUP_SLEEPTMRCOMPB_MASK   (0x00000020u)
#define	PWRUP_SLEEPTMRCOMPB_BIT   (5)
#define	PWRUP_SLEEPTMRCOMPB_BITS   (1)
#define	PWRUP_SLEEPTMRCOMPA   (0x00000010u)
#define	PWRUP_SLEEPTMRCOMPA_MASK   (0x00000010u)
#define	PWRUP_SLEEPTMRCOMPA_BIT   (4)
#define	PWRUP_SLEEPTMRCOMPA_BITS   (1)
#define	PWRUP_IRQD   (0x00000008u)
#define	PWRUP_IRQD_MASK   (0x00000008u)
#define	PWRUP_IRQD_BIT   (3)
#define	PWRUP_IRQD_BITS   (1)
#define	PWRUP_SC2   (0x00000004u)
#define	PWRUP_SC2_MASK   (0x00000004u)
#define	PWRUP_SC2_BIT   (2)
#define	PWRUP_SC2_BITS   (1)
#define	PWRUP_SC1   (0x00000002u)
#define	PWRUP_SC1_MASK   (0x00000002u)
#define	PWRUP_SC1_BIT   (1)
#define	PWRUP_SC1_BITS   (1)
#define	PWRUP_GPIO   (0x00000001u)
#define	PWRUP_GPIO_MASK   (0x00000001u)
#define	PWRUP_GPIO_BIT   (0)
#define	PWRUP_GPIO_BITS   (1)
#define	RESET_EVENT   *((volatile int32u *)0x4000002Cu)
#define	RESET_EVENT_REG   *((volatile int32u *)0x4000002Cu)
#define	RESET_EVENT_ADDR   (0x4000002Cu)
#define	RESET_EVENT_RESET   (0x00000001u)
#define	RESET_CPULOCKUP   (0x00000080u)
#define	RESET_CPULOCKUP_MASK   (0x00000080u)
#define	RESET_CPULOCKUP_BIT   (7)
#define	RESET_CPULOCKUP_BITS   (1)
#define	RESET_OPTBYTEFAIL   (0x00000040u)
#define	RESET_OPTBYTEFAIL_MASK   (0x00000040u)
#define	RESET_OPTBYTEFAIL_BIT   (6)
#define	RESET_OPTBYTEFAIL_BITS   (1)
#define	RESET_DSLEEP   (0x00000020u)
#define	RESET_DSLEEP_MASK   (0x00000020u)
#define	RESET_DSLEEP_BIT   (5)
#define	RESET_DSLEEP_BITS   (1)
#define	RESET_SW   (0x00000010u)
#define	RESET_SW_MASK   (0x00000010u)
#define	RESET_SW_BIT   (4)
#define	RESET_SW_BITS   (1)
#define	RESET_WDOG   (0x00000008u)
#define	RESET_WDOG_MASK   (0x00000008u)
#define	RESET_WDOG_BIT   (3)
#define	RESET_WDOG_BITS   (1)
#define	RESET_NRESET   (0x00000004u)
#define	RESET_NRESET_MASK   (0x00000004u)
#define	RESET_NRESET_BIT   (2)
#define	RESET_NRESET_BITS   (1)
#define	RESET_PWRLV   (0x00000002u)
#define	RESET_PWRLV_MASK   (0x00000002u)
#define	RESET_PWRLV_BIT   (1)
#define	RESET_PWRLV_BITS   (1)
#define	RESET_PWRHV   (0x00000001u)
#define	RESET_PWRHV_MASK   (0x00000001u)
#define	RESET_PWRHV_BIT   (0)
#define	RESET_PWRHV_BITS   (1)
#define	DBG_MBOX   *((volatile int32u *)0x40000030u)
#define	DBG_MBOX_REG   *((volatile int32u *)0x40000030u)
#define	DBG_MBOX_ADDR   (0x40000030u)
#define	DBG_MBOX_RESET   (0x00000000u)
#define	DBG_MBOX_DBG_MBOX   (0x0000FFFFu)
#define	DBG_MBOX_DBG_MBOX_MASK   (0x0000FFFFu)
#define	DBG_MBOX_DBG_MBOX_BIT   (0)
#define	DBG_MBOX_DBG_MBOX_BITS   (16)
#define	CPWRUPREQ_STATUS   *((volatile int32u *)0x40000034u)
#define	CPWRUPREQ_STATUS_REG   *((volatile int32u *)0x40000034u)
#define	CPWRUPREQ_STATUS_ADDR   (0x40000034u)
#define	CPWRUPREQ_STATUS_RESET   (0x00000000u)
#define	CPWRUPREQ_STATUS_CPWRUPREQ   (0x00000001u)
#define	CPWRUPREQ_STATUS_CPWRUPREQ_MASK   (0x00000001u)
#define	CPWRUPREQ_STATUS_CPWRUPREQ_BIT   (0)
#define	CPWRUPREQ_STATUS_CPWRUPREQ_BITS   (1)
#define	CSYSPWRUPREQ_STATUS   *((volatile int32u *)0x40000038u)
#define	CSYSPWRUPREQ_STATUS_REG   *((volatile int32u *)0x40000038u)
#define	CSYSPWRUPREQ_STATUS_ADDR   (0x40000038u)
#define	CSYSPWRUPREQ_STATUS_RESET   (0x00000000u)
#define	CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ   (0x00000001u)
#define	CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_MASK   (0x00000001u)
#define	CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_BIT   (0)
#define	CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_BITS   (1)
#define	CSYSPWRUPACK_STATUS   *((volatile int32u *)0x4000003Cu)
#define	CSYSPWRUPACK_STATUS_REG   *((volatile int32u *)0x4000003Cu)
#define	CSYSPWRUPACK_STATUS_ADDR   (0x4000003Cu)
#define	CSYSPWRUPACK_STATUS_RESET   (0x00000000u)
#define	CSYSPWRUPACK_STATUS_CSYSPWRUPACK   (0x00000001u)
#define	CSYSPWRUPACK_STATUS_CSYSPWRUPACK_MASK   (0x00000001u)
#define	CSYSPWRUPACK_STATUS_CSYSPWRUPACK_BIT   (0)
#define	CSYSPWRUPACK_STATUS_CSYSPWRUPACK_BITS   (1)
#define	CSYSPWRUPACK_INHIBIT   *((volatile int32u *)0x40000040u)
#define	CSYSPWRUPACK_INHIBIT_REG   *((volatile int32u *)0x40000040u)
#define	CSYSPWRUPACK_INHIBIT_ADDR   (0x40000040u)
#define	CSYSPWRUPACK_INHIBIT_RESET   (0x00000000u)
#define	CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT   (0x00000001u)
#define	CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_MASK   (0x00000001u)
#define	CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_BIT   (0)
#define	CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_BITS   (1)
#define	OPT_ERR_MAINTAIN_WAKE   *((volatile int32u *)0x40000044u)
#define	OPT_ERR_MAINTAIN_WAKE_REG   *((volatile int32u *)0x40000044u)
#define	OPT_ERR_MAINTAIN_WAKE_ADDR   (0x40000044u)
#define	OPT_ERR_MAINTAIN_WAKE_RESET   (0x00000000u)
#define	OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE   (0x00000001u)
#define	OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE_MASK   (0x00000001u)
#define	OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE_BIT   (0)
#define	OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE_BITS   (1)
#define	DATA_BASEBAND_BASE   (0x40001000u)
#define	DATA_BASEBAND_END   (0x40001114u)
#define	DATA_BASEBAND_SIZE   (DATA_BASEBAND_END - DATA_BASEBAND_BASE + 1)
#define	MOD_CAL_CTRL   *((volatile int32u *)0x40001000u)
#define	MOD_CAL_CTRL_REG   *((volatile int32u *)0x40001000u)
#define	MOD_CAL_CTRL_ADDR   (0x40001000u)
#define	MOD_CAL_CTRL_RESET   (0x00000000u)
#define	MOD_CAL_CTRL_MOD_CAL_GO   (0x00008000u)
#define	MOD_CAL_CTRL_MOD_CAL_GO_MASK   (0x00008000u)
#define	MOD_CAL_CTRL_MOD_CAL_GO_BIT   (15)
#define	MOD_CAL_CTRL_MOD_CAL_GO_BITS   (1)
#define	MOD_CAL_CTRL_MOD_CAL_DONE   (0x00000010u)
#define	MOD_CAL_CTRL_MOD_CAL_DONE_MASK   (0x00000010u)
#define	MOD_CAL_CTRL_MOD_CAL_DONE_BIT   (4)
#define	MOD_CAL_CTRL_MOD_CAL_DONE_BITS   (1)
#define	MOD_CAL_CTRL_MOD_CAL_CYCLES   (0x00000003u)
#define	MOD_CAL_CTRL_MOD_CAL_CYCLES_MASK   (0x00000003u)
#define	MOD_CAL_CTRL_MOD_CAL_CYCLES_BIT   (0)
#define	MOD_CAL_CTRL_MOD_CAL_CYCLES_BITS   (2)
#define	MOD_CAL_COUNT_H   *((volatile int32u *)0x40001004u)
#define	MOD_CAL_COUNT_H_REG   *((volatile int32u *)0x40001004u)
#define	MOD_CAL_COUNT_H_ADDR   (0x40001004u)
#define	MOD_CAL_COUNT_H_RESET   (0x00000000u)
#define	MOD_CAL_COUNT_H_MOD_CAL_COUNT_H   (0x000000FFu)
#define	MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_MASK   (0x000000FFu)
#define	MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_BIT   (0)
#define	MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_BITS   (8)
#define	MOD_CAL_COUNT_L   *((volatile int32u *)0x40001008u)
#define	MOD_CAL_COUNT_L_REG   *((volatile int32u *)0x40001008u)
#define	MOD_CAL_COUNT_L_ADDR   (0x40001008u)
#define	MOD_CAL_COUNT_L_RESET   (0x00000000u)
#define	MOD_CAL_COUNT_L_MOD_CAL_COUNT_L   (0x0000FFFFu)
#define	MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_MASK   (0x0000FFFFu)
#define	MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_BIT   (0)
#define	MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_BITS   (16)
#define	RSSI_ROLLING   *((volatile int32u *)0x4000100Cu)
#define	RSSI_ROLLING_REG   *((volatile int32u *)0x4000100Cu)
#define	RSSI_ROLLING_ADDR   (0x4000100Cu)
#define	RSSI_ROLLING_RESET   (0x00000000u)
#define	RSSI_ROLLING_RSSI_ROLLING   (0x00003FFFu)
#define	RSSI_ROLLING_RSSI_ROLLING_MASK   (0x00003FFFu)
#define	RSSI_ROLLING_RSSI_ROLLING_BIT   (0)
#define	RSSI_ROLLING_RSSI_ROLLING_BITS   (14)
#define	RSSI_PKT   *((volatile int32u *)0x40001010u)
#define	RSSI_PKT_REG   *((volatile int32u *)0x40001010u)
#define	RSSI_PKT_ADDR   (0x40001010u)
#define	RSSI_PKT_RESET   (0x00000000u)
#define	RSSI_PKT_RSSI_PKT   (0x000000FFu)
#define	RSSI_PKT_RSSI_PKT_MASK   (0x000000FFu)
#define	RSSI_PKT_RSSI_PKT_BIT   (0)
#define	RSSI_PKT_RSSI_PKT_BITS   (8)
#define	RX_ADC   *((volatile int32u *)0x40001014u)
#define	RX_ADC_REG   *((volatile int32u *)0x40001014u)
#define	RX_ADC_ADDR   (0x40001014u)
#define	RX_ADC_RESET   (0x00000024u)
#define	RX_ADC_RX_ADC   (0x0000007Fu)
#define	RX_ADC_RX_ADC_MASK   (0x0000007Fu)
#define	RX_ADC_RX_ADC_BIT   (0)
#define	RX_ADC_RX_ADC_BITS   (7)
#define	DEBUG_BB_MODE   *((volatile int32u *)0x40001018u)
#define	DEBUG_BB_MODE_REG   *((volatile int32u *)0x40001018u)
#define	DEBUG_BB_MODE_ADDR   (0x40001018u)
#define	DEBUG_BB_MODE_RESET   (0x00000000u)
#define	DEBUG_BB_MODE_DEBUG_BB_MODE_EN   (0x00008000u)
#define	DEBUG_BB_MODE_DEBUG_BB_MODE_EN_MASK   (0x00008000u)
#define	DEBUG_BB_MODE_DEBUG_BB_MODE_EN_BIT   (15)
#define	DEBUG_BB_MODE_DEBUG_BB_MODE_EN_BITS   (1)
#define	DEBUG_BB_MODE_DEBUG_BB_MODE   (0x00000003u)
#define	DEBUG_BB_MODE_DEBUG_BB_MODE_MASK   (0x00000003u)
#define	DEBUG_BB_MODE_DEBUG_BB_MODE_BIT   (0)
#define	DEBUG_BB_MODE_DEBUG_BB_MODE_BITS   (2)
#define	BB_DEBUG   *((volatile int32u *)0x4000101Cu)
#define	BB_DEBUG_REG   *((volatile int32u *)0x4000101Cu)
#define	BB_DEBUG_ADDR   (0x4000101Cu)
#define	BB_DEBUG_RESET   (0x00000002u)
#define	BB_DEBUG_SYNC_REG_EN   (0x00008000u)
#define	BB_DEBUG_SYNC_REG_EN_MASK   (0x00008000u)
#define	BB_DEBUG_SYNC_REG_EN_BIT   (15)
#define	BB_DEBUG_SYNC_REG_EN_BITS   (1)
#define	BB_DEBUG_DEBUG_MUX_ADDR   (0x000000F0u)
#define	BB_DEBUG_DEBUG_MUX_ADDR_MASK   (0x000000F0u)
#define	BB_DEBUG_DEBUG_MUX_ADDR_BIT   (4)
#define	BB_DEBUG_DEBUG_MUX_ADDR_BITS   (4)
#define	BB_DEBUG_BB_DEBUG_SEL   (0x00000003u)
#define	BB_DEBUG_BB_DEBUG_SEL_MASK   (0x00000003u)
#define	BB_DEBUG_BB_DEBUG_SEL_BIT   (0)
#define	BB_DEBUG_BB_DEBUG_SEL_BITS   (2)
#define	BB_DEBUG_VIEW   *((volatile int32u *)0x40001020u)
#define	BB_DEBUG_VIEW_REG   *((volatile int32u *)0x40001020u)
#define	BB_DEBUG_VIEW_ADDR   (0x40001020u)
#define	BB_DEBUG_VIEW_RESET   (0x00000000u)
#define	BB_DEBUG_VIEW_BB_DEBUG_VIEW   (0x0000FFFFu)
#define	BB_DEBUG_VIEW_BB_DEBUG_VIEW_MASK   (0x0000FFFFu)
#define	BB_DEBUG_VIEW_BB_DEBUG_VIEW_BIT   (0)
#define	BB_DEBUG_VIEW_BB_DEBUG_VIEW_BITS   (16)
#define	IF_FREQ   *((volatile int32u *)0x40001024u)
#define	IF_FREQ_REG   *((volatile int32u *)0x40001024u)
#define	IF_FREQ_ADDR   (0x40001024u)
#define	IF_FREQ_RESET   (0x00000155u)
#define	IF_FREQ_TIMING_CORR_EN   (0x00008000u)
#define	IF_FREQ_TIMING_CORR_EN_MASK   (0x00008000u)
#define	IF_FREQ_TIMING_CORR_EN_BIT   (15)
#define	IF_FREQ_TIMING_CORR_EN_BITS   (1)
#define	IF_FREQ_IF_FREQ   (0x000001FFu)
#define	IF_FREQ_IF_FREQ_MASK   (0x000001FFu)
#define	IF_FREQ_IF_FREQ_BIT   (0)
#define	IF_FREQ_IF_FREQ_BITS   (9)
#define	MOD_EN   *((volatile int32u *)0x40001028u)
#define	MOD_EN_REG   *((volatile int32u *)0x40001028u)
#define	MOD_EN_ADDR   (0x40001028u)
#define	MOD_EN_RESET   (0x00000001u)
#define	MOD_EN_MOD_EN   (0x00000001u)
#define	MOD_EN_MOD_EN_MASK   (0x00000001u)
#define	MOD_EN_MOD_EN_BIT   (0)
#define	MOD_EN_MOD_EN_BITS   (1)
#define	PRESCALE_CTRL   *((volatile int32u *)0x4000102Cu)
#define	PRESCALE_CTRL_REG   *((volatile int32u *)0x4000102Cu)
#define	PRESCALE_CTRL_ADDR   (0x4000102Cu)
#define	PRESCALE_CTRL_RESET   (0x00000000u)
#define	PRESCALE_CTRL_PRESCALE_SET   (0x00008000u)
#define	PRESCALE_CTRL_PRESCALE_SET_MASK   (0x00008000u)
#define	PRESCALE_CTRL_PRESCALE_SET_BIT   (15)
#define	PRESCALE_CTRL_PRESCALE_SET_BITS   (1)
#define	PRESCALE_CTRL_PRESCALE_VAL   (0x00000007u)
#define	PRESCALE_CTRL_PRESCALE_VAL_MASK   (0x00000007u)
#define	PRESCALE_CTRL_PRESCALE_VAL_BIT   (0)
#define	PRESCALE_CTRL_PRESCALE_VAL_BITS   (3)
#define	ADC_BYPASS_EN   *((volatile int32u *)0x40001030u)
#define	ADC_BYPASS_EN_REG   *((volatile int32u *)0x40001030u)
#define	ADC_BYPASS_EN_ADDR   (0x40001030u)
#define	ADC_BYPASS_EN_RESET   (0x00000000u)
#define	ADC_BYPASS_EN_ADC_BYPASS_EN   (0x00000001u)
#define	ADC_BYPASS_EN_ADC_BYPASS_EN_MASK   (0x00000001u)
#define	ADC_BYPASS_EN_ADC_BYPASS_EN_BIT   (0)
#define	ADC_BYPASS_EN_ADC_BYPASS_EN_BITS   (1)
#define	FIXED_CODE_EN   *((volatile int32u *)0x40001034u)
#define	FIXED_CODE_EN_REG   *((volatile int32u *)0x40001034u)
#define	FIXED_CODE_EN_ADDR   (0x40001034u)
#define	FIXED_CODE_EN_RESET   (0x00000000u)
#define	FIXED_CODE_EN_FIXED_CODE_EN   (0x00000001u)
#define	FIXED_CODE_EN_FIXED_CODE_EN_MASK   (0x00000001u)
#define	FIXED_CODE_EN_FIXED_CODE_EN_BIT   (0)
#define	FIXED_CODE_EN_FIXED_CODE_EN_BITS   (1)
#define	FIXED_CODE_H   *((volatile int32u *)0x40001038u)
#define	FIXED_CODE_H_REG   *((volatile int32u *)0x40001038u)
#define	FIXED_CODE_H_ADDR   (0x40001038u)
#define	FIXED_CODE_H_RESET   (0x00000000u)
#define	FIXED_CODE_H_FIXED_CODE_H   (0x0000FFFFu)
#define	FIXED_CODE_H_FIXED_CODE_H_MASK   (0x0000FFFFu)
#define	FIXED_CODE_H_FIXED_CODE_H_BIT   (0)
#define	FIXED_CODE_H_FIXED_CODE_H_BITS   (16)
#define	FIXED_CODE_L   *((volatile int32u *)0x4000103Cu)
#define	FIXED_CODE_L_REG   *((volatile int32u *)0x4000103Cu)
#define	FIXED_CODE_L_ADDR   (0x4000103Cu)
#define	FIXED_CODE_L_RESET   (0x00000000u)
#define	FIXED_CODE_L_FIXED_CODE_L   (0x0000FFFFu)
#define	FIXED_CODE_L_FIXED_CODE_L_MASK   (0x0000FFFFu)
#define	FIXED_CODE_L_FIXED_CODE_L_BIT   (0)
#define	FIXED_CODE_L_FIXED_CODE_L_BITS   (16)
#define	FIXED_CODE_L_SHADOW   *((volatile int32u *)0x40001040u)
#define	FIXED_CODE_L_SHADOW_REG   *((volatile int32u *)0x40001040u)
#define	FIXED_CODE_L_SHADOW_ADDR   (0x40001040u)
#define	FIXED_CODE_L_SHADOW_RESET   (0x00000000u)
#define	FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW   (0x0000FFFFu)
#define	FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_MASK   (0x0000FFFFu)
#define	FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_BIT   (0)
#define	FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_BITS   (16)
#define	RX_GAIN_CTRL   *((volatile int32u *)0x40001044u)
#define	RX_GAIN_CTRL_REG   *((volatile int32u *)0x40001044u)
#define	RX_GAIN_CTRL_ADDR   (0x40001044u)
#define	RX_GAIN_CTRL_RESET   (0x00000000u)
#define	RX_GAIN_CTRL_RX_GAIN_MUX   (0x00008000u)
#define	RX_GAIN_CTRL_RX_GAIN_MUX_MASK   (0x00008000u)
#define	RX_GAIN_CTRL_RX_GAIN_MUX_BIT   (15)
#define	RX_GAIN_CTRL_RX_GAIN_MUX_BITS   (1)
#define	RX_GAIN_CTRL_RX_RF_GAIN_TEST   (0x00000080u)
#define	RX_GAIN_CTRL_RX_RF_GAIN_TEST_MASK   (0x00000080u)
#define	RX_GAIN_CTRL_RX_RF_GAIN_TEST_BIT   (7)
#define	RX_GAIN_CTRL_RX_RF_GAIN_TEST_BITS   (1)
#define	RX_GAIN_CTRL_RX_MIXER_GAIN_TEST   (0x00000040u)
#define	RX_GAIN_CTRL_RX_MIXER_GAIN_TEST_MASK   (0x00000040u)
#define	RX_GAIN_CTRL_RX_MIXER_GAIN_TEST_BIT   (6)
#define	RX_GAIN_CTRL_RX_MIXER_GAIN_TEST_BITS   (1)
#define	RX_GAIN_CTRL_RX_FILTER_GAIN_TEST   (0x00000030u)
#define	RX_GAIN_CTRL_RX_FILTER_GAIN_TEST_MASK   (0x00000030u)
#define	RX_GAIN_CTRL_RX_FILTER_GAIN_TEST_BIT   (4)
#define	RX_GAIN_CTRL_RX_FILTER_GAIN_TEST_BITS   (2)
#define	RX_GAIN_CTRL_RX_IF_GAIN_TEST   (0x0000000Fu)
#define	RX_GAIN_CTRL_RX_IF_GAIN_TEST_MASK   (0x0000000Fu)
#define	RX_GAIN_CTRL_RX_IF_GAIN_TEST_BIT   (0)
#define	RX_GAIN_CTRL_RX_IF_GAIN_TEST_BITS   (4)
#define	PD_DITHER_EN   *((volatile int32u *)0x40001048u)
#define	PD_DITHER_EN_REG   *((volatile int32u *)0x40001048u)
#define	PD_DITHER_EN_ADDR   (0x40001048u)
#define	PD_DITHER_EN_RESET   (0x00000001u)
#define	PD_DITHER_EN_PD_DITHER_EN   (0x00000001u)
#define	PD_DITHER_EN_PD_DITHER_EN_MASK   (0x00000001u)
#define	PD_DITHER_EN_PD_DITHER_EN_BIT   (0)
#define	PD_DITHER_EN_PD_DITHER_EN_BITS   (1)
#define	RX_ERR_THRESH   *((volatile int32u *)0x4000104Cu)
#define	RX_ERR_THRESH_REG   *((volatile int32u *)0x4000104Cu)
#define	RX_ERR_THRESH_ADDR   (0x4000104Cu)
#define	RX_ERR_THRESH_RESET   (0x00004608u)
#define	RX_ERR_THRESH_LPF_RX_ERR_COEFF   (0x0000E000u)
#define	RX_ERR_THRESH_LPF_RX_ERR_COEFF_MASK   (0x0000E000u)
#define	RX_ERR_THRESH_LPF_RX_ERR_COEFF_BIT   (13)
#define	RX_ERR_THRESH_LPF_RX_ERR_COEFF_BITS   (3)
#define	RX_ERR_THRESH_LPF_RX_ERR_THRESH   (0x00001F00u)
#define	RX_ERR_THRESH_LPF_RX_ERR_THRESH_MASK   (0x00001F00u)
#define	RX_ERR_THRESH_LPF_RX_ERR_THRESH_BIT   (8)
#define	RX_ERR_THRESH_LPF_RX_ERR_THRESH_BITS   (5)
#define	RX_ERR_THRESH_RX_ERR_THRESH   (0x0000001Fu)
#define	RX_ERR_THRESH_RX_ERR_THRESH_MASK   (0x0000001Fu)
#define	RX_ERR_THRESH_RX_ERR_THRESH_BIT   (0)
#define	RX_ERR_THRESH_RX_ERR_THRESH_BITS   (5)
#define	CARRIER_THRESH   *((volatile int32u *)0x40001050u)
#define	CARRIER_THRESH_REG   *((volatile int32u *)0x40001050u)
#define	CARRIER_THRESH_ADDR   (0x40001050u)
#define	CARRIER_THRESH_RESET   (0x00002332u)
#define	CARRIER_THRESH_CARRIER_SPIKE_THRESH   (0x0000FF00u)
#define	CARRIER_THRESH_CARRIER_SPIKE_THRESH_MASK   (0x0000FF00u)
#define	CARRIER_THRESH_CARRIER_SPIKE_THRESH_BIT   (8)
#define	CARRIER_THRESH_CARRIER_SPIKE_THRESH_BITS   (8)
#define	CARRIER_THRESH_CARRIER_THRESH   (0x000000FFu)
#define	CARRIER_THRESH_CARRIER_THRESH_MASK   (0x000000FFu)
#define	CARRIER_THRESH_CARRIER_THRESH_BIT   (0)
#define	CARRIER_THRESH_CARRIER_THRESH_BITS   (8)
#define	RSSI_THRESH   *((volatile int32u *)0x40001054u)
#define	RSSI_THRESH_REG   *((volatile int32u *)0x40001054u)
#define	RSSI_THRESH_ADDR   (0x40001054u)
#define	RSSI_THRESH_RESET   (0x00000100u)
#define	RSSI_THRESH_RSSI_THRESH   (0x0000FFFFu)
#define	RSSI_THRESH_RSSI_THRESH_MASK   (0x0000FFFFu)
#define	RSSI_THRESH_RSSI_THRESH_BIT   (0)
#define	RSSI_THRESH_RSSI_THRESH_BITS   (16)
#define	SYNTH_START   *((volatile int32u *)0x40001058u)
#define	SYNTH_START_REG   *((volatile int32u *)0x40001058u)
#define	SYNTH_START_ADDR   (0x40001058u)
#define	SYNTH_START_RESET   (0x00006464u)
#define	SYNTH_START_SYNTH_WARM_START   (0x0000FF00u)
#define	SYNTH_START_SYNTH_WARM_START_MASK   (0x0000FF00u)
#define	SYNTH_START_SYNTH_WARM_START_BIT   (8)
#define	SYNTH_START_SYNTH_WARM_START_BITS   (8)
#define	SYNTH_START_SYNTH_COLD_START   (0x000000FFu)
#define	SYNTH_START_SYNTH_COLD_START_MASK   (0x000000FFu)
#define	SYNTH_START_SYNTH_COLD_START_BIT   (0)
#define	SYNTH_START_SYNTH_COLD_START_BITS   (8)
#define	IN_LOCK_EN   *((volatile int32u *)0x4000105Cu)
#define	IN_LOCK_EN_REG   *((volatile int32u *)0x4000105Cu)
#define	IN_LOCK_EN_ADDR   (0x4000105Cu)
#define	IN_LOCK_EN_RESET   (0x00000001u)
#define	IN_LOCK_EN_IN_LOCK_EN   (0x00000001u)
#define	IN_LOCK_EN_IN_LOCK_EN_MASK   (0x00000001u)
#define	IN_LOCK_EN_IN_LOCK_EN_BIT   (0)
#define	IN_LOCK_EN_IN_LOCK_EN_BITS   (1)
#define	DITHER_AMPLITUDE   *((volatile int32u *)0x40001060u)
#define	DITHER_AMPLITUDE_REG   *((volatile int32u *)0x40001060u)
#define	DITHER_AMPLITUDE_ADDR   (0x40001060u)
#define	DITHER_AMPLITUDE_RESET   (0x0000003Fu)
#define	DITHER_AMPLITUDE_DITHER_AMP   (0x0000003Fu)
#define	DITHER_AMPLITUDE_DITHER_AMP_MASK   (0x0000003Fu)
#define	DITHER_AMPLITUDE_DITHER_AMP_BIT   (0)
#define	DITHER_AMPLITUDE_DITHER_AMP_BITS   (6)
#define	TX_STEP_TIME   *((volatile int32u *)0x40001064u)
#define	TX_STEP_TIME_REG   *((volatile int32u *)0x40001064u)
#define	TX_STEP_TIME_ADDR   (0x40001064u)
#define	TX_STEP_TIME_RESET   (0x00000000u)
#define	TX_STEP_TIME_TX_STEP_TIME   (0x000000FFu)
#define	TX_STEP_TIME_TX_STEP_TIME_MASK   (0x000000FFu)
#define	TX_STEP_TIME_TX_STEP_TIME_BIT   (0)
#define	TX_STEP_TIME_TX_STEP_TIME_BITS   (8)
#define	GAIN_THRESH_MAX   *((volatile int32u *)0x40001068u)
#define	GAIN_THRESH_MAX_REG   *((volatile int32u *)0x40001068u)
#define	GAIN_THRESH_MAX_ADDR   (0x40001068u)
#define	GAIN_THRESH_MAX_RESET   (0x00000060u)
#define	GAIN_THRESH_MAX_GAIN_THRESH_MAX   (0x000000FFu)
#define	GAIN_THRESH_MAX_GAIN_THRESH_MAX_MASK   (0x000000FFu)
#define	GAIN_THRESH_MAX_GAIN_THRESH_MAX_BIT   (0)
#define	GAIN_THRESH_MAX_GAIN_THRESH_MAX_BITS   (8)
#define	GAIN_THRESH_MID   *((volatile int32u *)0x4000106Cu)
#define	GAIN_THRESH_MID_REG   *((volatile int32u *)0x4000106Cu)
#define	GAIN_THRESH_MID_ADDR   (0x4000106Cu)
#define	GAIN_THRESH_MID_RESET   (0x00000030u)
#define	GAIN_THRESH_MID_GAIN_THRESH_MID   (0x000000FFu)
#define	GAIN_THRESH_MID_GAIN_THRESH_MID_MASK   (0x000000FFu)
#define	GAIN_THRESH_MID_GAIN_THRESH_MID_BIT   (0)
#define	GAIN_THRESH_MID_GAIN_THRESH_MID_BITS   (8)
#define	GAIN_THRESH_MIN   *((volatile int32u *)0x40001070u)
#define	GAIN_THRESH_MIN_REG   *((volatile int32u *)0x40001070u)
#define	GAIN_THRESH_MIN_ADDR   (0x40001070u)
#define	GAIN_THRESH_MIN_RESET   (0x00000018u)
#define	GAIN_THRESH_MIN_GAIN_THRESH_MIN   (0x000000FFu)
#define	GAIN_THRESH_MIN_GAIN_THRESH_MIN_MASK   (0x000000FFu)
#define	GAIN_THRESH_MIN_GAIN_THRESH_MIN_BIT   (0)
#define	GAIN_THRESH_MIN_GAIN_THRESH_MIN_BITS   (8)
#define	GAIN_SETTING_0   *((volatile int32u *)0x40001074u)
#define	GAIN_SETTING_0_REG   *((volatile int32u *)0x40001074u)
#define	GAIN_SETTING_0_ADDR   (0x40001074u)
#define	GAIN_SETTING_0_RESET   (0x00000000u)
#define	GAIN_SETTING_0_RX_MIXER_GAIN_0   (0x00000040u)
#define	GAIN_SETTING_0_RX_MIXER_GAIN_0_MASK   (0x00000040u)
#define	GAIN_SETTING_0_RX_MIXER_GAIN_0_BIT   (6)
#define	GAIN_SETTING_0_RX_MIXER_GAIN_0_BITS   (1)
#define	GAIN_SETTING_0_RX_FILTER_GAIN_0   (0x00000030u)
#define	GAIN_SETTING_0_RX_FILTER_GAIN_0_MASK   (0x00000030u)
#define	GAIN_SETTING_0_RX_FILTER_GAIN_0_BIT   (4)
#define	GAIN_SETTING_0_RX_FILTER_GAIN_0_BITS   (2)
#define	GAIN_SETTING_0_RX_IF_GAIN_0   (0x0000000Fu)
#define	GAIN_SETTING_0_RX_IF_GAIN_0_MASK   (0x0000000Fu)
#define	GAIN_SETTING_0_RX_IF_GAIN_0_BIT   (0)
#define	GAIN_SETTING_0_RX_IF_GAIN_0_BITS   (4)
#define	GAIN_SETTING_1   *((volatile int32u *)0x40001078u)
#define	GAIN_SETTING_1_REG   *((volatile int32u *)0x40001078u)
#define	GAIN_SETTING_1_ADDR   (0x40001078u)
#define	GAIN_SETTING_1_RESET   (0x00000010u)
#define	GAIN_SETTING_1_RX_MIXER_GAIN_1   (0x00000040u)
#define	GAIN_SETTING_1_RX_MIXER_GAIN_1_MASK   (0x00000040u)
#define	GAIN_SETTING_1_RX_MIXER_GAIN_1_BIT   (6)
#define	GAIN_SETTING_1_RX_MIXER_GAIN_1_BITS   (1)
#define	GAIN_SETTING_1_RX_FILTER_GAIN_1   (0x00000030u)
#define	GAIN_SETTING_1_RX_FILTER_GAIN_1_MASK   (0x00000030u)
#define	GAIN_SETTING_1_RX_FILTER_GAIN_1_BIT   (4)
#define	GAIN_SETTING_1_RX_FILTER_GAIN_1_BITS   (2)
#define	GAIN_SETTING_1_RX_IF_GAIN_1   (0x0000000Fu)
#define	GAIN_SETTING_1_RX_IF_GAIN_1_MASK   (0x0000000Fu)
#define	GAIN_SETTING_1_RX_IF_GAIN_1_BIT   (0)
#define	GAIN_SETTING_1_RX_IF_GAIN_1_BITS   (4)
#define	GAIN_SETTING_2   *((volatile int32u *)0x4000107Cu)
#define	GAIN_SETTING_2_REG   *((volatile int32u *)0x4000107Cu)
#define	GAIN_SETTING_2_ADDR   (0x4000107Cu)
#define	GAIN_SETTING_2_RESET   (0x00000030u)
#define	GAIN_SETTING_2_RX_MIXER_GAIN_2   (0x00000040u)
#define	GAIN_SETTING_2_RX_MIXER_GAIN_2_MASK   (0x00000040u)
#define	GAIN_SETTING_2_RX_MIXER_GAIN_2_BIT   (6)
#define	GAIN_SETTING_2_RX_MIXER_GAIN_2_BITS   (1)
#define	GAIN_SETTING_2_RX_FILTER_GAIN_2   (0x00000030u)
#define	GAIN_SETTING_2_RX_FILTER_GAIN_2_MASK   (0x00000030u)
#define	GAIN_SETTING_2_RX_FILTER_GAIN_2_BIT   (4)
#define	GAIN_SETTING_2_RX_FILTER_GAIN_2_BITS   (2)
#define	GAIN_SETTING_2_RX_IF_GAIN_2   (0x0000000Fu)
#define	GAIN_SETTING_2_RX_IF_GAIN_2_MASK   (0x0000000Fu)
#define	GAIN_SETTING_2_RX_IF_GAIN_2_BIT   (0)
#define	GAIN_SETTING_2_RX_IF_GAIN_2_BITS   (4)
#define	GAIN_SETTING_3   *((volatile int32u *)0x40001080u)
#define	GAIN_SETTING_3_REG   *((volatile int32u *)0x40001080u)
#define	GAIN_SETTING_3_ADDR   (0x40001080u)
#define	GAIN_SETTING_3_RESET   (0x00000031u)
#define	GAIN_SETTING_3_RX_MIXER_GAIN_3   (0x00000040u)
#define	GAIN_SETTING_3_RX_MIXER_GAIN_3_MASK   (0x00000040u)
#define	GAIN_SETTING_3_RX_MIXER_GAIN_3_BIT   (6)
#define	GAIN_SETTING_3_RX_MIXER_GAIN_3_BITS   (1)
#define	GAIN_SETTING_3_RX_FILTER_GAIN_3   (0x00000030u)
#define	GAIN_SETTING_3_RX_FILTER_GAIN_3_MASK   (0x00000030u)
#define	GAIN_SETTING_3_RX_FILTER_GAIN_3_BIT   (4)
#define	GAIN_SETTING_3_RX_FILTER_GAIN_3_BITS   (2)
#define	GAIN_SETTING_3_RX_IF_GAIN_3   (0x0000000Fu)
#define	GAIN_SETTING_3_RX_IF_GAIN_3_MASK   (0x0000000Fu)
#define	GAIN_SETTING_3_RX_IF_GAIN_3_BIT   (0)
#define	GAIN_SETTING_3_RX_IF_GAIN_3_BITS   (4)
#define	GAIN_SETTING_4   *((volatile int32u *)0x40001084u)
#define	GAIN_SETTING_4_REG   *((volatile int32u *)0x40001084u)
#define	GAIN_SETTING_4_ADDR   (0x40001084u)
#define	GAIN_SETTING_4_RESET   (0x00000032u)
#define	GAIN_SETTING_4_RX_MIXER_GAIN_4   (0x00000040u)
#define	GAIN_SETTING_4_RX_MIXER_GAIN_4_MASK   (0x00000040u)
#define	GAIN_SETTING_4_RX_MIXER_GAIN_4_BIT   (6)
#define	GAIN_SETTING_4_RX_MIXER_GAIN_4_BITS   (1)
#define	GAIN_SETTING_4_RX_FILTER_GAIN_4   (0x00000030u)
#define	GAIN_SETTING_4_RX_FILTER_GAIN_4_MASK   (0x00000030u)
#define	GAIN_SETTING_4_RX_FILTER_GAIN_4_BIT   (4)
#define	GAIN_SETTING_4_RX_FILTER_GAIN_4_BITS   (2)
#define	GAIN_SETTING_4_RX_IF_GAIN_4   (0x0000000Fu)
#define	GAIN_SETTING_4_RX_IF_GAIN_4_MASK   (0x0000000Fu)
#define	GAIN_SETTING_4_RX_IF_GAIN_4_BIT   (0)
#define	GAIN_SETTING_4_RX_IF_GAIN_4_BITS   (4)
#define	GAIN_SETTING_5   *((volatile int32u *)0x40001088u)
#define	GAIN_SETTING_5_REG   *((volatile int32u *)0x40001088u)
#define	GAIN_SETTING_5_ADDR   (0x40001088u)
#define	GAIN_SETTING_5_RESET   (0x00000033u)
#define	GAIN_SETTING_5_RX_MIXER_GAIN_5   (0x00000040u)
#define	GAIN_SETTING_5_RX_MIXER_GAIN_5_MASK   (0x00000040u)
#define	GAIN_SETTING_5_RX_MIXER_GAIN_5_BIT   (6)
#define	GAIN_SETTING_5_RX_MIXER_GAIN_5_BITS   (1)
#define	GAIN_SETTING_5_RX_FILTER_GAIN_5   (0x00000030u)
#define	GAIN_SETTING_5_RX_FILTER_GAIN_5_MASK   (0x00000030u)
#define	GAIN_SETTING_5_RX_FILTER_GAIN_5_BIT   (4)
#define	GAIN_SETTING_5_RX_FILTER_GAIN_5_BITS   (2)
#define	GAIN_SETTING_5_RX_IF_GAIN_5   (0x0000000Fu)
#define	GAIN_SETTING_5_RX_IF_GAIN_5_MASK   (0x0000000Fu)
#define	GAIN_SETTING_5_RX_IF_GAIN_5_BIT   (0)
#define	GAIN_SETTING_5_RX_IF_GAIN_5_BITS   (4)
#define	GAIN_SETTING_6   *((volatile int32u *)0x4000108Cu)
#define	GAIN_SETTING_6_REG   *((volatile int32u *)0x4000108Cu)
#define	GAIN_SETTING_6_ADDR   (0x4000108Cu)
#define	GAIN_SETTING_6_RESET   (0x00000034u)
#define	GAIN_SETTING_6_RX_MIXER_GAIN_6   (0x00000040u)
#define	GAIN_SETTING_6_RX_MIXER_GAIN_6_MASK   (0x00000040u)
#define	GAIN_SETTING_6_RX_MIXER_GAIN_6_BIT   (6)
#define	GAIN_SETTING_6_RX_MIXER_GAIN_6_BITS   (1)
#define	GAIN_SETTING_6_RX_FILTER_GAIN_6   (0x00000030u)
#define	GAIN_SETTING_6_RX_FILTER_GAIN_6_MASK   (0x00000030u)
#define	GAIN_SETTING_6_RX_FILTER_GAIN_6_BIT   (4)
#define	GAIN_SETTING_6_RX_FILTER_GAIN_6_BITS   (2)
#define	GAIN_SETTING_6_RX_IF_GAIN_6   (0x0000000Fu)
#define	GAIN_SETTING_6_RX_IF_GAIN_6_MASK   (0x0000000Fu)
#define	GAIN_SETTING_6_RX_IF_GAIN_6_BIT   (0)
#define	GAIN_SETTING_6_RX_IF_GAIN_6_BITS   (4)
#define	GAIN_SETTING_7   *((volatile int32u *)0x40001090u)
#define	GAIN_SETTING_7_REG   *((volatile int32u *)0x40001090u)
#define	GAIN_SETTING_7_ADDR   (0x40001090u)
#define	GAIN_SETTING_7_RESET   (0x00000035u)
#define	GAIN_SETTING_7_RX_MIXER_GAIN_7   (0x00000040u)
#define	GAIN_SETTING_7_RX_MIXER_GAIN_7_MASK   (0x00000040u)
#define	GAIN_SETTING_7_RX_MIXER_GAIN_7_BIT   (6)
#define	GAIN_SETTING_7_RX_MIXER_GAIN_7_BITS   (1)
#define	GAIN_SETTING_7_RX_FILTER_GAIN_7   (0x00000030u)
#define	GAIN_SETTING_7_RX_FILTER_GAIN_7_MASK   (0x00000030u)
#define	GAIN_SETTING_7_RX_FILTER_GAIN_7_BIT   (4)
#define	GAIN_SETTING_7_RX_FILTER_GAIN_7_BITS   (2)
#define	GAIN_SETTING_7_RX_IF_GAIN_7   (0x0000000Fu)
#define	GAIN_SETTING_7_RX_IF_GAIN_7_MASK   (0x0000000Fu)
#define	GAIN_SETTING_7_RX_IF_GAIN_7_BIT   (0)
#define	GAIN_SETTING_7_RX_IF_GAIN_7_BITS   (4)
#define	GAIN_SETTING_8   *((volatile int32u *)0x40001094u)
#define	GAIN_SETTING_8_REG   *((volatile int32u *)0x40001094u)
#define	GAIN_SETTING_8_ADDR   (0x40001094u)
#define	GAIN_SETTING_8_RESET   (0x00000036u)
#define	GAIN_SETTING_8_RX_MIXER_GAIN_8   (0x00000040u)
#define	GAIN_SETTING_8_RX_MIXER_GAIN_8_MASK   (0x00000040u)
#define	GAIN_SETTING_8_RX_MIXER_GAIN_8_BIT   (6)
#define	GAIN_SETTING_8_RX_MIXER_GAIN_8_BITS   (1)
#define	GAIN_SETTING_8_RX_FILTER_GAIN_8   (0x00000030u)
#define	GAIN_SETTING_8_RX_FILTER_GAIN_8_MASK   (0x00000030u)
#define	GAIN_SETTING_8_RX_FILTER_GAIN_8_BIT   (4)
#define	GAIN_SETTING_8_RX_FILTER_GAIN_8_BITS   (2)
#define	GAIN_SETTING_8_RX_IF_GAIN_8   (0x0000000Fu)
#define	GAIN_SETTING_8_RX_IF_GAIN_8_MASK   (0x0000000Fu)
#define	GAIN_SETTING_8_RX_IF_GAIN_8_BIT   (0)
#define	GAIN_SETTING_8_RX_IF_GAIN_8_BITS   (4)
#define	GAIN_SETTING_9   *((volatile int32u *)0x40001098u)
#define	GAIN_SETTING_9_REG   *((volatile int32u *)0x40001098u)
#define	GAIN_SETTING_9_ADDR   (0x40001098u)
#define	GAIN_SETTING_9_RESET   (0x00000076u)
#define	GAIN_SETTING_9_RX_MIXER_GAIN_9   (0x00000040u)
#define	GAIN_SETTING_9_RX_MIXER_GAIN_9_MASK   (0x00000040u)
#define	GAIN_SETTING_9_RX_MIXER_GAIN_9_BIT   (6)
#define	GAIN_SETTING_9_RX_MIXER_GAIN_9_BITS   (1)
#define	GAIN_SETTING_9_RX_FILTER_GAIN_9   (0x00000030u)
#define	GAIN_SETTING_9_RX_FILTER_GAIN_9_MASK   (0x00000030u)
#define	GAIN_SETTING_9_RX_FILTER_GAIN_9_BIT   (4)
#define	GAIN_SETTING_9_RX_FILTER_GAIN_9_BITS   (2)
#define	GAIN_SETTING_9_RX_IF_GAIN_9   (0x0000000Fu)
#define	GAIN_SETTING_9_RX_IF_GAIN_9_MASK   (0x0000000Fu)
#define	GAIN_SETTING_9_RX_IF_GAIN_9_BIT   (0)
#define	GAIN_SETTING_9_RX_IF_GAIN_9_BITS   (4)
#define	GAIN_SETTING_10   *((volatile int32u *)0x4000109Cu)
#define	GAIN_SETTING_10_REG   *((volatile int32u *)0x4000109Cu)
#define	GAIN_SETTING_10_ADDR   (0x4000109Cu)
#define	GAIN_SETTING_10_RESET   (0x00000077u)
#define	GAIN_SETTING_10_RX_MIXER_GAIN_10   (0x00000040u)
#define	GAIN_SETTING_10_RX_MIXER_GAIN_10_MASK   (0x00000040u)
#define	GAIN_SETTING_10_RX_MIXER_GAIN_10_BIT   (6)
#define	GAIN_SETTING_10_RX_MIXER_GAIN_10_BITS   (1)
#define	GAIN_SETTING_10_RX_FILTER_GAIN_10   (0x00000030u)
#define	GAIN_SETTING_10_RX_FILTER_GAIN_10_MASK   (0x00000030u)
#define	GAIN_SETTING_10_RX_FILTER_GAIN_10_BIT   (4)
#define	GAIN_SETTING_10_RX_FILTER_GAIN_10_BITS   (2)
#define	GAIN_SETTING_10_RX_IF_GAIN_10   (0x0000000Fu)
#define	GAIN_SETTING_10_RX_IF_GAIN_10_MASK   (0x0000000Fu)
#define	GAIN_SETTING_10_RX_IF_GAIN_10_BIT   (0)
#define	GAIN_SETTING_10_RX_IF_GAIN_10_BITS   (4)
#define	GAIN_SETTING_11   *((volatile int32u *)0x400010A0u)
#define	GAIN_SETTING_11_REG   *((volatile int32u *)0x400010A0u)
#define	GAIN_SETTING_11_ADDR   (0x400010A0u)
#define	GAIN_SETTING_11_RESET   (0x00000078u)
#define	GAIN_SETTING_11_RX_MIXER_GAIN_11   (0x00000040u)
#define	GAIN_SETTING_11_RX_MIXER_GAIN_11_MASK   (0x00000040u)
#define	GAIN_SETTING_11_RX_MIXER_GAIN_11_BIT   (6)
#define	GAIN_SETTING_11_RX_MIXER_GAIN_11_BITS   (1)
#define	GAIN_SETTING_11_RX_FILTER_GAIN_11   (0x00000030u)
#define	GAIN_SETTING_11_RX_FILTER_GAIN_11_MASK   (0x00000030u)
#define	GAIN_SETTING_11_RX_FILTER_GAIN_11_BIT   (4)
#define	GAIN_SETTING_11_RX_FILTER_GAIN_11_BITS   (2)
#define	GAIN_SETTING_11_RX_IF_GAIN_11   (0x0000000Fu)
#define	GAIN_SETTING_11_RX_IF_GAIN_11_MASK   (0x0000000Fu)
#define	GAIN_SETTING_11_RX_IF_GAIN_11_BIT   (0)
#define	GAIN_SETTING_11_RX_IF_GAIN_11_BITS   (4)
#define	GAIN_CTRL_MIN_RF   *((volatile int32u *)0x400010A4u)
#define	GAIN_CTRL_MIN_RF_REG   *((volatile int32u *)0x400010A4u)
#define	GAIN_CTRL_MIN_RF_ADDR   (0x400010A4u)
#define	GAIN_CTRL_MIN_RF_RESET   (0x000000F0u)
#define	GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF   (0x000001FFu)
#define	GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_MASK   (0x000001FFu)
#define	GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_BIT   (0)
#define	GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_BITS   (9)
#define	GAIN_CTRL_MAX_RF   *((volatile int32u *)0x400010A8u)
#define	GAIN_CTRL_MAX_RF_REG   *((volatile int32u *)0x400010A8u)
#define	GAIN_CTRL_MAX_RF_ADDR   (0x400010A8u)
#define	GAIN_CTRL_MAX_RF_RESET   (0x000000FCu)
#define	GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF   (0x000001FFu)
#define	GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_MASK   (0x000001FFu)
#define	GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_BIT   (0)
#define	GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_BITS   (9)
#define	MIXER_GAIN_STEP   *((volatile int32u *)0x400010ACu)
#define	MIXER_GAIN_STEP_REG   *((volatile int32u *)0x400010ACu)
#define	MIXER_GAIN_STEP_ADDR   (0x400010ACu)
#define	MIXER_GAIN_STEP_RESET   (0x0000000Cu)
#define	MIXER_GAIN_STEP_MIXER_GAIN_STEP   (0x0000000Fu)
#define	MIXER_GAIN_STEP_MIXER_GAIN_STEP_MASK   (0x0000000Fu)
#define	MIXER_GAIN_STEP_MIXER_GAIN_STEP_BIT   (0)
#define	MIXER_GAIN_STEP_MIXER_GAIN_STEP_BITS   (4)
#define	PREAMBLE_EVENT   *((volatile int32u *)0x400010B0u)
#define	PREAMBLE_EVENT_REG   *((volatile int32u *)0x400010B0u)
#define	PREAMBLE_EVENT_ADDR   (0x400010B0u)
#define	PREAMBLE_EVENT_RESET   (0x00005877u)
#define	PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH   (0x0000FF00u)
#define	PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH_MASK   (0x0000FF00u)
#define	PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH_BIT   (8)
#define	PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH_BITS   (8)
#define	PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH   (0x000000FFu)
#define	PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_MASK   (0x000000FFu)
#define	PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_BIT   (0)
#define	PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_BITS   (8)
#define	PREAMBLE_ABORT_THRESH   *((volatile int32u *)0x400010B4u)
#define	PREAMBLE_ABORT_THRESH_REG   *((volatile int32u *)0x400010B4u)
#define	PREAMBLE_ABORT_THRESH_ADDR   (0x400010B4u)
#define	PREAMBLE_ABORT_THRESH_RESET   (0x00000071u)
#define	PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH   (0x000000FFu)
#define	PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_MASK   (0x000000FFu)
#define	PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_BIT   (0)
#define	PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_BITS   (8)
#define	PREAMBLE_ACCEPT_WINDOW   *((volatile int32u *)0x400010B8u)
#define	PREAMBLE_ACCEPT_WINDOW_REG   *((volatile int32u *)0x400010B8u)
#define	PREAMBLE_ACCEPT_WINDOW_ADDR   (0x400010B8u)
#define	PREAMBLE_ACCEPT_WINDOW_RESET   (0x00000003u)
#define	PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW   (0x0000007Fu)
#define	PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_MASK   (0x0000007Fu)
#define	PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_BIT   (0)
#define	PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_BITS   (7)
#define	CCA_MODE   *((volatile int32u *)0x400010BCu)
#define	CCA_MODE_REG   *((volatile int32u *)0x400010BCu)
#define	CCA_MODE_ADDR   (0x400010BCu)
#define	CCA_MODE_RESET   (0x00000000u)
#define	CCA_MODE_CCA_MODE   (0x00000003u)
#define	CCA_MODE_CCA_MODE_MASK   (0x00000003u)
#define	CCA_MODE_CCA_MODE_BIT   (0)
#define	CCA_MODE_CCA_MODE_BITS   (2)
#define	TX_POWER_MAX   *((volatile int32u *)0x400010C0u)
#define	TX_POWER_MAX_REG   *((volatile int32u *)0x400010C0u)
#define	TX_POWER_MAX_ADDR   (0x400010C0u)
#define	TX_POWER_MAX_RESET   (0x00000000u)
#define	TX_POWER_MAX_MANUAL_POWER   (0x00008000u)
#define	TX_POWER_MAX_MANUAL_POWER_MASK   (0x00008000u)
#define	TX_POWER_MAX_MANUAL_POWER_BIT   (15)
#define	TX_POWER_MAX_MANUAL_POWER_BITS   (1)
#define	TX_POWER_MAX_TX_POWER_MAX   (0x0000001Fu)
#define	TX_POWER_MAX_TX_POWER_MAX_MASK   (0x0000001Fu)
#define	TX_POWER_MAX_TX_POWER_MAX_BIT   (0)
#define	TX_POWER_MAX_TX_POWER_MAX_BITS   (5)
#define	SYNTH_FREQ_H   *((volatile int32u *)0x400010C4u)
#define	SYNTH_FREQ_H_REG   *((volatile int32u *)0x400010C4u)
#define	SYNTH_FREQ_H_ADDR   (0x400010C4u)
#define	SYNTH_FREQ_H_RESET   (0x00000003u)
#define	SYNTH_FREQ_H_SYNTH_FREQ_H   (0x00000003u)
#define	SYNTH_FREQ_H_SYNTH_FREQ_H_MASK   (0x00000003u)
#define	SYNTH_FREQ_H_SYNTH_FREQ_H_BIT   (0)
#define	SYNTH_FREQ_H_SYNTH_FREQ_H_BITS   (2)
#define	SYNTH_FREQ_L   *((volatile int32u *)0x400010C8u)
#define	SYNTH_FREQ_L_REG   *((volatile int32u *)0x400010C8u)
#define	SYNTH_FREQ_L_ADDR   (0x400010C8u)
#define	SYNTH_FREQ_L_RESET   (0x00003800u)
#define	SYNTH_FREQ_L_SYNTH_FREQ_L   (0x0000FFFFu)
#define	SYNTH_FREQ_L_SYNTH_FREQ_L_MASK   (0x0000FFFFu)
#define	SYNTH_FREQ_L_SYNTH_FREQ_L_BIT   (0)
#define	SYNTH_FREQ_L_SYNTH_FREQ_L_BITS   (16)
#define	RSSI_INST   *((volatile int32u *)0x400010CCu)
#define	RSSI_INST_REG   *((volatile int32u *)0x400010CCu)
#define	RSSI_INST_ADDR   (0x400010CCu)
#define	RSSI_INST_RESET   (0x00000000u)
#define	RSSI_INST_NEW_RSSI_INST   (0x00000200u)
#define	RSSI_INST_NEW_RSSI_INST_MASK   (0x00000200u)
#define	RSSI_INST_NEW_RSSI_INST_BIT   (9)
#define	RSSI_INST_NEW_RSSI_INST_BITS   (1)
#define	RSSI_INST_RSSI_INST   (0x000001FFu)
#define	RSSI_INST_RSSI_INST_MASK   (0x000001FFu)
#define	RSSI_INST_RSSI_INST_BIT   (0)
#define	RSSI_INST_RSSI_INST_BITS   (9)
#define	FREQ_MEAS_CTRL1   *((volatile int32u *)0x400010D0u)
#define	FREQ_MEAS_CTRL1_REG   *((volatile int32u *)0x400010D0u)
#define	FREQ_MEAS_CTRL1_ADDR   (0x400010D0u)
#define	FREQ_MEAS_CTRL1_RESET   (0x00000160u)
#define	FREQ_MEAS_CTRL1_AUTO_TUNE_EN   (0x00008000u)
#define	FREQ_MEAS_CTRL1_AUTO_TUNE_EN_MASK   (0x00008000u)
#define	FREQ_MEAS_CTRL1_AUTO_TUNE_EN_BIT   (15)
#define	FREQ_MEAS_CTRL1_AUTO_TUNE_EN_BITS   (1)
#define	FREQ_MEAS_CTRL1_FREQ_MEAS_EN   (0x00004000u)
#define	FREQ_MEAS_CTRL1_FREQ_MEAS_EN_MASK   (0x00004000u)
#define	FREQ_MEAS_CTRL1_FREQ_MEAS_EN_BIT   (14)
#define	FREQ_MEAS_CTRL1_FREQ_MEAS_EN_BITS   (1)
#define	FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL   (0x00002000u)
#define	FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL_MASK   (0x00002000u)
#define	FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL_BIT   (13)
#define	FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL_BITS   (1)
#define	FREQ_MEAS_CTRL1_OPEN_LOOP   (0x00001000u)
#define	FREQ_MEAS_CTRL1_OPEN_LOOP_MASK   (0x00001000u)
#define	FREQ_MEAS_CTRL1_OPEN_LOOP_BIT   (12)
#define	FREQ_MEAS_CTRL1_OPEN_LOOP_BITS   (1)
#define	FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS   (0x00000400u)
#define	FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS_MASK   (0x00000400u)
#define	FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS_BIT   (10)
#define	FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS_BITS   (1)
#define	FREQ_MEAS_CTRL1_DELAY_ALL_MEAS   (0x00000200u)
#define	FREQ_MEAS_CTRL1_DELAY_ALL_MEAS_MASK   (0x00000200u)
#define	FREQ_MEAS_CTRL1_DELAY_ALL_MEAS_BIT   (9)
#define	FREQ_MEAS_CTRL1_DELAY_ALL_MEAS_BITS   (1)
#define	FREQ_MEAS_CTRL1_BIN_SEARCH_MSB   (0x000001C0u)
#define	FREQ_MEAS_CTRL1_BIN_SEARCH_MSB_MASK   (0x000001C0u)
#define	FREQ_MEAS_CTRL1_BIN_SEARCH_MSB_BIT   (6)
#define	FREQ_MEAS_CTRL1_BIN_SEARCH_MSB_BITS   (3)
#define	FREQ_MEAS_CTRL1_TUNE_VCO_INIT   (0x0000003Fu)
#define	FREQ_MEAS_CTRL1_TUNE_VCO_INIT_MASK   (0x0000003Fu)
#define	FREQ_MEAS_CTRL1_TUNE_VCO_INIT_BIT   (0)
#define	FREQ_MEAS_CTRL1_TUNE_VCO_INIT_BITS   (6)
#define	FREQ_MEAS_CTRL2   *((volatile int32u *)0x400010D4u)
#define	FREQ_MEAS_CTRL2_REG   *((volatile int32u *)0x400010D4u)
#define	FREQ_MEAS_CTRL2_ADDR   (0x400010D4u)
#define	FREQ_MEAS_CTRL2_RESET   (0x0000201Eu)
#define	FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER   (0x0000FF00u)
#define	FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER_MASK   (0x0000FF00u)
#define	FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER_BIT   (8)
#define	FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER_BITS   (8)
#define	FREQ_MEAS_CTRL2_TARGET_PERIOD   (0x000000FFu)
#define	FREQ_MEAS_CTRL2_TARGET_PERIOD_MASK   (0x000000FFu)
#define	FREQ_MEAS_CTRL2_TARGET_PERIOD_BIT   (0)
#define	FREQ_MEAS_CTRL2_TARGET_PERIOD_BITS   (8)
#define	FREQ_MEAS_SHIFT   *((volatile int32u *)0x400010D8u)
#define	FREQ_MEAS_SHIFT_REG   *((volatile int32u *)0x400010D8u)
#define	FREQ_MEAS_SHIFT_ADDR   (0x400010D8u)
#define	FREQ_MEAS_SHIFT_RESET   (0x00000035u)
#define	FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT   (0x000000FFu)
#define	FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_MASK   (0x000000FFu)
#define	FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_BIT   (0)
#define	FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_BITS   (8)
#define	FREQ_MEAS_STATUS1   *((volatile int32u *)0x400010DCu)
#define	FREQ_MEAS_STATUS1_REG   *((volatile int32u *)0x400010DCu)
#define	FREQ_MEAS_STATUS1_ADDR   (0x400010DCu)
#define	FREQ_MEAS_STATUS1_RESET   (0x00000000u)
#define	FREQ_MEAS_STATUS1_INVALID_EDGE   (0x00008000u)
#define	FREQ_MEAS_STATUS1_INVALID_EDGE_MASK   (0x00008000u)
#define	FREQ_MEAS_STATUS1_INVALID_EDGE_BIT   (15)
#define	FREQ_MEAS_STATUS1_INVALID_EDGE_BITS   (1)
#define	FREQ_MEAS_STATUS1_SIGN_FOUND   (0x00004000u)
#define	FREQ_MEAS_STATUS1_SIGN_FOUND_MASK   (0x00004000u)
#define	FREQ_MEAS_STATUS1_SIGN_FOUND_BIT   (14)
#define	FREQ_MEAS_STATUS1_SIGN_FOUND_BITS   (1)
#define	FREQ_MEAS_STATUS1_FREQ_SIGN   (0x00002000u)
#define	FREQ_MEAS_STATUS1_FREQ_SIGN_MASK   (0x00002000u)
#define	FREQ_MEAS_STATUS1_FREQ_SIGN_BIT   (13)
#define	FREQ_MEAS_STATUS1_FREQ_SIGN_BITS   (1)
#define	FREQ_MEAS_STATUS1_PERIOD_FOUND   (0x00001000u)
#define	FREQ_MEAS_STATUS1_PERIOD_FOUND_MASK   (0x00001000u)
#define	FREQ_MEAS_STATUS1_PERIOD_FOUND_BIT   (12)
#define	FREQ_MEAS_STATUS1_PERIOD_FOUND_BITS   (1)
#define	FREQ_MEAS_STATUS1_NEAREST_DIFF   (0x000003FFu)
#define	FREQ_MEAS_STATUS1_NEAREST_DIFF_MASK   (0x000003FFu)
#define	FREQ_MEAS_STATUS1_NEAREST_DIFF_BIT   (0)
#define	FREQ_MEAS_STATUS1_NEAREST_DIFF_BITS   (10)
#define	FREQ_MEAS_STATUS2   *((volatile int32u *)0x400010E0u)
#define	FREQ_MEAS_STATUS2_REG   *((volatile int32u *)0x400010E0u)
#define	FREQ_MEAS_STATUS2_ADDR   (0x400010E0u)
#define	FREQ_MEAS_STATUS2_RESET   (0x00000000u)
#define	FREQ_MEAS_STATUS2_BEAT_TIMER   (0x0000FFC0u)
#define	FREQ_MEAS_STATUS2_BEAT_TIMER_MASK   (0x0000FFC0u)
#define	FREQ_MEAS_STATUS2_BEAT_TIMER_BIT   (6)
#define	FREQ_MEAS_STATUS2_BEAT_TIMER_BITS   (10)
#define	FREQ_MEAS_STATUS2_BEATS   (0x0000003Fu)
#define	FREQ_MEAS_STATUS2_BEATS_MASK   (0x0000003Fu)
#define	FREQ_MEAS_STATUS2_BEATS_BIT   (0)
#define	FREQ_MEAS_STATUS2_BEATS_BITS   (6)
#define	FREQ_MEAS_STATUS3   *((volatile int32u *)0x400010E4u)
#define	FREQ_MEAS_STATUS3_REG   *((volatile int32u *)0x400010E4u)
#define	FREQ_MEAS_STATUS3_ADDR   (0x400010E4u)
#define	FREQ_MEAS_STATUS3_RESET   (0x00000020u)
#define	FREQ_MEAS_STATUS3_TUNE_VCO   (0x0000003Fu)
#define	FREQ_MEAS_STATUS3_TUNE_VCO_MASK   (0x0000003Fu)
#define	FREQ_MEAS_STATUS3_TUNE_VCO_BIT   (0)
#define	FREQ_MEAS_STATUS3_TUNE_VCO_BITS   (6)
#define	SCR_CTRL   *((volatile int32u *)0x400010E8u)
#define	SCR_CTRL_REG   *((volatile int32u *)0x400010E8u)
#define	SCR_CTRL_ADDR   (0x400010E8u)
#define	SCR_CTRL_RESET   (0x00000004u)
#define	SCR_CTRL_SCR_RESET   (0x00000004u)
#define	SCR_CTRL_SCR_RESET_MASK   (0x00000004u)
#define	SCR_CTRL_SCR_RESET_BIT   (2)
#define	SCR_CTRL_SCR_RESET_BITS   (1)
#define	SCR_CTRL_SCR_WRITE   (0x00000002u)
#define	SCR_CTRL_SCR_WRITE_MASK   (0x00000002u)
#define	SCR_CTRL_SCR_WRITE_BIT   (1)
#define	SCR_CTRL_SCR_WRITE_BITS   (1)
#define	SCR_CTRL_SCR_READ   (0x00000001u)
#define	SCR_CTRL_SCR_READ_MASK   (0x00000001u)
#define	SCR_CTRL_SCR_READ_BIT   (0)
#define	SCR_CTRL_SCR_READ_BITS   (1)
#define	SCR_BUSY   *((volatile int32u *)0x400010ECu)
#define	SCR_BUSY_REG   *((volatile int32u *)0x400010ECu)
#define	SCR_BUSY_ADDR   (0x400010ECu)
#define	SCR_BUSY_RESET   (0x00000000u)
#define	SCR_BUSY_SCR_BUSY   (0x00000001u)
#define	SCR_BUSY_SCR_BUSY_MASK   (0x00000001u)
#define	SCR_BUSY_SCR_BUSY_BIT   (0)
#define	SCR_BUSY_SCR_BUSY_BITS   (1)
#define	SCR_ADDR   *((volatile int32u *)0x400010F0u)
#define	SCR_ADDR_REG   *((volatile int32u *)0x400010F0u)
#define	SCR_ADDR_ADDR   (0x400010F0u)
#define	SCR_ADDR_RESET   (0x00000000u)
#define	SCR_ADDR_SCR_ADDR   (0x000000FFu)
#define	SCR_ADDR_SCR_ADDR_MASK   (0x000000FFu)
#define	SCR_ADDR_SCR_ADDR_BIT   (0)
#define	SCR_ADDR_SCR_ADDR_BITS   (8)
#define	SCR_WRITE   *((volatile int32u *)0x400010F4u)
#define	SCR_WRITE_REG   *((volatile int32u *)0x400010F4u)
#define	SCR_WRITE_ADDR   (0x400010F4u)
#define	SCR_WRITE_RESET   (0x00000000u)
#define	SCR_WRITE_SCR_WRITE   (0x0000FFFFu)
#define	SCR_WRITE_SCR_WRITE_MASK   (0x0000FFFFu)
#define	SCR_WRITE_SCR_WRITE_BIT   (0)
#define	SCR_WRITE_SCR_WRITE_BITS   (16)
#define	SCR_READ   *((volatile int32u *)0x400010F8u)
#define	SCR_READ_REG   *((volatile int32u *)0x400010F8u)
#define	SCR_READ_ADDR   (0x400010F8u)
#define	SCR_READ_RESET   (0x00000000u)
#define	SCR_READ_SCR_READ   (0x0000FFFFu)
#define	SCR_READ_SCR_READ_MASK   (0x0000FFFFu)
#define	SCR_READ_SCR_READ_BIT   (0)
#define	SCR_READ_SCR_READ_BITS   (16)
#define	SYNTH_LOCK   *((volatile int32u *)0x400010FCu)
#define	SYNTH_LOCK_REG   *((volatile int32u *)0x400010FCu)
#define	SYNTH_LOCK_ADDR   (0x400010FCu)
#define	SYNTH_LOCK_RESET   (0x00000000u)
#define	SYNTH_LOCK_IN_LOCK   (0x00000001u)
#define	SYNTH_LOCK_IN_LOCK_MASK   (0x00000001u)
#define	SYNTH_LOCK_IN_LOCK_BIT   (0)
#define	SYNTH_LOCK_IN_LOCK_BITS   (1)
#define	AN_CAL_STATUS   *((volatile int32u *)0x40001100u)
#define	AN_CAL_STATUS_REG   *((volatile int32u *)0x40001100u)
#define	AN_CAL_STATUS_ADDR   (0x40001100u)
#define	AN_CAL_STATUS_RESET   (0x00000000u)
#define	AN_CAL_STATUS_VCO_CTRL   (0x0000000Cu)
#define	AN_CAL_STATUS_VCO_CTRL_MASK   (0x0000000Cu)
#define	AN_CAL_STATUS_VCO_CTRL_BIT   (2)
#define	AN_CAL_STATUS_VCO_CTRL_BITS   (2)
#define	BIAS_CAL_STATUS   *((volatile int32u *)0x40001104u)
#define	BIAS_CAL_STATUS_REG   *((volatile int32u *)0x40001104u)
#define	BIAS_CAL_STATUS_ADDR   (0x40001104u)
#define	BIAS_CAL_STATUS_RESET   (0x00000000u)
#define	BIAS_CAL_STATUS_VCOMP   (0x00000002u)
#define	BIAS_CAL_STATUS_VCOMP_MASK   (0x00000002u)
#define	BIAS_CAL_STATUS_VCOMP_BIT   (1)
#define	BIAS_CAL_STATUS_VCOMP_BITS   (1)
#define	BIAS_CAL_STATUS_ICOMP   (0x00000001u)
#define	BIAS_CAL_STATUS_ICOMP_MASK   (0x00000001u)
#define	BIAS_CAL_STATUS_ICOMP_BIT   (0)
#define	BIAS_CAL_STATUS_ICOMP_BITS   (1)
#define	ATEST_SEL   *((volatile int32u *)0x40001108u)
#define	ATEST_SEL_REG   *((volatile int32u *)0x40001108u)
#define	ATEST_SEL_ADDR   (0x40001108u)
#define	ATEST_SEL_RESET   (0x00000000u)
#define	ATEST_SEL_ATEST_CTRL   (0x0000FF00u)
#define	ATEST_SEL_ATEST_CTRL_MASK   (0x0000FF00u)
#define	ATEST_SEL_ATEST_CTRL_BIT   (8)
#define	ATEST_SEL_ATEST_CTRL_BITS   (8)
#define	ATEST_SEL_ATEST_SEL   (0x0000001Fu)
#define	ATEST_SEL_ATEST_SEL_MASK   (0x0000001Fu)
#define	ATEST_SEL_ATEST_SEL_BIT   (0)
#define	ATEST_SEL_ATEST_SEL_BITS   (5)
#define	AN_EN_TEST   *((volatile int32u *)0x4000110Cu)
#define	AN_EN_TEST_REG   *((volatile int32u *)0x4000110Cu)
#define	AN_EN_TEST_ADDR   (0x4000110Cu)
#define	AN_EN_TEST_RESET   (0x00000000u)
#define	AN_EN_TEST_AN_TEST_MODE   (0x00008000u)
#define	AN_EN_TEST_AN_TEST_MODE_MASK   (0x00008000u)
#define	AN_EN_TEST_AN_TEST_MODE_BIT   (15)
#define	AN_EN_TEST_AN_TEST_MODE_BITS   (1)
#define	AN_EN_TEST_PFD_EN   (0x00004000u)
#define	AN_EN_TEST_PFD_EN_MASK   (0x00004000u)
#define	AN_EN_TEST_PFD_EN_BIT   (14)
#define	AN_EN_TEST_PFD_EN_BITS   (1)
#define	AN_EN_TEST_ADC_EN   (0x00002000u)
#define	AN_EN_TEST_ADC_EN_MASK   (0x00002000u)
#define	AN_EN_TEST_ADC_EN_BIT   (13)
#define	AN_EN_TEST_ADC_EN_BITS   (1)
#define	AN_EN_TEST_UNUSED   (0x00001000u)
#define	AN_EN_TEST_UNUSED_MASK   (0x00001000u)
#define	AN_EN_TEST_UNUSED_BIT   (12)
#define	AN_EN_TEST_UNUSED_BITS   (1)
#define	AN_EN_TEST_PRE_FILT_EN   (0x00000800u)
#define	AN_EN_TEST_PRE_FILT_EN_MASK   (0x00000800u)
#define	AN_EN_TEST_PRE_FILT_EN_BIT   (11)
#define	AN_EN_TEST_PRE_FILT_EN_BITS   (1)
#define	AN_EN_TEST_IF_AMP_EN   (0x00000400u)
#define	AN_EN_TEST_IF_AMP_EN_MASK   (0x00000400u)
#define	AN_EN_TEST_IF_AMP_EN_BIT   (10)
#define	AN_EN_TEST_IF_AMP_EN_BITS   (1)
#define	AN_EN_TEST_LNA_EN   (0x00000200u)
#define	AN_EN_TEST_LNA_EN_MASK   (0x00000200u)
#define	AN_EN_TEST_LNA_EN_BIT   (9)
#define	AN_EN_TEST_LNA_EN_BITS   (1)
#define	AN_EN_TEST_MIXER_EN   (0x00000100u)
#define	AN_EN_TEST_MIXER_EN_MASK   (0x00000100u)
#define	AN_EN_TEST_MIXER_EN_BIT   (8)
#define	AN_EN_TEST_MIXER_EN_BITS   (1)
#define	AN_EN_TEST_CH_FILT_EN   (0x00000080u)
#define	AN_EN_TEST_CH_FILT_EN_MASK   (0x00000080u)
#define	AN_EN_TEST_CH_FILT_EN_BIT   (7)
#define	AN_EN_TEST_CH_FILT_EN_BITS   (1)
#define	AN_EN_TEST_MOD_DAC_EN   (0x00000040u)
#define	AN_EN_TEST_MOD_DAC_EN_MASK   (0x00000040u)
#define	AN_EN_TEST_MOD_DAC_EN_BIT   (6)
#define	AN_EN_TEST_MOD_DAC_EN_BITS   (1)
#define	AN_EN_TEST_PA_EN   (0x00000010u)
#define	AN_EN_TEST_PA_EN_MASK   (0x00000010u)
#define	AN_EN_TEST_PA_EN_BIT   (4)
#define	AN_EN_TEST_PA_EN_BITS   (1)
#define	AN_EN_TEST_PRESCALER_EN   (0x00000008u)
#define	AN_EN_TEST_PRESCALER_EN_MASK   (0x00000008u)
#define	AN_EN_TEST_PRESCALER_EN_BIT   (3)
#define	AN_EN_TEST_PRESCALER_EN_BITS   (1)
#define	AN_EN_TEST_VCO_EN   (0x00000004u)
#define	AN_EN_TEST_VCO_EN_MASK   (0x00000004u)
#define	AN_EN_TEST_VCO_EN_BIT   (2)
#define	AN_EN_TEST_VCO_EN_BITS   (1)
#define	AN_EN_TEST_BIAS_EN   (0x00000001u)
#define	AN_EN_TEST_BIAS_EN_MASK   (0x00000001u)
#define	AN_EN_TEST_BIAS_EN_BIT   (0)
#define	AN_EN_TEST_BIAS_EN_BITS   (1)
#define	TUNE_FILTER_CTRL   *((volatile int32u *)0x40001110u)
#define	TUNE_FILTER_CTRL_REG   *((volatile int32u *)0x40001110u)
#define	TUNE_FILTER_CTRL_ADDR   (0x40001110u)
#define	TUNE_FILTER_CTRL_RESET   (0x00000000u)
#define	TUNE_FILTER_CTRL_TUNE_FILTER_EN   (0x00000002u)
#define	TUNE_FILTER_CTRL_TUNE_FILTER_EN_MASK   (0x00000002u)
#define	TUNE_FILTER_CTRL_TUNE_FILTER_EN_BIT   (1)
#define	TUNE_FILTER_CTRL_TUNE_FILTER_EN_BITS   (1)
#define	TUNE_FILTER_CTRL_TUNE_FILTER_RESET   (0x00000001u)
#define	TUNE_FILTER_CTRL_TUNE_FILTER_RESET_MASK   (0x00000001u)
#define	TUNE_FILTER_CTRL_TUNE_FILTER_RESET_BIT   (0)
#define	TUNE_FILTER_CTRL_TUNE_FILTER_RESET_BITS   (1)
#define	NOISE_EN   *((volatile int32u *)0x40001114u)
#define	NOISE_EN_REG   *((volatile int32u *)0x40001114u)
#define	NOISE_EN_ADDR   (0x40001114u)
#define	NOISE_EN_RESET   (0x00000000u)
#define	NOISE_EN_NOISE_EN   (0x00000001u)
#define	NOISE_EN_NOISE_EN_MASK   (0x00000001u)
#define	NOISE_EN_NOISE_EN_BIT   (0)
#define	NOISE_EN_NOISE_EN_BITS   (1)
#define	DATA_MAC_BASE   (0x40002000u)
#define	DATA_MAC_END   (0x400020C8u)
#define	DATA_MAC_SIZE   (DATA_MAC_END - DATA_MAC_BASE + 1)
#define	MAC_RX_ST_ADDR_A   *((volatile int32u *)0x40002000u)
#define	MAC_RX_ST_ADDR_A_REG   *((volatile int32u *)0x40002000u)
#define	MAC_RX_ST_ADDR_A_ADDR   (0x40002000u)
#define	MAC_RX_ST_ADDR_A_RESET   (0x20000000u)
#define	MAC_RX_ST_ADDR_A_MAC_RAM_OFFS   (0xFFFFE000u)
#define	MAC_RX_ST_ADDR_A_MAC_RAM_OFFS_MASK   (0xFFFFE000u)
#define	MAC_RX_ST_ADDR_A_MAC_RAM_OFFS_BIT   (13)
#define	MAC_RX_ST_ADDR_A_MAC_RAM_OFFS_BITS   (19)
#define	MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A   (0x00001FFEu)
#define	MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_MASK   (0x00001FFEu)
#define	MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_BIT   (1)
#define	MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_BITS   (12)
#define	MAC_RX_END_ADDR_A   *((volatile int32u *)0x40002004u)
#define	MAC_RX_END_ADDR_A_REG   *((volatile int32u *)0x40002004u)
#define	MAC_RX_END_ADDR_A_ADDR   (0x40002004u)
#define	MAC_RX_END_ADDR_A_RESET   (0x20000088u)
#define	MAC_RX_END_ADDR_A_MAC_RAM_OFFS   (0xFFFFE000u)
#define	MAC_RX_END_ADDR_A_MAC_RAM_OFFS_MASK   (0xFFFFE000u)
#define	MAC_RX_END_ADDR_A_MAC_RAM_OFFS_BIT   (13)
#define	MAC_RX_END_ADDR_A_MAC_RAM_OFFS_BITS   (19)
#define	MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A   (0x00001FFEu)
#define	MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_MASK   (0x00001FFEu)
#define	MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_BIT   (1)
#define	MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_BITS   (12)
#define	MAC_RX_ST_ADDR_B   *((volatile int32u *)0x40002008u)
#define	MAC_RX_ST_ADDR_B_REG   *((volatile int32u *)0x40002008u)
#define	MAC_RX_ST_ADDR_B_ADDR   (0x40002008u)
#define	MAC_RX_ST_ADDR_B_RESET   (0x20000000u)
#define	MAC_RX_ST_ADDR_B_MAC_RAM_OFFS   (0xFFFFE000u)
#define	MAC_RX_ST_ADDR_B_MAC_RAM_OFFS_MASK   (0xFFFFE000u)
#define	MAC_RX_ST_ADDR_B_MAC_RAM_OFFS_BIT   (13)
#define	MAC_RX_ST_ADDR_B_MAC_RAM_OFFS_BITS   (19)
#define	MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B   (0x00001FFEu)
#define	MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_MASK   (0x00001FFEu)
#define	MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_BIT   (1)
#define	MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_BITS   (12)
#define	MAC_RX_END_ADDR_B   *((volatile int32u *)0x4000200Cu)
#define	MAC_RX_END_ADDR_B_REG   *((volatile int32u *)0x4000200Cu)
#define	MAC_RX_END_ADDR_B_ADDR   (0x4000200Cu)
#define	MAC_RX_END_ADDR_B_RESET   (0x20000088u)
#define	MAC_RX_END_ADDR_B_MAC_RAM_OFFS   (0xFFFFE000u)
#define	MAC_RX_END_ADDR_B_MAC_RAM_OFFS_MASK   (0xFFFFE000u)
#define	MAC_RX_END_ADDR_B_MAC_RAM_OFFS_BIT   (13)
#define	MAC_RX_END_ADDR_B_MAC_RAM_OFFS_BITS   (19)
#define	MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B   (0x00001FFEu)
#define	MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_MASK   (0x00001FFEu)
#define	MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_BIT   (1)
#define	MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_BITS   (12)
#define	MAC_TX_ST_ADDR_A   *((volatile int32u *)0x40002010u)
#define	MAC_TX_ST_ADDR_A_REG   *((volatile int32u *)0x40002010u)
#define	MAC_TX_ST_ADDR_A_ADDR   (0x40002010u)
#define	MAC_TX_ST_ADDR_A_RESET   (0x20000000u)
#define	MAC_TX_ST_ADDR_A_MAC_RAM_OFFS   (0xFFFFE000u)
#define	MAC_TX_ST_ADDR_A_MAC_RAM_OFFS_MASK   (0xFFFFE000u)
#define	MAC_TX_ST_ADDR_A_MAC_RAM_OFFS_BIT   (13)
#define	MAC_TX_ST_ADDR_A_MAC_RAM_OFFS_BITS   (19)
#define	MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A   (0x00001FFEu)
#define	MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_MASK   (0x00001FFEu)
#define	MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_BIT   (1)
#define	MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_BITS   (12)
#define	MAC_TX_END_ADDR_A   *((volatile int32u *)0x40002014u)
#define	MAC_TX_END_ADDR_A_REG   *((volatile int32u *)0x40002014u)
#define	MAC_TX_END_ADDR_A_ADDR   (0x40002014u)
#define	MAC_TX_END_ADDR_A_RESET   (0x20000000u)
#define	MAC_TX_END_ADDR_A_MAC_RAM_OFFS   (0xFFFFE000u)
#define	MAC_TX_END_ADDR_A_MAC_RAM_OFFS_MASK   (0xFFFFE000u)
#define	MAC_TX_END_ADDR_A_MAC_RAM_OFFS_BIT   (13)
#define	MAC_TX_END_ADDR_A_MAC_RAM_OFFS_BITS   (19)
#define	MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A   (0x00001FFEu)
#define	MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_MASK   (0x00001FFEu)
#define	MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_BIT   (1)
#define	MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_BITS   (12)
#define	MAC_TX_ST_ADDR_B   *((volatile int32u *)0x40002018u)
#define	MAC_TX_ST_ADDR_B_REG   *((volatile int32u *)0x40002018u)
#define	MAC_TX_ST_ADDR_B_ADDR   (0x40002018u)
#define	MAC_TX_ST_ADDR_B_RESET   (0x20000000u)
#define	MAC_TX_ST_ADDR_B_MAC_RAM_OFFS   (0xFFFFE000u)
#define	MAC_TX_ST_ADDR_B_MAC_RAM_OFFS_MASK   (0xFFFFE000u)
#define	MAC_TX_ST_ADDR_B_MAC_RAM_OFFS_BIT   (13)
#define	MAC_TX_ST_ADDR_B_MAC_RAM_OFFS_BITS   (19)
#define	MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B   (0x00001FFEu)
#define	MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_MASK   (0x00001FFEu)
#define	MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_BIT   (1)
#define	MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_BITS   (12)
#define	MAC_TX_END_ADDR_B   *((volatile int32u *)0x4000201Cu)
#define	MAC_TX_END_ADDR_B_REG   *((volatile int32u *)0x4000201Cu)
#define	MAC_TX_END_ADDR_B_ADDR   (0x4000201Cu)
#define	MAC_TX_END_ADDR_B_RESET   (0x20000000u)
#define	MAC_TX_END_ADDR_B_MAC_RAM_OFFS   (0xFFFFE000u)
#define	MAC_TX_END_ADDR_B_MAC_RAM_OFFS_MASK   (0xFFFFE000u)
#define	MAC_TX_END_ADDR_B_MAC_RAM_OFFS_BIT   (13)
#define	MAC_TX_END_ADDR_B_MAC_RAM_OFFS_BITS   (19)
#define	MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B   (0x00001FFEu)
#define	MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_MASK   (0x00001FFEu)
#define	MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_BIT   (1)
#define	MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_BITS   (12)
#define	RX_A_COUNT   *((volatile int32u *)0x40002020u)
#define	RX_A_COUNT_REG   *((volatile int32u *)0x40002020u)
#define	RX_A_COUNT_ADDR   (0x40002020u)
#define	RX_A_COUNT_RESET   (0x00000000u)
#define	RX_A_COUNT_RX_A_COUNT   (0x000007FFu)
#define	RX_A_COUNT_RX_A_COUNT_MASK   (0x000007FFu)
#define	RX_A_COUNT_RX_A_COUNT_BIT   (0)
#define	RX_A_COUNT_RX_A_COUNT_BITS   (11)
#define	RX_B_COUNT   *((volatile int32u *)0x40002024u)
#define	RX_B_COUNT_REG   *((volatile int32u *)0x40002024u)
#define	RX_B_COUNT_ADDR   (0x40002024u)
#define	RX_B_COUNT_RESET   (0x00000000u)
#define	RX_B_COUNT_RX_B_COUNT   (0x000007FFu)
#define	RX_B_COUNT_RX_B_COUNT_MASK   (0x000007FFu)
#define	RX_B_COUNT_RX_B_COUNT_BIT   (0)
#define	RX_B_COUNT_RX_B_COUNT_BITS   (11)
#define	TX_COUNT   *((volatile int32u *)0x40002028u)
#define	TX_COUNT_REG   *((volatile int32u *)0x40002028u)
#define	TX_COUNT_ADDR   (0x40002028u)
#define	TX_COUNT_RESET   (0x00000000u)
#define	TX_COUNT_TX_COUNT   (0x000007FFu)
#define	TX_COUNT_TX_COUNT_MASK   (0x000007FFu)
#define	TX_COUNT_TX_COUNT_BIT   (0)
#define	TX_COUNT_TX_COUNT_BITS   (11)
#define	MAC_DMA_STATUS   *((volatile int32u *)0x4000202Cu)
#define	MAC_DMA_STATUS_REG   *((volatile int32u *)0x4000202Cu)
#define	MAC_DMA_STATUS_ADDR   (0x4000202Cu)
#define	MAC_DMA_STATUS_RESET   (0x00000000u)
#define	MAC_DMA_STATUS_TX_ACTIVE_B   (0x00000008u)
#define	MAC_DMA_STATUS_TX_ACTIVE_B_MASK   (0x00000008u)
#define	MAC_DMA_STATUS_TX_ACTIVE_B_BIT   (3)
#define	MAC_DMA_STATUS_TX_ACTIVE_B_BITS   (1)
#define	MAC_DMA_STATUS_TX_ACTIVE_A   (0x00000004u)
#define	MAC_DMA_STATUS_TX_ACTIVE_A_MASK   (0x00000004u)
#define	MAC_DMA_STATUS_TX_ACTIVE_A_BIT   (2)
#define	MAC_DMA_STATUS_TX_ACTIVE_A_BITS   (1)
#define	MAC_DMA_STATUS_RX_ACTIVE_B   (0x00000002u)
#define	MAC_DMA_STATUS_RX_ACTIVE_B_MASK   (0x00000002u)
#define	MAC_DMA_STATUS_RX_ACTIVE_B_BIT   (1)
#define	MAC_DMA_STATUS_RX_ACTIVE_B_BITS   (1)
#define	MAC_DMA_STATUS_RX_ACTIVE_A   (0x00000001u)
#define	MAC_DMA_STATUS_RX_ACTIVE_A_MASK   (0x00000001u)
#define	MAC_DMA_STATUS_RX_ACTIVE_A_BIT   (0)
#define	MAC_DMA_STATUS_RX_ACTIVE_A_BITS   (1)
#define	MAC_DMA_CONFIG   *((volatile int32u *)0x40002030u)
#define	MAC_DMA_CONFIG_REG   *((volatile int32u *)0x40002030u)
#define	MAC_DMA_CONFIG_ADDR   (0x40002030u)
#define	MAC_DMA_CONFIG_RESET   (0x00000000u)
#define	MAC_DMA_CONFIG_TX_DMA_RESET   (0x00000020u)
#define	MAC_DMA_CONFIG_TX_DMA_RESET_MASK   (0x00000020u)
#define	MAC_DMA_CONFIG_TX_DMA_RESET_BIT   (5)
#define	MAC_DMA_CONFIG_TX_DMA_RESET_BITS   (1)
#define	MAC_DMA_CONFIG_RX_DMA_RESET   (0x00000010u)
#define	MAC_DMA_CONFIG_RX_DMA_RESET_MASK   (0x00000010u)
#define	MAC_DMA_CONFIG_RX_DMA_RESET_BIT   (4)
#define	MAC_DMA_CONFIG_RX_DMA_RESET_BITS   (1)
#define	MAC_DMA_CONFIG_TX_LOAD_B   (0x00000008u)
#define	MAC_DMA_CONFIG_TX_LOAD_B_MASK   (0x00000008u)
#define	MAC_DMA_CONFIG_TX_LOAD_B_BIT   (3)
#define	MAC_DMA_CONFIG_TX_LOAD_B_BITS   (1)
#define	MAC_DMA_CONFIG_TX_LOAD_A   (0x00000004u)
#define	MAC_DMA_CONFIG_TX_LOAD_A_MASK   (0x00000004u)
#define	MAC_DMA_CONFIG_TX_LOAD_A_BIT   (2)
#define	MAC_DMA_CONFIG_TX_LOAD_A_BITS   (1)
#define	MAC_DMA_CONFIG_RX_LOAD_B   (0x00000002u)
#define	MAC_DMA_CONFIG_RX_LOAD_B_MASK   (0x00000002u)
#define	MAC_DMA_CONFIG_RX_LOAD_B_BIT   (1)
#define	MAC_DMA_CONFIG_RX_LOAD_B_BITS   (1)
#define	MAC_DMA_CONFIG_RX_LOAD_A   (0x00000001u)
#define	MAC_DMA_CONFIG_RX_LOAD_A_MASK   (0x00000001u)
#define	MAC_DMA_CONFIG_RX_LOAD_A_BIT   (0)
#define	MAC_DMA_CONFIG_RX_LOAD_A_BITS   (1)
#define	MAC_TIMER   *((volatile int32u *)0x40002038u)
#define	MAC_TIMER_REG   *((volatile int32u *)0x40002038u)
#define	MAC_TIMER_ADDR   (0x40002038u)
#define	MAC_TIMER_RESET   (0x00000000u)
#define	MAC_TIMER_MAC_TIMER   (0x000FFFFFu)
#define	MAC_TIMER_MAC_TIMER_MASK   (0x000FFFFFu)
#define	MAC_TIMER_MAC_TIMER_BIT   (0)
#define	MAC_TIMER_MAC_TIMER_BITS   (20)
#define	MAC_TIMER_COMPARE_A_H   *((volatile int32u *)0x40002040u)
#define	MAC_TIMER_COMPARE_A_H_REG   *((volatile int32u *)0x40002040u)
#define	MAC_TIMER_COMPARE_A_H_ADDR   (0x40002040u)
#define	MAC_TIMER_COMPARE_A_H_RESET   (0x00000000u)
#define	MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H   (0x0000000Fu)
#define	MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_MASK   (0x0000000Fu)
#define	MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_BIT   (0)
#define	MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_BITS   (4)
#define	MAC_TIMER_COMPARE_A_L   *((volatile int32u *)0x40002044u)
#define	MAC_TIMER_COMPARE_A_L_REG   *((volatile int32u *)0x40002044u)
#define	MAC_TIMER_COMPARE_A_L_ADDR   (0x40002044u)
#define	MAC_TIMER_COMPARE_A_L_RESET   (0x00000000u)
#define	MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L   (0x0000FFFFu)
#define	MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_MASK   (0x0000FFFFu)
#define	MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_BIT   (0)
#define	MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_BITS   (16)
#define	MAC_TIMER_COMPARE_B_H   *((volatile int32u *)0x40002048u)
#define	MAC_TIMER_COMPARE_B_H_REG   *((volatile int32u *)0x40002048u)
#define	MAC_TIMER_COMPARE_B_H_ADDR   (0x40002048u)
#define	MAC_TIMER_COMPARE_B_H_RESET   (0x00000000u)
#define	MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H   (0x0000000Fu)
#define	MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_MASK   (0x0000000Fu)
#define	MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_BIT   (0)
#define	MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_BITS   (4)
#define	MAC_TIMER_COMPARE_B_L   *((volatile int32u *)0x4000204Cu)
#define	MAC_TIMER_COMPARE_B_L_REG   *((volatile int32u *)0x4000204Cu)
#define	MAC_TIMER_COMPARE_B_L_ADDR   (0x4000204Cu)
#define	MAC_TIMER_COMPARE_B_L_RESET   (0x00000000u)
#define	MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L   (0x0000FFFFu)
#define	MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_MASK   (0x0000FFFFu)
#define	MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_BIT   (0)
#define	MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_BITS   (16)
#define	MAC_TIMER_CAPTURE_H   *((volatile int32u *)0x40002050u)
#define	MAC_TIMER_CAPTURE_H_REG   *((volatile int32u *)0x40002050u)
#define	MAC_TIMER_CAPTURE_H_ADDR   (0x40002050u)
#define	MAC_TIMER_CAPTURE_H_RESET   (0x00000000u)
#define	MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH   (0x0000000Fu)
#define	MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_MASK   (0x0000000Fu)
#define	MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_BIT   (0)
#define	MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_BITS   (4)
#define	MAC_TIMER_CAPTURE_L   *((volatile int32u *)0x40002054u)
#define	MAC_TIMER_CAPTURE_L_REG   *((volatile int32u *)0x40002054u)
#define	MAC_TIMER_CAPTURE_L_ADDR   (0x40002054u)
#define	MAC_TIMER_CAPTURE_L_RESET   (0x00000000u)
#define	MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW   (0x0000FFFFu)
#define	MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_MASK   (0x0000FFFFu)
#define	MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_BIT   (0)
#define	MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_BITS   (16)
#define	MAC_BO_TIMER   *((volatile int32u *)0x40002058u)
#define	MAC_BO_TIMER_REG   *((volatile int32u *)0x40002058u)
#define	MAC_BO_TIMER_ADDR   (0x40002058u)
#define	MAC_BO_TIMER_RESET   (0x00000000u)
#define	MAC_BO_TIMER_MAC_BO_TIMER   (0x00000FFFu)
#define	MAC_BO_TIMER_MAC_BO_TIMER_MASK   (0x00000FFFu)
#define	MAC_BO_TIMER_MAC_BO_TIMER_BIT   (0)
#define	MAC_BO_TIMER_MAC_BO_TIMER_BITS   (12)
#define	MAC_BOP_TIMER   *((volatile int32u *)0x4000205Cu)
#define	MAC_BOP_TIMER_REG   *((volatile int32u *)0x4000205Cu)
#define	MAC_BOP_TIMER_ADDR   (0x4000205Cu)
#define	MAC_BOP_TIMER_RESET   (0x00000000u)
#define	MAC_BOP_TIMER_MAC_BOP_TIMER   (0x0000007Fu)
#define	MAC_BOP_TIMER_MAC_BOP_TIMER_MASK   (0x0000007Fu)
#define	MAC_BOP_TIMER_MAC_BOP_TIMER_BIT   (0)
#define	MAC_BOP_TIMER_MAC_BOP_TIMER_BITS   (7)
#define	MAC_TX_STROBE   *((volatile int32u *)0x40002060u)
#define	MAC_TX_STROBE_REG   *((volatile int32u *)0x40002060u)
#define	MAC_TX_STROBE_ADDR   (0x40002060u)
#define	MAC_TX_STROBE_RESET   (0x00000000u)
#define	MAC_TX_STROBE_AUTO_CRC_TX   (0x00000008u)
#define	MAC_TX_STROBE_AUTO_CRC_TX_MASK   (0x00000008u)
#define	MAC_TX_STROBE_AUTO_CRC_TX_BIT   (3)
#define	MAC_TX_STROBE_AUTO_CRC_TX_BITS   (1)
#define	MAC_TX_STROBE_CCA_ON   (0x00000004u)
#define	MAC_TX_STROBE_CCA_ON_MASK   (0x00000004u)
#define	MAC_TX_STROBE_CCA_ON_BIT   (2)
#define	MAC_TX_STROBE_CCA_ON_BITS   (1)
#define	MAC_TX_STROBE_MAC_TX_RST   (0x00000002u)
#define	MAC_TX_STROBE_MAC_TX_RST_MASK   (0x00000002u)
#define	MAC_TX_STROBE_MAC_TX_RST_BIT   (1)
#define	MAC_TX_STROBE_MAC_TX_RST_BITS   (1)
#define	MAC_TX_STROBE_START_TX   (0x00000001u)
#define	MAC_TX_STROBE_START_TX_MASK   (0x00000001u)
#define	MAC_TX_STROBE_START_TX_BIT   (0)
#define	MAC_TX_STROBE_START_TX_BITS   (1)
#define	MAC_ACK_STROBE   *((volatile int32u *)0x40002064u)
#define	MAC_ACK_STROBE_REG   *((volatile int32u *)0x40002064u)
#define	MAC_ACK_STROBE_ADDR   (0x40002064u)
#define	MAC_ACK_STROBE_RESET   (0x00000000u)
#define	MAC_ACK_STROBE_MANUAL_ACK   (0x00000002u)
#define	MAC_ACK_STROBE_MANUAL_ACK_MASK   (0x00000002u)
#define	MAC_ACK_STROBE_MANUAL_ACK_BIT   (1)
#define	MAC_ACK_STROBE_MANUAL_ACK_BITS   (1)
#define	MAC_ACK_STROBE_FRAME_PENDING   (0x00000001u)
#define	MAC_ACK_STROBE_FRAME_PENDING_MASK   (0x00000001u)
#define	MAC_ACK_STROBE_FRAME_PENDING_BIT   (0)
#define	MAC_ACK_STROBE_FRAME_PENDING_BITS   (1)
#define	MAC_STATUS   *((volatile int32u *)0x40002068u)
#define	MAC_STATUS_REG   *((volatile int32u *)0x40002068u)
#define	MAC_STATUS_ADDR   (0x40002068u)
#define	MAC_STATUS_RESET   (0x00000000u)
#define	MAC_STATUS_RX_B_PEND_TX_ACK   (0x00000800u)
#define	MAC_STATUS_RX_B_PEND_TX_ACK_MASK   (0x00000800u)
#define	MAC_STATUS_RX_B_PEND_TX_ACK_BIT   (11)
#define	MAC_STATUS_RX_B_PEND_TX_ACK_BITS   (1)
#define	MAC_STATUS_RX_A_PEND_TX_ACK   (0x00000400u)
#define	MAC_STATUS_RX_A_PEND_TX_ACK_MASK   (0x00000400u)
#define	MAC_STATUS_RX_A_PEND_TX_ACK_BIT   (10)
#define	MAC_STATUS_RX_A_PEND_TX_ACK_BITS   (1)
#define	MAC_STATUS_RX_B_LAST_UNLOAD   (0x00000200u)
#define	MAC_STATUS_RX_B_LAST_UNLOAD_MASK   (0x00000200u)
#define	MAC_STATUS_RX_B_LAST_UNLOAD_BIT   (9)
#define	MAC_STATUS_RX_B_LAST_UNLOAD_BITS   (1)
#define	MAC_STATUS_RX_A_LAST_UNLOAD   (0x00000100u)
#define	MAC_STATUS_RX_A_LAST_UNLOAD_MASK   (0x00000100u)
#define	MAC_STATUS_RX_A_LAST_UNLOAD_BIT   (8)
#define	MAC_STATUS_RX_A_LAST_UNLOAD_BITS   (1)
#define	MAC_STATUS_WRONG_FORMAT   (0x00000080u)
#define	MAC_STATUS_WRONG_FORMAT_MASK   (0x00000080u)
#define	MAC_STATUS_WRONG_FORMAT_BIT   (7)
#define	MAC_STATUS_WRONG_FORMAT_BITS   (1)
#define	MAC_STATUS_WRONG_ADDRESS   (0x00000040u)
#define	MAC_STATUS_WRONG_ADDRESS_MASK   (0x00000040u)
#define	MAC_STATUS_WRONG_ADDRESS_BIT   (6)
#define	MAC_STATUS_WRONG_ADDRESS_BITS   (1)
#define	MAC_STATUS_RX_ACK_REC   (0x00000020u)
#define	MAC_STATUS_RX_ACK_REC_MASK   (0x00000020u)
#define	MAC_STATUS_RX_ACK_REC_BIT   (5)
#define	MAC_STATUS_RX_ACK_REC_BITS   (1)
#define	MAC_STATUS_SENDING_ACK   (0x00000010u)
#define	MAC_STATUS_SENDING_ACK_MASK   (0x00000010u)
#define	MAC_STATUS_SENDING_ACK_BIT   (4)
#define	MAC_STATUS_SENDING_ACK_BITS   (1)
#define	MAC_STATUS_RUN_BO   (0x00000008u)
#define	MAC_STATUS_RUN_BO_MASK   (0x00000008u)
#define	MAC_STATUS_RUN_BO_BIT   (3)
#define	MAC_STATUS_RUN_BO_BITS   (1)
#define	MAC_STATUS_TX_FRAME   (0x00000004u)
#define	MAC_STATUS_TX_FRAME_MASK   (0x00000004u)
#define	MAC_STATUS_TX_FRAME_BIT   (2)
#define	MAC_STATUS_TX_FRAME_BITS   (1)
#define	MAC_STATUS_RX_FRAME   (0x00000002u)
#define	MAC_STATUS_RX_FRAME_MASK   (0x00000002u)
#define	MAC_STATUS_RX_FRAME_BIT   (1)
#define	MAC_STATUS_RX_FRAME_BITS   (1)
#define	MAC_STATUS_RX_CRC_PASS   (0x00000001u)
#define	MAC_STATUS_RX_CRC_PASS_MASK   (0x00000001u)
#define	MAC_STATUS_RX_CRC_PASS_BIT   (0)
#define	MAC_STATUS_RX_CRC_PASS_BITS   (1)
#define	TX_CRC   *((volatile int32u *)0x4000206Cu)
#define	TX_CRC_REG   *((volatile int32u *)0x4000206Cu)
#define	TX_CRC_ADDR   (0x4000206Cu)
#define	TX_CRC_RESET   (0x00000000u)
#define	TX_CRC_TX_CRC   (0x0000FFFFu)
#define	TX_CRC_TX_CRC_MASK   (0x0000FFFFu)
#define	TX_CRC_TX_CRC_BIT   (0)
#define	TX_CRC_TX_CRC_BITS   (16)
#define	RX_CRC   *((volatile int32u *)0x40002070u)
#define	RX_CRC_REG   *((volatile int32u *)0x40002070u)
#define	RX_CRC_ADDR   (0x40002070u)
#define	RX_CRC_RESET   (0x00000000u)
#define	RX_CRC_RX_CRC   (0x0000FFFFu)
#define	RX_CRC_RX_CRC_MASK   (0x0000FFFFu)
#define	RX_CRC_RX_CRC_BIT   (0)
#define	RX_CRC_RX_CRC_BITS   (16)
#define	MAC_ACK_TO   *((volatile int32u *)0x40002074u)
#define	MAC_ACK_TO_REG   *((volatile int32u *)0x40002074u)
#define	MAC_ACK_TO_ADDR   (0x40002074u)
#define	MAC_ACK_TO_RESET   (0x00000300u)
#define	MAC_ACK_TO_ACK_TO   (0x00003FFFu)
#define	MAC_ACK_TO_ACK_TO_MASK   (0x00003FFFu)
#define	MAC_ACK_TO_ACK_TO_BIT   (0)
#define	MAC_ACK_TO_ACK_TO_BITS   (14)
#define	MAC_BOP_COMPARE   *((volatile int32u *)0x40002078u)
#define	MAC_BOP_COMPARE_REG   *((volatile int32u *)0x40002078u)
#define	MAC_BOP_COMPARE_ADDR   (0x40002078u)
#define	MAC_BOP_COMPARE_RESET   (0x00000014u)
#define	MAC_BOP_COMPARE_MAC_BOP_COMPARE   (0x0000007Fu)
#define	MAC_BOP_COMPARE_MAC_BOP_COMPARE_MASK   (0x0000007Fu)
#define	MAC_BOP_COMPARE_MAC_BOP_COMPARE_BIT   (0)
#define	MAC_BOP_COMPARE_MAC_BOP_COMPARE_BITS   (7)
#define	MAC_TX_ACK_FRAME   *((volatile int32u *)0x4000207Cu)
#define	MAC_TX_ACK_FRAME_REG   *((volatile int32u *)0x4000207Cu)
#define	MAC_TX_ACK_FRAME_ADDR   (0x4000207Cu)
#define	MAC_TX_ACK_FRAME_RESET   (0x00000002u)
#define	MAC_TX_ACK_FRAME_ACK_SRC_AM   (0x0000C000u)
#define	MAC_TX_ACK_FRAME_ACK_SRC_AM_MASK   (0x0000C000u)
#define	MAC_TX_ACK_FRAME_ACK_SRC_AM_BIT   (14)
#define	MAC_TX_ACK_FRAME_ACK_SRC_AM_BITS   (2)
#define	MAC_TX_ACK_FRAME_RES1213   (0x00003000u)
#define	MAC_TX_ACK_FRAME_RES1213_MASK   (0x00003000u)
#define	MAC_TX_ACK_FRAME_RES1213_BIT   (12)
#define	MAC_TX_ACK_FRAME_RES1213_BITS   (2)
#define	MAC_TX_ACK_FRAME_ACK_DST_AM   (0x00000C00u)
#define	MAC_TX_ACK_FRAME_ACK_DST_AM_MASK   (0x00000C00u)
#define	MAC_TX_ACK_FRAME_ACK_DST_AM_BIT   (10)
#define	MAC_TX_ACK_FRAME_ACK_DST_AM_BITS   (2)
#define	MAC_TX_ACK_FRAME_RES789   (0x00000380u)
#define	MAC_TX_ACK_FRAME_RES789_MASK   (0x00000380u)
#define	MAC_TX_ACK_FRAME_RES789_BIT   (7)
#define	MAC_TX_ACK_FRAME_RES789_BITS   (3)
#define	MAC_TX_ACK_FRAME_ACK_IP   (0x00000040u)
#define	MAC_TX_ACK_FRAME_ACK_IP_MASK   (0x00000040u)
#define	MAC_TX_ACK_FRAME_ACK_IP_BIT   (6)
#define	MAC_TX_ACK_FRAME_ACK_IP_BITS   (1)
#define	MAC_TX_ACK_FRAME_ACK_ACK_REQ   (0x00000020u)
#define	MAC_TX_ACK_FRAME_ACK_ACK_REQ_MASK   (0x00000020u)
#define	MAC_TX_ACK_FRAME_ACK_ACK_REQ_BIT   (5)
#define	MAC_TX_ACK_FRAME_ACK_ACK_REQ_BITS   (1)
#define	MAC_TX_ACK_FRAME_ACK_FRAME_P   (0x00000010u)
#define	MAC_TX_ACK_FRAME_ACK_FRAME_P_MASK   (0x00000010u)
#define	MAC_TX_ACK_FRAME_ACK_FRAME_P_BIT   (4)
#define	MAC_TX_ACK_FRAME_ACK_FRAME_P_BITS   (1)
#define	MAC_TX_ACK_FRAME_ACK_SEC_EN   (0x00000008u)
#define	MAC_TX_ACK_FRAME_ACK_SEC_EN_MASK   (0x00000008u)
#define	MAC_TX_ACK_FRAME_ACK_SEC_EN_BIT   (3)
#define	MAC_TX_ACK_FRAME_ACK_SEC_EN_BITS   (1)
#define	MAC_TX_ACK_FRAME_ACK_FRAME_T   (0x00000007u)
#define	MAC_TX_ACK_FRAME_ACK_FRAME_T_MASK   (0x00000007u)
#define	MAC_TX_ACK_FRAME_ACK_FRAME_T_BIT   (0)
#define	MAC_TX_ACK_FRAME_ACK_FRAME_T_BITS   (3)
#define	MAC_CONFIG   *((volatile int32u *)0x40002080u)
#define	MAC_CONFIG_REG   *((volatile int32u *)0x40002080u)
#define	MAC_CONFIG_ADDR   (0x40002080u)
#define	MAC_CONFIG_RESET   (0x00000000u)
#define	MAC_CONFIG_RSSI_INST_EN   (0x00000004u)
#define	MAC_CONFIG_RSSI_INST_EN_MASK   (0x00000004u)
#define	MAC_CONFIG_RSSI_INST_EN_BIT   (2)
#define	MAC_CONFIG_RSSI_INST_EN_BITS   (1)
#define	MAC_CONFIG_SPI_SPY_EN   (0x00000002u)
#define	MAC_CONFIG_SPI_SPY_EN_MASK   (0x00000002u)
#define	MAC_CONFIG_SPI_SPY_EN_BIT   (1)
#define	MAC_CONFIG_SPI_SPY_EN_BITS   (1)
#define	MAC_CONFIG_MAC_MODE   (0x00000001u)
#define	MAC_CONFIG_MAC_MODE_MASK   (0x00000001u)
#define	MAC_CONFIG_MAC_MODE_BIT   (0)
#define	MAC_CONFIG_MAC_MODE_BITS   (1)
#define	MAC_RX_CONFIG   *((volatile int32u *)0x40002084u)
#define	MAC_RX_CONFIG_REG   *((volatile int32u *)0x40002084u)
#define	MAC_RX_CONFIG_ADDR   (0x40002084u)
#define	MAC_RX_CONFIG_RESET   (0x00000000u)
#define	MAC_RX_CONFIG_AUTO_ACK   (0x00000080u)
#define	MAC_RX_CONFIG_AUTO_ACK_MASK   (0x00000080u)
#define	MAC_RX_CONFIG_AUTO_ACK_BIT   (7)
#define	MAC_RX_CONFIG_AUTO_ACK_BITS   (1)
#define	MAC_RX_CONFIG_APPEND_INFO   (0x00000040u)
#define	MAC_RX_CONFIG_APPEND_INFO_MASK   (0x00000040u)
#define	MAC_RX_CONFIG_APPEND_INFO_BIT   (6)
#define	MAC_RX_CONFIG_APPEND_INFO_BITS   (1)
#define	MAC_RX_CONFIG_COORDINATOR   (0x00000020u)
#define	MAC_RX_CONFIG_COORDINATOR_MASK   (0x00000020u)
#define	MAC_RX_CONFIG_COORDINATOR_BIT   (5)
#define	MAC_RX_CONFIG_COORDINATOR_BITS   (1)
#define	MAC_RX_CONFIG_FILT_ADDR_ON   (0x00000010u)
#define	MAC_RX_CONFIG_FILT_ADDR_ON_MASK   (0x00000010u)
#define	MAC_RX_CONFIG_FILT_ADDR_ON_BIT   (4)
#define	MAC_RX_CONFIG_FILT_ADDR_ON_BITS   (1)
#define	MAC_RX_CONFIG_RES_FILT_PASS_ADDR   (0x00000008u)
#define	MAC_RX_CONFIG_RES_FILT_PASS_ADDR_MASK   (0x00000008u)
#define	MAC_RX_CONFIG_RES_FILT_PASS_ADDR_BIT   (3)
#define	MAC_RX_CONFIG_RES_FILT_PASS_ADDR_BITS   (1)
#define	MAC_RX_CONFIG_RES_FILT_PASS   (0x00000004u)
#define	MAC_RX_CONFIG_RES_FILT_PASS_MASK   (0x00000004u)
#define	MAC_RX_CONFIG_RES_FILT_PASS_BIT   (2)
#define	MAC_RX_CONFIG_RES_FILT_PASS_BITS   (1)
#define	MAC_RX_CONFIG_FILT_FORMAT_ON   (0x00000002u)
#define	MAC_RX_CONFIG_FILT_FORMAT_ON_MASK   (0x00000002u)
#define	MAC_RX_CONFIG_FILT_FORMAT_ON_BIT   (1)
#define	MAC_RX_CONFIG_FILT_FORMAT_ON_BITS   (1)
#define	MAC_RX_CONFIG_MAC_RX_RST   (0x00000001u)
#define	MAC_RX_CONFIG_MAC_RX_RST_MASK   (0x00000001u)
#define	MAC_RX_CONFIG_MAC_RX_RST_BIT   (0)
#define	MAC_RX_CONFIG_MAC_RX_RST_BITS   (1)
#define	MAC_TX_CONFIG   *((volatile int32u *)0x40002088u)
#define	MAC_TX_CONFIG_REG   *((volatile int32u *)0x40002088u)
#define	MAC_TX_CONFIG_ADDR   (0x40002088u)
#define	MAC_TX_CONFIG_RESET   (0x00000008u)
#define	MAC_TX_CONFIG_SLOTTED   (0x00000010u)
#define	MAC_TX_CONFIG_SLOTTED_MASK   (0x00000010u)
#define	MAC_TX_CONFIG_SLOTTED_BIT   (4)
#define	MAC_TX_CONFIG_SLOTTED_BITS   (1)
#define	MAC_TX_CONFIG_CCA_DELAY   (0x00000008u)
#define	MAC_TX_CONFIG_CCA_DELAY_MASK   (0x00000008u)
#define	MAC_TX_CONFIG_CCA_DELAY_BIT   (3)
#define	MAC_TX_CONFIG_CCA_DELAY_BITS   (1)
#define	MAC_TX_CONFIG_SLOTTED_ACK   (0x00000004u)
#define	MAC_TX_CONFIG_SLOTTED_ACK_MASK   (0x00000004u)
#define	MAC_TX_CONFIG_SLOTTED_ACK_BIT   (2)
#define	MAC_TX_CONFIG_SLOTTED_ACK_BITS   (1)
#define	MAC_TX_CONFIG_INFINITE_CRC   (0x00000002u)
#define	MAC_TX_CONFIG_INFINITE_CRC_MASK   (0x00000002u)
#define	MAC_TX_CONFIG_INFINITE_CRC_BIT   (1)
#define	MAC_TX_CONFIG_INFINITE_CRC_BITS   (1)
#define	MAC_TX_CONFIG_WAIT_ACK   (0x00000001u)
#define	MAC_TX_CONFIG_WAIT_ACK_MASK   (0x00000001u)
#define	MAC_TX_CONFIG_WAIT_ACK_BIT   (0)
#define	MAC_TX_CONFIG_WAIT_ACK_BITS   (1)
#define	MAC_TIMER_CTRL   *((volatile int32u *)0x4000208Cu)
#define	MAC_TIMER_CTRL_REG   *((volatile int32u *)0x4000208Cu)
#define	MAC_TIMER_CTRL_ADDR   (0x4000208Cu)
#define	MAC_TIMER_CTRL_RESET   (0x00000000u)
#define	MAC_TIMER_CTRL_COMP_A_SYNC   (0x00000040u)
#define	MAC_TIMER_CTRL_COMP_A_SYNC_MASK   (0x00000040u)
#define	MAC_TIMER_CTRL_COMP_A_SYNC_BIT   (6)
#define	MAC_TIMER_CTRL_COMP_A_SYNC_BITS   (1)
#define	MAC_TIMER_CTRL_BOP_TIMER_RST   (0x00000020u)
#define	MAC_TIMER_CTRL_BOP_TIMER_RST_MASK   (0x00000020u)
#define	MAC_TIMER_CTRL_BOP_TIMER_RST_BIT   (5)
#define	MAC_TIMER_CTRL_BOP_TIMER_RST_BITS   (1)
#define	MAC_TIMER_CTRL_BOP_TIMER_EN   (0x00000010u)
#define	MAC_TIMER_CTRL_BOP_TIMER_EN_MASK   (0x00000010u)
#define	MAC_TIMER_CTRL_BOP_TIMER_EN_BIT   (4)
#define	MAC_TIMER_CTRL_BOP_TIMER_EN_BITS   (1)
#define	MAC_TIMER_CTRL_BO_TIMER_RST   (0x00000008u)
#define	MAC_TIMER_CTRL_BO_TIMER_RST_MASK   (0x00000008u)
#define	MAC_TIMER_CTRL_BO_TIMER_RST_BIT   (3)
#define	MAC_TIMER_CTRL_BO_TIMER_RST_BITS   (1)
#define	MAC_TIMER_CTRL_BO_TIMER_EN   (0x00000004u)
#define	MAC_TIMER_CTRL_BO_TIMER_EN_MASK   (0x00000004u)
#define	MAC_TIMER_CTRL_BO_TIMER_EN_BIT   (2)
#define	MAC_TIMER_CTRL_BO_TIMER_EN_BITS   (1)
#define	MAC_TIMER_CTRL_MAC_TIMER_RST   (0x00000002u)
#define	MAC_TIMER_CTRL_MAC_TIMER_RST_MASK   (0x00000002u)
#define	MAC_TIMER_CTRL_MAC_TIMER_RST_BIT   (1)
#define	MAC_TIMER_CTRL_MAC_TIMER_RST_BITS   (1)
#define	MAC_TIMER_CTRL_MAC_TIMER_EN   (0x00000001u)
#define	MAC_TIMER_CTRL_MAC_TIMER_EN_MASK   (0x00000001u)
#define	MAC_TIMER_CTRL_MAC_TIMER_EN_BIT   (0)
#define	MAC_TIMER_CTRL_MAC_TIMER_EN_BITS   (1)
#define	PAN_ID   *((volatile int32u *)0x40002090u)
#define	PAN_ID_REG   *((volatile int32u *)0x40002090u)
#define	PAN_ID_ADDR   (0x40002090u)
#define	PAN_ID_RESET   (0x00000000u)
#define	PAN_ID_PAN_ID   (0x0000FFFFu)
#define	PAN_ID_PAN_ID_MASK   (0x0000FFFFu)
#define	PAN_ID_PAN_ID_BIT   (0)
#define	PAN_ID_PAN_ID_BITS   (16)
#define	SHORT_ADDR   *((volatile int32u *)0x40002094u)
#define	SHORT_ADDR_REG   *((volatile int32u *)0x40002094u)
#define	SHORT_ADDR_ADDR   (0x40002094u)
#define	SHORT_ADDR_RESET   (0x00000000u)
#define	SHORT_ADDR_SHORT_ADDR   (0x0000FFFFu)
#define	SHORT_ADDR_SHORT_ADDR_MASK   (0x0000FFFFu)
#define	SHORT_ADDR_SHORT_ADDR_BIT   (0)
#define	SHORT_ADDR_SHORT_ADDR_BITS   (16)
#define	EXT_ADDR_0   *((volatile int32u *)0x40002098u)
#define	EXT_ADDR_0_REG   *((volatile int32u *)0x40002098u)
#define	EXT_ADDR_0_ADDR   (0x40002098u)
#define	EXT_ADDR_0_RESET   (0x00000000u)
#define	EXT_ADDR_0_EXT_ADDR_0   (0x0000FFFFu)
#define	EXT_ADDR_0_EXT_ADDR_0_MASK   (0x0000FFFFu)
#define	EXT_ADDR_0_EXT_ADDR_0_BIT   (0)
#define	EXT_ADDR_0_EXT_ADDR_0_BITS   (16)
#define	EXT_ADDR_1   *((volatile int32u *)0x4000209Cu)
#define	EXT_ADDR_1_REG   *((volatile int32u *)0x4000209Cu)
#define	EXT_ADDR_1_ADDR   (0x4000209Cu)
#define	EXT_ADDR_1_RESET   (0x00000000u)
#define	EXT_ADDR_1_EXT_ADDR_1   (0x0000FFFFu)
#define	EXT_ADDR_1_EXT_ADDR_1_MASK   (0x0000FFFFu)
#define	EXT_ADDR_1_EXT_ADDR_1_BIT   (0)
#define	EXT_ADDR_1_EXT_ADDR_1_BITS   (16)
#define	EXT_ADDR_2   *((volatile int32u *)0x400020A0u)
#define	EXT_ADDR_2_REG   *((volatile int32u *)0x400020A0u)
#define	EXT_ADDR_2_ADDR   (0x400020A0u)
#define	EXT_ADDR_2_RESET   (0x00000000u)
#define	EXT_ADDR_2_EXT_ADDR_2   (0x0000FFFFu)
#define	EXT_ADDR_2_EXT_ADDR_2_MASK   (0x0000FFFFu)
#define	EXT_ADDR_2_EXT_ADDR_2_BIT   (0)
#define	EXT_ADDR_2_EXT_ADDR_2_BITS   (16)
#define	EXT_ADDR_3   *((volatile int32u *)0x400020A4u)
#define	EXT_ADDR_3_REG   *((volatile int32u *)0x400020A4u)
#define	EXT_ADDR_3_ADDR   (0x400020A4u)
#define	EXT_ADDR_3_RESET   (0x00000000u)
#define	EXT_ADDR_3_EXT_ADDR_3   (0x0000FFFFu)
#define	EXT_ADDR_3_EXT_ADDR_3_MASK   (0x0000FFFFu)
#define	EXT_ADDR_3_EXT_ADDR_3_BIT   (0)
#define	EXT_ADDR_3_EXT_ADDR_3_BITS   (16)
#define	MAC_STATE   *((volatile int32u *)0x400020A8u)
#define	MAC_STATE_REG   *((volatile int32u *)0x400020A8u)
#define	MAC_STATE_ADDR   (0x400020A8u)
#define	MAC_STATE_RESET   (0x00000000u)
#define	MAC_STATE_SPY_STATE   (0x00000700u)
#define	MAC_STATE_SPY_STATE_MASK   (0x00000700u)
#define	MAC_STATE_SPY_STATE_BIT   (8)
#define	MAC_STATE_SPY_STATE_BITS   (3)
#define	MAC_STATE_ACK_STATE   (0x000000C0u)
#define	MAC_STATE_ACK_STATE_MASK   (0x000000C0u)
#define	MAC_STATE_ACK_STATE_BIT   (6)
#define	MAC_STATE_ACK_STATE_BITS   (2)
#define	MAC_STATE_BO_STATE   (0x0000003Cu)
#define	MAC_STATE_BO_STATE_MASK   (0x0000003Cu)
#define	MAC_STATE_BO_STATE_BIT   (2)
#define	MAC_STATE_BO_STATE_BITS   (4)
#define	MAC_STATE_TOP_STATE   (0x00000003u)
#define	MAC_STATE_TOP_STATE_MASK   (0x00000003u)
#define	MAC_STATE_TOP_STATE_BIT   (0)
#define	MAC_STATE_TOP_STATE_BITS   (2)
#define	RX_STATE   *((volatile int32u *)0x400020ACu)
#define	RX_STATE_REG   *((volatile int32u *)0x400020ACu)
#define	RX_STATE_ADDR   (0x400020ACu)
#define	RX_STATE_RESET   (0x00000000u)
#define	RX_STATE_RX_BUFFER_STATE   (0x000001E0u)
#define	RX_STATE_RX_BUFFER_STATE_MASK   (0x000001E0u)
#define	RX_STATE_RX_BUFFER_STATE_BIT   (5)
#define	RX_STATE_RX_BUFFER_STATE_BITS   (4)
#define	RX_STATE_RX_TOP_STATE   (0x0000001Fu)
#define	RX_STATE_RX_TOP_STATE_MASK   (0x0000001Fu)
#define	RX_STATE_RX_TOP_STATE_BIT   (0)
#define	RX_STATE_RX_TOP_STATE_BITS   (5)
#define	TX_STATE   *((volatile int32u *)0x400020B0u)
#define	TX_STATE_REG   *((volatile int32u *)0x400020B0u)
#define	TX_STATE_ADDR   (0x400020B0u)
#define	TX_STATE_RESET   (0x00000000u)
#define	TX_STATE_TX_BUFFER_STATE   (0x000000F0u)
#define	TX_STATE_TX_BUFFER_STATE_MASK   (0x000000F0u)
#define	TX_STATE_TX_BUFFER_STATE_BIT   (4)
#define	TX_STATE_TX_BUFFER_STATE_BITS   (4)
#define	TX_STATE_TX_TOP_STATE   (0x0000000Fu)
#define	TX_STATE_TX_TOP_STATE_MASK   (0x0000000Fu)
#define	TX_STATE_TX_TOP_STATE_BIT   (0)
#define	TX_STATE_TX_TOP_STATE_BITS   (4)
#define	DMA_STATE   *((volatile int32u *)0x400020B4u)
#define	DMA_STATE_REG   *((volatile int32u *)0x400020B4u)
#define	DMA_STATE_ADDR   (0x400020B4u)
#define	DMA_STATE_RESET   (0x00000000u)
#define	DMA_STATE_DMA_RX_STATE   (0x00000038u)
#define	DMA_STATE_DMA_RX_STATE_MASK   (0x00000038u)
#define	DMA_STATE_DMA_RX_STATE_BIT   (3)
#define	DMA_STATE_DMA_RX_STATE_BITS   (3)
#define	DMA_STATE_DMA_TX_STATE   (0x00000007u)
#define	DMA_STATE_DMA_TX_STATE_MASK   (0x00000007u)
#define	DMA_STATE_DMA_TX_STATE_BIT   (0)
#define	DMA_STATE_DMA_TX_STATE_BITS   (3)
#define	MAC_DEBUG   *((volatile int32u *)0x400020B8u)
#define	MAC_DEBUG_REG   *((volatile int32u *)0x400020B8u)
#define	MAC_DEBUG_ADDR   (0x400020B8u)
#define	MAC_DEBUG_RESET   (0x00000000u)
#define	MAC_DEBUG_SW_DEBUG_OUT   (0x00000060u)
#define	MAC_DEBUG_SW_DEBUG_OUT_MASK   (0x00000060u)
#define	MAC_DEBUG_SW_DEBUG_OUT_BIT   (5)
#define	MAC_DEBUG_SW_DEBUG_OUT_BITS   (2)
#define	MAC_DEBUG_MAC_DEBUG_MUX   (0x0000001Fu)
#define	MAC_DEBUG_MAC_DEBUG_MUX_MASK   (0x0000001Fu)
#define	MAC_DEBUG_MAC_DEBUG_MUX_BIT   (0)
#define	MAC_DEBUG_MAC_DEBUG_MUX_BITS   (5)
#define	MAC_DEBUG_VIEW   *((volatile int32u *)0x400020BCu)
#define	MAC_DEBUG_VIEW_REG   *((volatile int32u *)0x400020BCu)
#define	MAC_DEBUG_VIEW_ADDR   (0x400020BCu)
#define	MAC_DEBUG_VIEW_RESET   (0x00000010u)
#define	MAC_DEBUG_VIEW_MAC_DEBUG_VIEW   (0x0000FFFFu)
#define	MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_MASK   (0x0000FFFFu)
#define	MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_BIT   (0)
#define	MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_BITS   (16)
#define	MAC_RSSI_DELAY   *((volatile int32u *)0x400020C0u)
#define	MAC_RSSI_DELAY_REG   *((volatile int32u *)0x400020C0u)
#define	MAC_RSSI_DELAY_ADDR   (0x400020C0u)
#define	MAC_RSSI_DELAY_RESET   (0x00000000u)
#define	MAC_RSSI_DELAY_RSSI_INST_DELAY_OK   (0x00000FC0u)
#define	MAC_RSSI_DELAY_RSSI_INST_DELAY_OK_MASK   (0x00000FC0u)
#define	MAC_RSSI_DELAY_RSSI_INST_DELAY_OK_BIT   (6)
#define	MAC_RSSI_DELAY_RSSI_INST_DELAY_OK_BITS   (6)
#define	MAC_RSSI_DELAY_RSSI_INST_DELAY   (0x0000003Fu)
#define	MAC_RSSI_DELAY_RSSI_INST_DELAY_MASK   (0x0000003Fu)
#define	MAC_RSSI_DELAY_RSSI_INST_DELAY_BIT   (0)
#define	MAC_RSSI_DELAY_RSSI_INST_DELAY_BITS   (6)
#define	PANID_COUNT   *((volatile int32u *)0x400020C4u)
#define	PANID_COUNT_REG   *((volatile int32u *)0x400020C4u)
#define	PANID_COUNT_ADDR   (0x400020C4u)
#define	PANID_COUNT_RESET   (0x00000000u)
#define	PANID_COUNT_PANID_COUNT   (0x0000FFFFu)
#define	PANID_COUNT_PANID_COUNT_MASK   (0x0000FFFFu)
#define	PANID_COUNT_PANID_COUNT_BIT   (0)
#define	PANID_COUNT_PANID_COUNT_BITS   (16)
#define	NONPAN_COUNT   *((volatile int32u *)0x400020C8u)
#define	NONPAN_COUNT_REG   *((volatile int32u *)0x400020C8u)
#define	NONPAN_COUNT_ADDR   (0x400020C8u)
#define	NONPAN_COUNT_RESET   (0x00000000u)
#define	NONPAN_COUNT_NONPAN_COUNT   (0x0000FFFFu)
#define	NONPAN_COUNT_NONPAN_COUNT_MASK   (0x0000FFFFu)
#define	NONPAN_COUNT_NONPAN_COUNT_BIT   (0)
#define	NONPAN_COUNT_NONPAN_COUNT_BITS   (16)
#define	DATA_SECURITY_BASE   (0x40003000u)
#define	DATA_SECURITY_END   (0x40003044u)
#define	DATA_SECURITY_SIZE   (DATA_SECURITY_END - DATA_SECURITY_BASE + 1)
#define	SECURITY_CONFIG   *((volatile int32u *)0x40003000u)
#define	SECURITY_CONFIG_REG   *((volatile int32u *)0x40003000u)
#define	SECURITY_CONFIG_ADDR   (0x40003000u)
#define	SECURITY_CONFIG_RESET   (0x00000000u)
#define	SECURITY_CONFIG_SEC_RST   (0x00000080u)
#define	SECURITY_CONFIG_SEC_RST_MASK   (0x00000080u)
#define	SECURITY_CONFIG_SEC_RST_BIT   (7)
#define	SECURITY_CONFIG_SEC_RST_BITS   (1)
#define	SECURITY_CONFIG_CTR_IN   (0x00000040u)
#define	SECURITY_CONFIG_CTR_IN_MASK   (0x00000040u)
#define	SECURITY_CONFIG_CTR_IN_BIT   (6)
#define	SECURITY_CONFIG_CTR_IN_BITS   (1)
#define	SECURITY_CONFIG_MIC_XOR_CT   (0x00000020u)
#define	SECURITY_CONFIG_MIC_XOR_CT_MASK   (0x00000020u)
#define	SECURITY_CONFIG_MIC_XOR_CT_BIT   (5)
#define	SECURITY_CONFIG_MIC_XOR_CT_BITS   (1)
#define	SECURITY_CONFIG_CBC_XOR_PT   (0x00000010u)
#define	SECURITY_CONFIG_CBC_XOR_PT_MASK   (0x00000010u)
#define	SECURITY_CONFIG_CBC_XOR_PT_BIT   (4)
#define	SECURITY_CONFIG_CBC_XOR_PT_BITS   (1)
#define	SECURITY_CONFIG_CT_TO_CBC_ST   (0x00000008u)
#define	SECURITY_CONFIG_CT_TO_CBC_ST_MASK   (0x00000008u)
#define	SECURITY_CONFIG_CT_TO_CBC_ST_BIT   (3)
#define	SECURITY_CONFIG_CT_TO_CBC_ST_BITS   (1)
#define	SECURITY_CONFIG_WAIT_CT_READ   (0x00000004u)
#define	SECURITY_CONFIG_WAIT_CT_READ_MASK   (0x00000004u)
#define	SECURITY_CONFIG_WAIT_CT_READ_BIT   (2)
#define	SECURITY_CONFIG_WAIT_CT_READ_BITS   (1)
#define	SECURITY_CONFIG_WAIT_PT_WRITE   (0x00000002u)
#define	SECURITY_CONFIG_WAIT_PT_WRITE_MASK   (0x00000002u)
#define	SECURITY_CONFIG_WAIT_PT_WRITE_BIT   (1)
#define	SECURITY_CONFIG_WAIT_PT_WRITE_BITS   (1)
#define	SECURITY_CONFIG_START_AES   (0x00000001u)
#define	SECURITY_CONFIG_START_AES_MASK   (0x00000001u)
#define	SECURITY_CONFIG_START_AES_BIT   (0)
#define	SECURITY_CONFIG_START_AES_BITS   (1)
#define	SECURITY_STATUS   *((volatile int32u *)0x40003004u)
#define	SECURITY_STATUS_REG   *((volatile int32u *)0x40003004u)
#define	SECURITY_STATUS_ADDR   (0x40003004u)
#define	SECURITY_STATUS_RESET   (0x00000000u)
#define	SECURITY_STATUS_SEC_BUSY   (0x00000001u)
#define	SECURITY_STATUS_SEC_BUSY_MASK   (0x00000001u)
#define	SECURITY_STATUS_SEC_BUSY_BIT   (0)
#define	SECURITY_STATUS_SEC_BUSY_BITS   (1)
#define	CBC_STATE_0   *((volatile int32u *)0x40003008u)
#define	CBC_STATE_0_REG   *((volatile int32u *)0x40003008u)
#define	CBC_STATE_0_ADDR   (0x40003008u)
#define	CBC_STATE_0_RESET   (0x00000000u)
#define	CBC_STATE_0_CBC_STATE   (0xFFFFFFFFu)
#define	CBC_STATE_0_CBC_STATE_MASK   (0xFFFFFFFFu)
#define	CBC_STATE_0_CBC_STATE_BIT   (0)
#define	CBC_STATE_0_CBC_STATE_BITS   (32)
#define	CBC_STATE_1   *((volatile int32u *)0x4000300Cu)
#define	CBC_STATE_1_REG   *((volatile int32u *)0x4000300Cu)
#define	CBC_STATE_1_ADDR   (0x4000300Cu)
#define	CBC_STATE_1_RESET   (0x00000000u)
#define	CBC_STATE_1_CBC_STATE_1   (0xFFFFFFFFu)
#define	CBC_STATE_1_CBC_STATE_1_MASK   (0xFFFFFFFFu)
#define	CBC_STATE_1_CBC_STATE_1_BIT   (0)
#define	CBC_STATE_1_CBC_STATE_1_BITS   (32)
#define	CBC_STATE_2   *((volatile int32u *)0x40003010u)
#define	CBC_STATE_2_REG   *((volatile int32u *)0x40003010u)
#define	CBC_STATE_2_ADDR   (0x40003010u)
#define	CBC_STATE_2_RESET   (0x00000000u)
#define	CBC_STATE_2_CBC_STATE_2   (0xFFFFFFFFu)
#define	CBC_STATE_2_CBC_STATE_2_MASK   (0xFFFFFFFFu)
#define	CBC_STATE_2_CBC_STATE_2_BIT   (0)
#define	CBC_STATE_2_CBC_STATE_2_BITS   (32)
#define	CBC_STATE_3   *((volatile int32u *)0x40003014u)
#define	CBC_STATE_3_REG   *((volatile int32u *)0x40003014u)
#define	CBC_STATE_3_ADDR   (0x40003014u)
#define	CBC_STATE_3_RESET   (0x00000000u)
#define	CBC_STATE_3_CBC_STATE_3   (0xFFFFFFFFu)
#define	CBC_STATE_3_CBC_STATE_3_MASK   (0xFFFFFFFFu)
#define	CBC_STATE_3_CBC_STATE_3_BIT   (0)
#define	CBC_STATE_3_CBC_STATE_3_BITS   (32)
#define	PT   *((volatile int32u *)0x40003028u)
#define	PT_REG   *((volatile int32u *)0x40003028u)
#define	PT_ADDR   (0x40003028u)
#define	PT_RESET   (0x00000000u)
#define	PT_PT   (0xFFFFFFFFu)
#define	PT_PT_MASK   (0xFFFFFFFFu)
#define	PT_PT_BIT   (0)
#define	PT_PT_BITS   (32)
#define	CT   *((volatile int32u *)0x40003030u)
#define	CT_REG   *((volatile int32u *)0x40003030u)
#define	CT_ADDR   (0x40003030u)
#define	CT_RESET   (0x00000000u)
#define	CT_CT   (0xFFFFFFFFu)
#define	CT_CT_MASK   (0xFFFFFFFFu)
#define	CT_CT_BIT   (0)
#define	CT_CT_BITS   (32)
#define	KEY_0   *((volatile int32u *)0x40003038u)
#define	KEY_0_REG   *((volatile int32u *)0x40003038u)
#define	KEY_0_ADDR   (0x40003038u)
#define	KEY_0_RESET   (0x00000000u)
#define	KEY_0_KEY_O   (0xFFFFFFFFu)
#define	KEY_0_KEY_O_MASK   (0xFFFFFFFFu)
#define	KEY_0_KEY_O_BIT   (0)
#define	KEY_0_KEY_O_BITS   (32)
#define	KEY_1   *((volatile int32u *)0x4000303Cu)
#define	KEY_1_REG   *((volatile int32u *)0x4000303Cu)
#define	KEY_1_ADDR   (0x4000303Cu)
#define	KEY_1_RESET   (0x00000000u)
#define	KEY_1_KEY_1   (0xFFFFFFFFu)
#define	KEY_1_KEY_1_MASK   (0xFFFFFFFFu)
#define	KEY_1_KEY_1_BIT   (0)
#define	KEY_1_KEY_1_BITS   (32)
#define	KEY_2   *((volatile int32u *)0x40003040u)
#define	KEY_2_REG   *((volatile int32u *)0x40003040u)
#define	KEY_2_ADDR   (0x40003040u)
#define	KEY_2_RESET   (0x00000000u)
#define	KEY_2_KEY_2   (0xFFFFFFFFu)
#define	KEY_2_KEY_2_MASK   (0xFFFFFFFFu)
#define	KEY_2_KEY_2_BIT   (0)
#define	KEY_2_KEY_2_BITS   (32)
#define	KEY_3   *((volatile int32u *)0x40003044u)
#define	KEY_3_REG   *((volatile int32u *)0x40003044u)
#define	KEY_3_ADDR   (0x40003044u)
#define	KEY_3_RESET   (0x00000000u)
#define	KEY_3_KEY_3   (0xFFFFFFFFu)
#define	KEY_3_KEY_3_MASK   (0xFFFFFFFFu)
#define	KEY_3_KEY_3_BIT   (0)
#define	KEY_3_KEY_3_BITS   (32)
#define	BLOCK_CM_LV_BASE   (0x40004000u)
#define	BLOCK_CM_LV_END   (0x40004034u)
#define	BLOCK_CM_LV_SIZE   (BLOCK_CM_LV_END - BLOCK_CM_LV_BASE + 1)
#define	SILICON_ID   *((volatile int32u *)0x40004000u)
#define	SILICON_ID_REG   *((volatile int32u *)0x40004000u)
#define	SILICON_ID_ADDR   (0x40004000u)
#define	SILICON_ID_RESET   (0x069A862Bu)
#define	SILICON_ID_HW_VERSION   (0xF0000000u)
#define	SILICON_ID_HW_VERSION_MASK   (0xF0000000u)
#define	SILICON_ID_HW_VERSION_BIT   (28)
#define	SILICON_ID_HW_VERSION_BITS   (4)
#define	SILICON_ID_ST_DIVISION   (0x0F000000u)
#define	SILICON_ID_ST_DIVISION_MASK   (0x0F000000u)
#define	SILICON_ID_ST_DIVISION_BIT   (24)
#define	SILICON_ID_ST_DIVISION_BITS   (4)
#define	SILICON_ID_CHIP_TYPE   (0x00FF8000u)
#define	SILICON_ID_CHIP_TYPE_MASK   (0x00FF8000u)
#define	SILICON_ID_CHIP_TYPE_BIT   (15)
#define	SILICON_ID_CHIP_TYPE_BITS   (9)
#define	SILICON_ID_SUB_TYPE   (0x00007000u)
#define	SILICON_ID_SUB_TYPE_MASK   (0x00007000u)
#define	SILICON_ID_SUB_TYPE_BIT   (12)
#define	SILICON_ID_SUB_TYPE_BITS   (3)
#define	SILICON_ID_JEDEC_MAN_ID   (0x00000FFEu)
#define	SILICON_ID_JEDEC_MAN_ID_MASK   (0x00000FFEu)
#define	SILICON_ID_JEDEC_MAN_ID_BIT   (1)
#define	SILICON_ID_JEDEC_MAN_ID_BITS   (11)
#define	SILICON_ID_ONE   (0x00000001u)
#define	SILICON_ID_ONE_MASK   (0x00000001u)
#define	SILICON_ID_ONE_BIT   (0)
#define	SILICON_ID_ONE_BITS   (1)
#define	OSC24M_BIASTRIM   *((volatile int32u *)0x40004004u)
#define	OSC24M_BIASTRIM_REG   *((volatile int32u *)0x40004004u)
#define	OSC24M_BIASTRIM_ADDR   (0x40004004u)
#define	OSC24M_BIASTRIM_RESET   (0x0000000Fu)
#define	OSC24M_BIASTRIM_OSC24M_BIAS_TRIM   (0x0000000Fu)
#define	OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_MASK   (0x0000000Fu)
#define	OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_BIT   (0)
#define	OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_BITS   (4)
#define	OSCHF_TUNE   *((volatile int32u *)0x40004008u)
#define	OSCHF_TUNE_REG   *((volatile int32u *)0x40004008u)
#define	OSCHF_TUNE_ADDR   (0x40004008u)
#define	OSCHF_TUNE_RESET   (0x00000017u)
#define	OSCHF_TUNE_FIELD   (0x0000001Fu)
#define	OSCHF_TUNE_FIELD_MASK   (0x0000001Fu)
#define	OSCHF_TUNE_FIELD_BIT   (0)
#define	OSCHF_TUNE_FIELD_BITS   (5)
#define	OSC24M_COMP   *((volatile int32u *)0x4000400Cu)
#define	OSC24M_COMP_REG   *((volatile int32u *)0x4000400Cu)
#define	OSC24M_COMP_ADDR   (0x4000400Cu)
#define	OSC24M_COMP_RESET   (0x00000000u)
#define	OSC24M_HI   (0x00000002u)
#define	OSC24M_HI_MASK   (0x00000002u)
#define	OSC24M_HI_BIT   (1)
#define	OSC24M_HI_BITS   (1)
#define	OSC24M_LO   (0x00000001u)
#define	OSC24M_LO_MASK   (0x00000001u)
#define	OSC24M_LO_BIT   (0)
#define	OSC24M_LO_BITS   (1)
#define	CLK_PERIODMODE   *((volatile int32u *)0x40004010u)
#define	CLK_PERIODMODE_REG   *((volatile int32u *)0x40004010u)
#define	CLK_PERIODMODE_ADDR   (0x40004010u)
#define	CLK_PERIODMODE_RESET   (0x00000000u)
#define	CLK_PERIODMODE_FIELD   (0x00000003u)
#define	CLK_PERIODMODE_FIELD_MASK   (0x00000003u)
#define	CLK_PERIODMODE_FIELD_BIT   (0)
#define	CLK_PERIODMODE_FIELD_BITS   (2)
#define	CLK_PERIOD   *((volatile int32u *)0x40004014u)
#define	CLK_PERIOD_REG   *((volatile int32u *)0x40004014u)
#define	CLK_PERIOD_ADDR   (0x40004014u)
#define	CLK_PERIOD_RESET   (0x00000000u)
#define	CLK_PERIOD_FIELD   (0x0000FFFFu)
#define	CLK_PERIOD_FIELD_MASK   (0x0000FFFFu)
#define	CLK_PERIOD_FIELD_BIT   (0)
#define	CLK_PERIOD_FIELD_BITS   (16)
#define	DITHER_DIS   *((volatile int32u *)0x40004018u)
#define	DITHER_DIS_REG   *((volatile int32u *)0x40004018u)
#define	DITHER_DIS_ADDR   (0x40004018u)
#define	DITHER_DIS_RESET   (0x00000000u)
#define	DITHER_DIS_DITHER_DIS   (0x00000001u)
#define	DITHER_DIS_DITHER_DIS_MASK   (0x00000001u)
#define	DITHER_DIS_DITHER_DIS_BIT   (0)
#define	DITHER_DIS_DITHER_DIS_BITS   (1)
#define	OSC24M_CTRL   *((volatile int32u *)0x4000401Cu)
#define	OSC24M_CTRL_REG   *((volatile int32u *)0x4000401Cu)
#define	OSC24M_CTRL_ADDR   (0x4000401Cu)
#define	OSC24M_CTRL_RESET   (0x00000000u)
#define	OSC24M_CTRL_OSC24M_EN   (0x00000002u)
#define	OSC24M_CTRL_OSC24M_EN_MASK   (0x00000002u)
#define	OSC24M_CTRL_OSC24M_EN_BIT   (1)
#define	OSC24M_CTRL_OSC24M_EN_BITS   (1)
#define	OSC24M_CTRL_OSC24M_SEL   (0x00000001u)
#define	OSC24M_CTRL_OSC24M_SEL_MASK   (0x00000001u)
#define	OSC24M_CTRL_OSC24M_SEL_BIT   (0)
#define	OSC24M_CTRL_OSC24M_SEL_BITS   (1)
#define	CPU_CLKSEL   *((volatile int32u *)0x40004020u)
#define	CPU_CLKSEL_REG   *((volatile int32u *)0x40004020u)
#define	CPU_CLKSEL_ADDR   (0x40004020u)
#define	CPU_CLKSEL_RESET   (0x00000000u)
#define	CPU_CLKSEL_FIELD   (0x00000001u)
#define	CPU_CLKSEL_FIELD_MASK   (0x00000001u)
#define	CPU_CLKSEL_FIELD_BIT   (0)
#define	CPU_CLKSEL_FIELD_BITS   (1)
#define	BUS_FAULT   *((volatile int32u *)0x40004024u)
#define	BUS_FAULT_REG   *((volatile int32u *)0x40004024u)
#define	BUS_FAULT_ADDR   (0x40004024u)
#define	BUS_FAULT_RESET   (0x00000000u)
#define	BUS_FAULT_WRONGSIZE   (0x00000008u)
#define	BUS_FAULT_WRONGSIZE_MASK   (0x00000008u)
#define	BUS_FAULT_WRONGSIZE_BIT   (3)
#define	BUS_FAULT_WRONGSIZE_BITS   (1)
#define	BUS_FAULT_PROTECTED   (0x00000004u)
#define	BUS_FAULT_PROTECTED_MASK   (0x00000004u)
#define	BUS_FAULT_PROTECTED_BIT   (2)
#define	BUS_FAULT_PROTECTED_BITS   (1)
#define	BUS_FAULT_RESERVED   (0x00000002u)
#define	BUS_FAULT_RESERVED_MASK   (0x00000002u)
#define	BUS_FAULT_RESERVED_BIT   (1)
#define	BUS_FAULT_RESERVED_BITS   (1)
#define	BUS_FAULT_MISSED   (0x00000001u)
#define	BUS_FAULT_MISSED_MASK   (0x00000001u)
#define	BUS_FAULT_MISSED_BIT   (0)
#define	BUS_FAULT_MISSED_BITS   (1)
#define	PCTRACE_SEL   *((volatile int32u *)0x40004028u)
#define	PCTRACE_SEL_REG   *((volatile int32u *)0x40004028u)
#define	PCTRACE_SEL_ADDR   (0x40004028u)
#define	PCTRACE_SEL_RESET   (0x00000000u)
#define	PCTRACE_SEL_FIELD   (0x00000001u)
#define	PCTRACE_SEL_FIELD_MASK   (0x00000001u)
#define	PCTRACE_SEL_FIELD_BIT   (0)
#define	PCTRACE_SEL_FIELD_BITS   (1)
#define	FPEC_CLKREQ   *((volatile int32u *)0x4000402Cu)
#define	FPEC_CLKREQ_REG   *((volatile int32u *)0x4000402Cu)
#define	FPEC_CLKREQ_ADDR   (0x4000402Cu)
#define	FPEC_CLKREQ_RESET   (0x00000000u)
#define	FPEC_CLKREQ_FIELD   (0x00000001u)
#define	FPEC_CLKREQ_FIELD_MASK   (0x00000001u)
#define	FPEC_CLKREQ_FIELD_BIT   (0)
#define	FPEC_CLKREQ_FIELD_BITS   (1)
#define	FPEC_CLKSTAT   *((volatile int32u *)0x40004030u)
#define	FPEC_CLKSTAT_REG   *((volatile int32u *)0x40004030u)
#define	FPEC_CLKSTAT_ADDR   (0x40004030u)
#define	FPEC_CLKSTAT_RESET   (0x00000000u)
#define	FPEC_CLKBSY   (0x00000002u)
#define	FPEC_CLKBSY_MASK   (0x00000002u)
#define	FPEC_CLKBSY_BIT   (1)
#define	FPEC_CLKBSY_BITS   (1)
#define	FPEC_CLKACK   (0x00000001u)
#define	FPEC_CLKACK_MASK   (0x00000001u)
#define	FPEC_CLKACK_BIT   (0)
#define	FPEC_CLKACK_BITS   (1)
#define	LV_SPARE   *((volatile int32u *)0x40004034u)
#define	LV_SPARE_REG   *((volatile int32u *)0x40004034u)
#define	LV_SPARE_ADDR   (0x40004034u)
#define	LV_SPARE_RESET   (0x00000000u)
#define	LV_SPARE_LV_SPARE   (0x000000FFu)
#define	LV_SPARE_LV_SPARE_MASK   (0x000000FFu)
#define	LV_SPARE_LV_SPARE_BIT   (0)
#define	LV_SPARE_LV_SPARE_BITS   (8)
#define	DATA_RAM_CTRL_BASE   (0x40005000u)
#define	DATA_RAM_CTRL_END   (0x40005028u)
#define	DATA_RAM_CTRL_SIZE   (DATA_RAM_CTRL_END - DATA_RAM_CTRL_BASE + 1)
#define	MEM_PROT_0   *((volatile int32u *)0x40005000u)
#define	MEM_PROT_0_REG   *((volatile int32u *)0x40005000u)
#define	MEM_PROT_0_ADDR   (0x40005000u)
#define	MEM_PROT_0_RESET   (0x00000000u)
#define	MEM_PROT_0_MEM_PROT_0   (0xFFFFFFFFu)
#define	MEM_PROT_0_MEM_PROT_0_MASK   (0xFFFFFFFFu)
#define	MEM_PROT_0_MEM_PROT_0_BIT   (0)
#define	MEM_PROT_0_MEM_PROT_0_BITS   (32)
#define	MEM_PROT_1   *((volatile int32u *)0x40005004u)
#define	MEM_PROT_1_REG   *((volatile int32u *)0x40005004u)
#define	MEM_PROT_1_ADDR   (0x40005004u)
#define	MEM_PROT_1_RESET   (0x00000000u)
#define	MEM_PROT_1_MEM_PROT_1   (0xFFFFFFFFu)
#define	MEM_PROT_1_MEM_PROT_1_MASK   (0xFFFFFFFFu)
#define	MEM_PROT_1_MEM_PROT_1_BIT   (0)
#define	MEM_PROT_1_MEM_PROT_1_BITS   (32)
#define	MEM_PROT_2   *((volatile int32u *)0x40005008u)
#define	MEM_PROT_2_REG   *((volatile int32u *)0x40005008u)
#define	MEM_PROT_2_ADDR   (0x40005008u)
#define	MEM_PROT_2_RESET   (0x00000000u)
#define	MEM_PROT_2_MEM_PROT_2   (0xFFFFFFFFu)
#define	MEM_PROT_2_MEM_PROT_2_MASK   (0xFFFFFFFFu)
#define	MEM_PROT_2_MEM_PROT_2_BIT   (0)
#define	MEM_PROT_2_MEM_PROT_2_BITS   (32)
#define	MEM_PROT_3   *((volatile int32u *)0x4000500Cu)
#define	MEM_PROT_3_REG   *((volatile int32u *)0x4000500Cu)
#define	MEM_PROT_3_ADDR   (0x4000500Cu)
#define	MEM_PROT_3_RESET   (0x00000000u)
#define	MEM_PROT_3_MEM_PROT_3   (0xFFFFFFFFu)
#define	MEM_PROT_3_MEM_PROT_3_MASK   (0xFFFFFFFFu)
#define	MEM_PROT_3_MEM_PROT_3_BIT   (0)
#define	MEM_PROT_3_MEM_PROT_3_BITS   (32)
#define	MEM_PROT_4   *((volatile int32u *)0x40005010u)
#define	MEM_PROT_4_REG   *((volatile int32u *)0x40005010u)
#define	MEM_PROT_4_ADDR   (0x40005010u)
#define	MEM_PROT_4_RESET   (0x00000000u)
#define	MEM_PROT_4_MEM_PROT_4   (0xFFFFFFFFu)
#define	MEM_PROT_4_MEM_PROT_4_MASK   (0xFFFFFFFFu)
#define	MEM_PROT_4_MEM_PROT_4_BIT   (0)
#define	MEM_PROT_4_MEM_PROT_4_BITS   (32)
#define	MEM_PROT_5   *((volatile int32u *)0x40005014u)
#define	MEM_PROT_5_REG   *((volatile int32u *)0x40005014u)
#define	MEM_PROT_5_ADDR   (0x40005014u)
#define	MEM_PROT_5_RESET   (0x00000000u)
#define	MEM_PROT_5_MEM_PROT_5   (0xFFFFFFFFu)
#define	MEM_PROT_5_MEM_PROT_5_MASK   (0xFFFFFFFFu)
#define	MEM_PROT_5_MEM_PROT_5_BIT   (0)
#define	MEM_PROT_5_MEM_PROT_5_BITS   (32)
#define	MEM_PROT_6   *((volatile int32u *)0x40005018u)
#define	MEM_PROT_6_REG   *((volatile int32u *)0x40005018u)
#define	MEM_PROT_6_ADDR   (0x40005018u)
#define	MEM_PROT_6_RESET   (0x00000000u)
#define	MEM_PROT_6_MEM_PROT_6   (0xFFFFFFFFu)
#define	MEM_PROT_6_MEM_PROT_6_MASK   (0xFFFFFFFFu)
#define	MEM_PROT_6_MEM_PROT_6_BIT   (0)
#define	MEM_PROT_6_MEM_PROT_6_BITS   (32)
#define	MEM_PROT_7   *((volatile int32u *)0x4000501Cu)
#define	MEM_PROT_7_REG   *((volatile int32u *)0x4000501Cu)
#define	MEM_PROT_7_ADDR   (0x4000501Cu)
#define	MEM_PROT_7_RESET   (0x00000000u)
#define	MEM_PROT_7_MEM_PROT_7   (0xFFFFFFFFu)
#define	MEM_PROT_7_MEM_PROT_7_MASK   (0xFFFFFFFFu)
#define	MEM_PROT_7_MEM_PROT_7_BIT   (0)
#define	MEM_PROT_7_MEM_PROT_7_BITS   (32)
#define	DMA_PROT_ADDR   *((volatile int32u *)0x40005020u)
#define	DMA_PROT_ADDR_REG   *((volatile int32u *)0x40005020u)
#define	DMA_PROT_ADDR_ADDR   (0x40005020u)
#define	DMA_PROT_ADDR_RESET   (0x20000000u)
#define	DMA_PROT_ADDR_DMA_PROT_OFFS   (0xFFFFE000u)
#define	DMA_PROT_ADDR_DMA_PROT_OFFS_MASK   (0xFFFFE000u)
#define	DMA_PROT_ADDR_DMA_PROT_OFFS_BIT   (13)
#define	DMA_PROT_ADDR_DMA_PROT_OFFS_BITS   (19)
#define	DMA_PROT_ADDR_DMA_PROT_ADDR   (0x00001FFFu)
#define	DMA_PROT_ADDR_DMA_PROT_ADDR_MASK   (0x00001FFFu)
#define	DMA_PROT_ADDR_DMA_PROT_ADDR_BIT   (0)
#define	DMA_PROT_ADDR_DMA_PROT_ADDR_BITS   (13)
#define	DMA_PROT_CH   *((volatile int32u *)0x40005024u)
#define	DMA_PROT_CH_REG   *((volatile int32u *)0x40005024u)
#define	DMA_PROT_CH_ADDR   (0x40005024u)
#define	DMA_PROT_CH_RESET   (0x00000000u)
#define	DMA_PROT_CH_DMA_PROT_CH   (0x00000007u)
#define	DMA_PROT_CH_DMA_PROT_CH_MASK   (0x00000007u)
#define	DMA_PROT_CH_DMA_PROT_CH_BIT   (0)
#define	DMA_PROT_CH_DMA_PROT_CH_BITS   (3)
#define	MEM_PROT_EN   *((volatile int32u *)0x40005028u)
#define	MEM_PROT_EN_REG   *((volatile int32u *)0x40005028u)
#define	MEM_PROT_EN_ADDR   (0x40005028u)
#define	MEM_PROT_EN_RESET   (0x00000000u)
#define	MEM_PROT_EN_FORCE_PROT   (0x00000004u)
#define	MEM_PROT_EN_FORCE_PROT_MASK   (0x00000004u)
#define	MEM_PROT_EN_FORCE_PROT_BIT   (2)
#define	MEM_PROT_EN_FORCE_PROT_BITS   (1)
#define	MEM_PROT_EN_DMA_PROT_EN_MAC   (0x00000002u)
#define	MEM_PROT_EN_DMA_PROT_EN_MAC_MASK   (0x00000002u)
#define	MEM_PROT_EN_DMA_PROT_EN_MAC_BIT   (1)
#define	MEM_PROT_EN_DMA_PROT_EN_MAC_BITS   (1)
#define	MEM_PROT_EN_DMA_PROT_EN_OTHER   (0x00000001u)
#define	MEM_PROT_EN_DMA_PROT_EN_OTHER_MASK   (0x00000001u)
#define	MEM_PROT_EN_DMA_PROT_EN_OTHER_BIT   (0)
#define	MEM_PROT_EN_DMA_PROT_EN_OTHER_BITS   (1)
#define	DATA_SLOW_TIMERS_BASE   (0x40006000u)
#define	DATA_SLOW_TIMERS_END   (0x40006024u)
#define	DATA_SLOW_TIMERS_SIZE   (DATA_SLOW_TIMERS_END - DATA_SLOW_TIMERS_BASE + 1)
#define	WDOG_CFG   *((volatile int32u *)0x40006000u)
#define	WDOG_CFG_REG   *((volatile int32u *)0x40006000u)
#define	WDOG_CFG_ADDR   (0x40006000u)
#define	WDOG_CFG_RESET   (0x00000002u)
#define	WDOG_DISABLE   (0x00000002u)
#define	WDOG_DISABLE_MASK   (0x00000002u)
#define	WDOG_DISABLE_BIT   (1)
#define	WDOG_DISABLE_BITS   (1)
#define	WDOG_ENABLE   (0x00000001u)
#define	WDOG_ENABLE_MASK   (0x00000001u)
#define	WDOG_ENABLE_BIT   (0)
#define	WDOG_ENABLE_BITS   (1)
#define	WDOG_KEY   *((volatile int32u *)0x40006004u)
#define	WDOG_KEY_REG   *((volatile int32u *)0x40006004u)
#define	WDOG_KEY_ADDR   (0x40006004u)
#define	WDOG_KEY_RESET   (0x00000000u)
#define	WDOG_KEY_FIELD   (0x0000FFFFu)
#define	WDOG_KEY_FIELD_MASK   (0x0000FFFFu)
#define	WDOG_KEY_FIELD_BIT   (0)
#define	WDOG_KEY_FIELD_BITS   (16)
#define	WDOG_RESET   *((volatile int32u *)0x40006008u)
#define	WDOG_RESET_REG   *((volatile int32u *)0x40006008u)
#define	WDOG_RESET_ADDR   (0x40006008u)
#define	WDOG_RESET_RESET   (0x00000000u)
#define	SLEEPTMR_CFG   *((volatile int32u *)0x4000600Cu)
#define	SLEEPTMR_CFG_REG   *((volatile int32u *)0x4000600Cu)
#define	SLEEPTMR_CFG_ADDR   (0x4000600Cu)
#define	SLEEPTMR_CFG_RESET   (0x00000400u)
#define	SLEEPTMR_REVERSE   (0x00001000u)
#define	SLEEPTMR_REVERSE_MASK   (0x00001000u)
#define	SLEEPTMR_REVERSE_BIT   (12)
#define	SLEEPTMR_REVERSE_BITS   (1)
#define	SLEEPTMR_ENABLE   (0x00000800u)
#define	SLEEPTMR_ENABLE_MASK   (0x00000800u)
#define	SLEEPTMR_ENABLE_BIT   (11)
#define	SLEEPTMR_ENABLE_BITS   (1)
#define	SLEEPTMR_DBGPAUSE   (0x00000400u)
#define	SLEEPTMR_DBGPAUSE_MASK   (0x00000400u)
#define	SLEEPTMR_DBGPAUSE_BIT   (10)
#define	SLEEPTMR_DBGPAUSE_BITS   (1)
#define	SLEEPTMR_CLKDIV   (0x000000F0u)
#define	SLEEPTMR_CLKDIV_MASK   (0x000000F0u)
#define	SLEEPTMR_CLKDIV_BIT   (4)
#define	SLEEPTMR_CLKDIV_BITS   (4)
#define	SLEEPTMR_CLKSEL   (0x00000001u)
#define	SLEEPTMR_CLKSEL_MASK   (0x00000001u)
#define	SLEEPTMR_CLKSEL_BIT   (0)
#define	SLEEPTMR_CLKSEL_BITS   (1)
#define	SLEEPTMR_CNTH   *((volatile int32u *)0x40006010u)
#define	SLEEPTMR_CNTH_REG   *((volatile int32u *)0x40006010u)
#define	SLEEPTMR_CNTH_ADDR   (0x40006010u)
#define	SLEEPTMR_CNTH_RESET   (0x00000000u)
#define	SLEEPTMR_CNTH_FIELD   (0x0000FFFFu)
#define	SLEEPTMR_CNTH_FIELD_MASK   (0x0000FFFFu)
#define	SLEEPTMR_CNTH_FIELD_BIT   (0)
#define	SLEEPTMR_CNTH_FIELD_BITS   (16)
#define	SLEEPTMR_CNTL   *((volatile int32u *)0x40006014u)
#define	SLEEPTMR_CNTL_REG   *((volatile int32u *)0x40006014u)
#define	SLEEPTMR_CNTL_ADDR   (0x40006014u)
#define	SLEEPTMR_CNTL_RESET   (0x00000000u)
#define	SLEEPTMR_CNTL_FIELD   (0x0000FFFFu)
#define	SLEEPTMR_CNTL_FIELD_MASK   (0x0000FFFFu)
#define	SLEEPTMR_CNTL_FIELD_BIT   (0)
#define	SLEEPTMR_CNTL_FIELD_BITS   (16)
#define	SLEEPTMR_CMPAH   *((volatile int32u *)0x40006018u)
#define	SLEEPTMR_CMPAH_REG   *((volatile int32u *)0x40006018u)
#define	SLEEPTMR_CMPAH_ADDR   (0x40006018u)
#define	SLEEPTMR_CMPAH_RESET   (0x0000FFFFu)
#define	SLEEPTMR_CMPAH_FIELD   (0x0000FFFFu)
#define	SLEEPTMR_CMPAH_FIELD_MASK   (0x0000FFFFu)
#define	SLEEPTMR_CMPAH_FIELD_BIT   (0)
#define	SLEEPTMR_CMPAH_FIELD_BITS   (16)
#define	SLEEPTMR_CMPAL   *((volatile int32u *)0x4000601Cu)
#define	SLEEPTMR_CMPAL_REG   *((volatile int32u *)0x4000601Cu)
#define	SLEEPTMR_CMPAL_ADDR   (0x4000601Cu)
#define	SLEEPTMR_CMPAL_RESET   (0x0000FFFFu)
#define	SLEEPTMR_CMPAL_FIELD   (0x0000FFFFu)
#define	SLEEPTMR_CMPAL_FIELD_MASK   (0x0000FFFFu)
#define	SLEEPTMR_CMPAL_FIELD_BIT   (0)
#define	SLEEPTMR_CMPAL_FIELD_BITS   (16)
#define	SLEEPTMR_CMPBH   *((volatile int32u *)0x40006020u)
#define	SLEEPTMR_CMPBH_REG   *((volatile int32u *)0x40006020u)
#define	SLEEPTMR_CMPBH_ADDR   (0x40006020u)
#define	SLEEPTMR_CMPBH_RESET   (0x0000FFFFu)
#define	SLEEPTMR_CMPBH_FIELD   (0x0000FFFFu)
#define	SLEEPTMR_CMPBH_FIELD_MASK   (0x0000FFFFu)
#define	SLEEPTMR_CMPBH_FIELD_BIT   (0)
#define	SLEEPTMR_CMPBH_FIELD_BITS   (16)
#define	SLEEPTMR_CMPBL   *((volatile int32u *)0x40006024u)
#define	SLEEPTMR_CMPBL_REG   *((volatile int32u *)0x40006024u)
#define	SLEEPTMR_CMPBL_ADDR   (0x40006024u)
#define	SLEEPTMR_CMPBL_RESET   (0x0000FFFFu)
#define	SLEEPTMR_CMPBL_FIELD   (0x0000FFFFu)
#define	SLEEPTMR_CMPBL_FIELD_MASK   (0x0000FFFFu)
#define	SLEEPTMR_CMPBL_FIELD_BIT   (0)
#define	SLEEPTMR_CMPBL_FIELD_BITS   (16)
#define	DATA_CAL_ADC_BASE   (0x40007000u)
#define	DATA_CAL_ADC_END   (0x40007004u)
#define	DATA_CAL_ADC_SIZE   (DATA_CAL_ADC_END - DATA_CAL_ADC_BASE + 1)
#define	CAL_ADC_DATA   *((volatile int32u *)0x40007000u)
#define	CAL_ADC_DATA_REG   *((volatile int32u *)0x40007000u)
#define	CAL_ADC_DATA_ADDR   (0x40007000u)
#define	CAL_ADC_DATA_RESET   (0x00000000u)
#define	CAL_ADC_DATA_CAL_ADC_DATA   (0x0000FFFFu)
#define	CAL_ADC_DATA_CAL_ADC_DATA_MASK   (0x0000FFFFu)
#define	CAL_ADC_DATA_CAL_ADC_DATA_BIT   (0)
#define	CAL_ADC_DATA_CAL_ADC_DATA_BITS   (16)
#define	CAL_ADC_CONFIG   *((volatile int32u *)0x40007004u)
#define	CAL_ADC_CONFIG_REG   *((volatile int32u *)0x40007004u)
#define	CAL_ADC_CONFIG_ADDR   (0x40007004u)
#define	CAL_ADC_CONFIG_RESET   (0x00000000u)
#define	CAL_ADC_CONFIG_CAL_ADC_RATE   (0x00007000u)
#define	CAL_ADC_CONFIG_CAL_ADC_RATE_MASK   (0x00007000u)
#define	CAL_ADC_CONFIG_CAL_ADC_RATE_BIT   (12)
#define	CAL_ADC_CONFIG_CAL_ADC_RATE_BITS   (3)
#define	CAL_ADC_CONFIG_CAL_ADC_MUX   (0x00000F80u)
#define	CAL_ADC_CONFIG_CAL_ADC_MUX_MASK   (0x00000F80u)
#define	CAL_ADC_CONFIG_CAL_ADC_MUX_BIT   (7)
#define	CAL_ADC_CONFIG_CAL_ADC_MUX_BITS   (5)
#define	CAL_ADC_CONFIG_CAL_ADC_CLKSEL   (0x00000004u)
#define	CAL_ADC_CONFIG_CAL_ADC_CLKSEL_MASK   (0x00000004u)
#define	CAL_ADC_CONFIG_CAL_ADC_CLKSEL_BIT   (2)
#define	CAL_ADC_CONFIG_CAL_ADC_CLKSEL_BITS   (1)
#define	CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS   (0x00000002u)
#define	CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS_MASK   (0x00000002u)
#define	CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS_BIT   (1)
#define	CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS_BITS   (1)
#define	CAL_ADC_CONFIG_CAL_ADC_EN   (0x00000001u)
#define	CAL_ADC_CONFIG_CAL_ADC_EN_MASK   (0x00000001u)
#define	CAL_ADC_CONFIG_CAL_ADC_EN_BIT   (0)
#define	CAL_ADC_CONFIG_CAL_ADC_EN_BITS   (1)
#define	DATA_FLASH_CONTROL_BASE   (0x40008000u)
#define	DATA_FLASH_CONTROL_END   (0x40008084u)
#define	DATA_FLASH_CONTROL_SIZE   (DATA_FLASH_CONTROL_END - DATA_FLASH_CONTROL_BASE + 1)
#define	FLASH_ACCESS   *((volatile int32u *)0x40008000u)
#define	FLASH_ACCESS_REG   *((volatile int32u *)0x40008000u)
#define	FLASH_ACCESS_ADDR   (0x40008000u)
#define	FLASH_ACCESS_RESET   (0x00000031u)
#define	FLASH_ACCESS_PREFETCH_STATUS   (0x00000020u)
#define	FLASH_ACCESS_PREFETCH_STATUS_MASK   (0x00000020u)
#define	FLASH_ACCESS_PREFETCH_STATUS_BIT   (5)
#define	FLASH_ACCESS_PREFETCH_STATUS_BITS   (1)
#define	FLASH_ACCESS_PREFETCH_EN   (0x00000010u)
#define	FLASH_ACCESS_PREFETCH_EN_MASK   (0x00000010u)
#define	FLASH_ACCESS_PREFETCH_EN_BIT   (4)
#define	FLASH_ACCESS_PREFETCH_EN_BITS   (1)
#define	FLASH_ACCESS_HALFCYCLE_ACCESS   (0x00000008u)
#define	FLASH_ACCESS_HALFCYCLE_ACCESS_MASK   (0x00000008u)
#define	FLASH_ACCESS_HALFCYCLE_ACCESS_BIT   (3)
#define	FLASH_ACCESS_HALFCYCLE_ACCESS_BITS   (1)
#define	FLASH_ACCESS_CODE_LATENCY   (0x00000007u)
#define	FLASH_ACCESS_CODE_LATENCY_MASK   (0x00000007u)
#define	FLASH_ACCESS_CODE_LATENCY_BIT   (0)
#define	FLASH_ACCESS_CODE_LATENCY_BITS   (3)
#define	FPEC_KEY   *((volatile int32u *)0x40008004u)
#define	FPEC_KEY_REG   *((volatile int32u *)0x40008004u)
#define	FPEC_KEY_ADDR   (0x40008004u)
#define	FPEC_KEY_RESET   (0x00000000u)
#define	FPEC_KEY_FKEYR   (0xFFFFFFFFu)
#define	FPEC_KEY_FKEYR_MASK   (0xFFFFFFFFu)
#define	FPEC_KEY_FKEYR_BIT   (0)
#define	FPEC_KEY_FKEYR_BITS   (32)
#define	OPT_KEY   *((volatile int32u *)0x40008008u)
#define	OPT_KEY_REG   *((volatile int32u *)0x40008008u)
#define	OPT_KEY_ADDR   (0x40008008u)
#define	OPT_KEY_RESET   (0x00000000u)
#define	OPT_KEY_OPTKEYR   (0xFFFFFFFFu)
#define	OPT_KEY_OPTKEYR_MASK   (0xFFFFFFFFu)
#define	OPT_KEY_OPTKEYR_BIT   (0)
#define	OPT_KEY_OPTKEYR_BITS   (32)
#define	FLASH_STATUS   *((volatile int32u *)0x4000800Cu)
#define	FLASH_STATUS_REG   *((volatile int32u *)0x4000800Cu)
#define	FLASH_STATUS_ADDR   (0x4000800Cu)
#define	FLASH_STATUS_RESET   (0x00000000u)
#define	FLASH_STATUS_EOP   (0x00000020u)
#define	FLASH_STATUS_EOP_MASK   (0x00000020u)
#define	FLASH_STATUS_EOP_BIT   (5)
#define	FLASH_STATUS_EOP_BITS   (1)
#define	FLASH_STATUS_WRP_ERR   (0x00000010u)
#define	FLASH_STATUS_WRP_ERR_MASK   (0x00000010u)
#define	FLASH_STATUS_WRP_ERR_BIT   (4)
#define	FLASH_STATUS_WRP_ERR_BITS   (1)
#define	FLASH_STATUS_PAGE_PROG_ERR   (0x00000008u)
#define	FLASH_STATUS_PAGE_PROG_ERR_MASK   (0x00000008u)
#define	FLASH_STATUS_PAGE_PROG_ERR_BIT   (3)
#define	FLASH_STATUS_PAGE_PROG_ERR_BITS   (1)
#define	FLASH_STATUS_PROG_ERR   (0x00000004u)
#define	FLASH_STATUS_PROG_ERR_MASK   (0x00000004u)
#define	FLASH_STATUS_PROG_ERR_BIT   (2)
#define	FLASH_STATUS_PROG_ERR_BITS   (1)
#define	FLASH_STATUS_EARLY_BSY   (0x00000002u)
#define	FLASH_STATUS_EARLY_BSY_MASK   (0x00000002u)
#define	FLASH_STATUS_EARLY_BSY_BIT   (1)
#define	FLASH_STATUS_EARLY_BSY_BITS   (1)
#define	FLASH_STATUS_FLA_BSY   (0x00000001u)
#define	FLASH_STATUS_FLA_BSY_MASK   (0x00000001u)
#define	FLASH_STATUS_FLA_BSY_BIT   (0)
#define	FLASH_STATUS_FLA_BSY_BITS   (1)
#define	FLASH_CTRL   *((volatile int32u *)0x40008010u)
#define	FLASH_CTRL_REG   *((volatile int32u *)0x40008010u)
#define	FLASH_CTRL_ADDR   (0x40008010u)
#define	FLASH_CTRL_RESET   (0x00000080u)
#define	FLASH_CTRL_EOPIE   (0x00001000u)
#define	FLASH_CTRL_EOPIE_MASK   (0x00001000u)
#define	FLASH_CTRL_EOPIE_BIT   (12)
#define	FLASH_CTRL_EOPIE_BITS   (1)
#define	FLASH_CTRL_EARLYBSYIE   (0x00000800u)
#define	FLASH_CTRL_EARLYBSYIE_MASK   (0x00000800u)
#define	FLASH_CTRL_EARLYBSYIE_BIT   (11)
#define	FLASH_CTRL_EARLYBSYIE_BITS   (1)
#define	FLASH_CTRL_ERRIE   (0x00000400u)
#define	FLASH_CTRL_ERRIE_MASK   (0x00000400u)
#define	FLASH_CTRL_ERRIE_BIT   (10)
#define	FLASH_CTRL_ERRIE_BITS   (1)
#define	FLASH_CTRL_OPTWREN   (0x00000200u)
#define	FLASH_CTRL_OPTWREN_MASK   (0x00000200u)
#define	FLASH_CTRL_OPTWREN_BIT   (9)
#define	FLASH_CTRL_OPTWREN_BITS   (1)
#define	FLASH_CTRL_FSTPROG   (0x00000100u)
#define	FLASH_CTRL_FSTPROG_MASK   (0x00000100u)
#define	FLASH_CTRL_FSTPROG_BIT   (8)
#define	FLASH_CTRL_FSTPROG_BITS   (1)
#define	FLASH_CTRL_LOCK   (0x00000080u)
#define	FLASH_CTRL_LOCK_MASK   (0x00000080u)
#define	FLASH_CTRL_LOCK_BIT   (7)
#define	FLASH_CTRL_LOCK_BITS   (1)
#define	FLASH_CTRL_FLA_START   (0x00000040u)
#define	FLASH_CTRL_FLA_START_MASK   (0x00000040u)
#define	FLASH_CTRL_FLA_START_BIT   (6)
#define	FLASH_CTRL_FLA_START_BITS   (1)
#define	FLASH_CTRL_OPTERASE   (0x00000020u)
#define	FLASH_CTRL_OPTERASE_MASK   (0x00000020u)
#define	FLASH_CTRL_OPTERASE_BIT   (5)
#define	FLASH_CTRL_OPTERASE_BITS   (1)
#define	FLASH_CTRL_OPTPROG   (0x00000010u)
#define	FLASH_CTRL_OPTPROG_MASK   (0x00000010u)
#define	FLASH_CTRL_OPTPROG_BIT   (4)
#define	FLASH_CTRL_OPTPROG_BITS   (1)
#define	FLASH_CTRL_GLOBALERASE   (0x00000008u)
#define	FLASH_CTRL_GLOBALERASE_MASK   (0x00000008u)
#define	FLASH_CTRL_GLOBALERASE_BIT   (3)
#define	FLASH_CTRL_GLOBALERASE_BITS   (1)
#define	FLASH_CTRL_MASSERASE   (0x00000004u)
#define	FLASH_CTRL_MASSERASE_MASK   (0x00000004u)
#define	FLASH_CTRL_MASSERASE_BIT   (2)
#define	FLASH_CTRL_MASSERASE_BITS   (1)
#define	FLASH_CTRL_PAGEERASE   (0x00000002u)
#define	FLASH_CTRL_PAGEERASE_MASK   (0x00000002u)
#define	FLASH_CTRL_PAGEERASE_BIT   (1)
#define	FLASH_CTRL_PAGEERASE_BITS   (1)
#define	FLASH_CTRL_PROG   (0x00000001u)
#define	FLASH_CTRL_PROG_MASK   (0x00000001u)
#define	FLASH_CTRL_PROG_BIT   (0)
#define	FLASH_CTRL_PROG_BITS   (1)
#define	FLASH_ADDR   *((volatile int32u *)0x40008014u)
#define	FLASH_ADDR_REG   *((volatile int32u *)0x40008014u)
#define	FLASH_ADDR_ADDR   (0x40008014u)
#define	FLASH_ADDR_RESET   (0x00000000u)
#define	FLASH_ADDR_FAR   (0xFFFFFFFFu)
#define	FLASH_ADDR_FAR_MASK   (0xFFFFFFFFu)
#define	FLASH_ADDR_FAR_BIT   (0)
#define	FLASH_ADDR_FAR_BITS   (32)
#define	OPT_BYTE   *((volatile int32u *)0x4000801Cu)
#define	OPT_BYTE_REG   *((volatile int32u *)0x4000801Cu)
#define	OPT_BYTE_ADDR   (0x4000801Cu)
#define	OPT_BYTE_RESET   (0xFBFFFFFEu)
#define	OPT_BYTE_RSVD   (0xF8000000u)
#define	OPT_BYTE_RSVD_MASK   (0xF8000000u)
#define	OPT_BYTE_RSVD_BIT   (27)
#define	OPT_BYTE_RSVD_BITS   (5)
#define	OPT_BYTE_OBR   (0x07FFFFFCu)
#define	OPT_BYTE_OBR_MASK   (0x07FFFFFCu)
#define	OPT_BYTE_OBR_BIT   (2)
#define	OPT_BYTE_OBR_BITS   (25)
#define	OPT_BYTE_RDPROT   (0x00000002u)
#define	OPT_BYTE_RDPROT_MASK   (0x00000002u)
#define	OPT_BYTE_RDPROT_BIT   (1)
#define	OPT_BYTE_RDPROT_BITS   (1)
#define	OPT_BYTE_OPT_ERR   (0x00000001u)
#define	OPT_BYTE_OPT_ERR_MASK   (0x00000001u)
#define	OPT_BYTE_OPT_ERR_BIT   (0)
#define	OPT_BYTE_OPT_ERR_BITS   (1)
#define	WRPROT   *((volatile int32u *)0x40008020u)
#define	WRPROT_REG   *((volatile int32u *)0x40008020u)
#define	WRPROT_ADDR   (0x40008020u)
#define	WRPROT_RESET   (0xFFFFFFFFu)
#define	WRPROT_WRP   (0xFFFFFFFFu)
#define	WRPROT_WRP_MASK   (0xFFFFFFFFu)
#define	WRPROT_WRP_BIT   (0)
#define	WRPROT_WRP_BITS   (32)
#define	FLASH_TEST_CTRL   *((volatile int32u *)0x40008080u)
#define	FLASH_TEST_CTRL_REG   *((volatile int32u *)0x40008080u)
#define	FLASH_TEST_CTRL_ADDR   (0x40008080u)
#define	FLASH_TEST_CTRL_RESET   (0x00000000u)
#define	FLASH_TEST_CTRL_TMR   (0x00001000u)
#define	FLASH_TEST_CTRL_TMR_MASK   (0x00001000u)
#define	FLASH_TEST_CTRL_TMR_BIT   (12)
#define	FLASH_TEST_CTRL_TMR_BITS   (1)
#define	FLASH_TEST_CTRL_ERASE   (0x00000800u)
#define	FLASH_TEST_CTRL_ERASE_MASK   (0x00000800u)
#define	FLASH_TEST_CTRL_ERASE_BIT   (11)
#define	FLASH_TEST_CTRL_ERASE_BITS   (1)
#define	FLASH_TEST_CTRL_MAS1   (0x00000400u)
#define	FLASH_TEST_CTRL_MAS1_MASK   (0x00000400u)
#define	FLASH_TEST_CTRL_MAS1_BIT   (10)
#define	FLASH_TEST_CTRL_MAS1_BITS   (1)
#define	FLASH_TEST_CTRL_TEST_PROG   (0x00000200u)
#define	FLASH_TEST_CTRL_TEST_PROG_MASK   (0x00000200u)
#define	FLASH_TEST_CTRL_TEST_PROG_BIT   (9)
#define	FLASH_TEST_CTRL_TEST_PROG_BITS   (1)
#define	FLASH_TEST_CTRL_NVSTR   (0x00000100u)
#define	FLASH_TEST_CTRL_NVSTR_MASK   (0x00000100u)
#define	FLASH_TEST_CTRL_NVSTR_BIT   (8)
#define	FLASH_TEST_CTRL_NVSTR_BITS   (1)
#define	FLASH_TEST_CTRL_SE   (0x00000080u)
#define	FLASH_TEST_CTRL_SE_MASK   (0x00000080u)
#define	FLASH_TEST_CTRL_SE_BIT   (7)
#define	FLASH_TEST_CTRL_SE_BITS   (1)
#define	FLASH_TEST_CTRL_IFREN   (0x00000040u)
#define	FLASH_TEST_CTRL_IFREN_MASK   (0x00000040u)
#define	FLASH_TEST_CTRL_IFREN_BIT   (6)
#define	FLASH_TEST_CTRL_IFREN_BITS   (1)
#define	FLASH_TEST_CTRL_YE   (0x00000020u)
#define	FLASH_TEST_CTRL_YE_MASK   (0x00000020u)
#define	FLASH_TEST_CTRL_YE_BIT   (5)
#define	FLASH_TEST_CTRL_YE_BITS   (1)
#define	FLASH_TEST_CTRL_XE   (0x00000010u)
#define	FLASH_TEST_CTRL_XE_MASK   (0x00000010u)
#define	FLASH_TEST_CTRL_XE_BIT   (4)
#define	FLASH_TEST_CTRL_XE_BITS   (1)
#define	FLASH_TEST_CTRL_SW_CTRL   (0x00000008u)
#define	FLASH_TEST_CTRL_SW_CTRL_MASK   (0x00000008u)
#define	FLASH_TEST_CTRL_SW_CTRL_BIT   (3)
#define	FLASH_TEST_CTRL_SW_CTRL_BITS   (1)
#define	FLASH_TEST_CTRL_SW   (0x00000006u)
#define	FLASH_TEST_CTRL_SW_MASK   (0x00000006u)
#define	FLASH_TEST_CTRL_SW_BIT   (1)
#define	FLASH_TEST_CTRL_SW_BITS   (2)
#define	FLASH_TEST_CTRL_SW_EN   (0x00000001u)
#define	FLASH_TEST_CTRL_SW_EN_MASK   (0x00000001u)
#define	FLASH_TEST_CTRL_SW_EN_BIT   (0)
#define	FLASH_TEST_CTRL_SW_EN_BITS   (1)
#define	FLASH_DATA0   *((volatile int32u *)0x40008084u)
#define	FLASH_DATA0_REG   *((volatile int32u *)0x40008084u)
#define	FLASH_DATA0_ADDR   (0x40008084u)
#define	FLASH_DATA0_RESET   (0xFFFFFFFFu)
#define	FLASH_DATA0_FDR0   (0xFFFFFFFFu)
#define	FLASH_DATA0_FDR0_MASK   (0xFFFFFFFFu)
#define	FLASH_DATA0_FDR0_BIT   (0)
#define	FLASH_DATA0_FDR0_BITS   (32)
#define	DATA_EMU_REGS_BASE   (0x40009000u)
#define	DATA_EMU_REGS_END   (0x40009000u)
#define	DATA_EMU_REGS_SIZE   (DATA_EMU_REGS_END - DATA_EMU_REGS_BASE + 1)
#define	I_AM_AN_EMULATOR   *((volatile int32u *)0x40009000u)
#define	I_AM_AN_EMULATOR_REG   *((volatile int32u *)0x40009000u)
#define	I_AM_AN_EMULATOR_ADDR   (0x40009000u)
#define	I_AM_AN_EMULATOR_RESET   (0x00000000u)
#define	I_AM_AN_EMULATOR_I_AM_AN_EMULATOR   (0x00000001u)
#define	I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_MASK   (0x00000001u)
#define	I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_BIT   (0)
#define	I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_BITS   (1)
#define	BLOCK_INTERRUPTS_BASE   (0x4000A000u)
#define	BLOCK_INTERRUPTS_END   (0x4000A86Cu)
#define	BLOCK_INTERRUPTS_SIZE   (BLOCK_INTERRUPTS_END - BLOCK_INTERRUPTS_BASE + 1)
#define	MAC_RX_INT_SRC   *((volatile int32u *)0x4000A000u)
#define	MAC_RX_INT_SRC_REG   *((volatile int32u *)0x4000A000u)
#define	MAC_RX_INT_SRC_ADDR   (0x4000A000u)
#define	MAC_RX_INT_SRC_RESET   (0x00000000u)
#define	MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC   (0x00008000u)
#define	MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC_MASK   (0x00008000u)
#define	MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC_BIT   (15)
#define	MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC_BITS   (1)
#define	MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC   (0x00004000u)
#define	MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC_MASK   (0x00004000u)
#define	MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC_BIT   (14)
#define	MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC_BITS   (1)
#define	MAC_RX_INT_SRC_RX_OVFLW_SRC   (0x00002000u)
#define	MAC_RX_INT_SRC_RX_OVFLW_SRC_MASK   (0x00002000u)
#define	MAC_RX_INT_SRC_RX_OVFLW_SRC_BIT   (13)
#define	MAC_RX_INT_SRC_RX_OVFLW_SRC_BITS   (1)
#define	MAC_RX_INT_SRC_RX_ERROR_SRC   (0x00001000u)
#define	MAC_RX_INT_SRC_RX_ERROR_SRC_MASK   (0x00001000u)
#define	MAC_RX_INT_SRC_RX_ERROR_SRC_BIT   (12)
#define	MAC_RX_INT_SRC_RX_ERROR_SRC_BITS   (1)
#define	MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC   (0x00000800u)
#define	MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC_MASK   (0x00000800u)
#define	MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC_BIT   (11)
#define	MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC_BITS   (1)
#define	MAC_RX_INT_SRC_TX_COLL_RX_SRC   (0x00000400u)
#define	MAC_RX_INT_SRC_TX_COLL_RX_SRC_MASK   (0x00000400u)
#define	MAC_RX_INT_SRC_TX_COLL_RX_SRC_BIT   (10)
#define	MAC_RX_INT_SRC_TX_COLL_RX_SRC_BITS   (1)
#define	MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC   (0x00000200u)
#define	MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC_MASK   (0x00000200u)
#define	MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC_BIT   (9)
#define	MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC_BITS   (1)
#define	MAC_RX_INT_SRC_TX_B_ACK_SRC   (0x00000100u)
#define	MAC_RX_INT_SRC_TX_B_ACK_SRC_MASK   (0x00000100u)
#define	MAC_RX_INT_SRC_TX_B_ACK_SRC_BIT   (8)
#define	MAC_RX_INT_SRC_TX_B_ACK_SRC_BITS   (1)
#define	MAC_RX_INT_SRC_TX_A_ACK_SRC   (0x00000080u)
#define	MAC_RX_INT_SRC_TX_A_ACK_SRC_MASK   (0x00000080u)
#define	MAC_RX_INT_SRC_TX_A_ACK_SRC_BIT   (7)
#define	MAC_RX_INT_SRC_TX_A_ACK_SRC_BITS   (1)
#define	MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC   (0x00000040u)
#define	MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC_MASK   (0x00000040u)
#define	MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC_BIT   (6)
#define	MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC_BITS   (1)
#define	MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC   (0x00000020u)
#define	MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC_MASK   (0x00000020u)
#define	MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC_BIT   (5)
#define	MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC_BITS   (1)
#define	MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC   (0x00000010u)
#define	MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC_MASK   (0x00000010u)
#define	MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC_BIT   (4)
#define	MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC_BITS   (1)
#define	MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC   (0x00000008u)
#define	MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC_MASK   (0x00000008u)
#define	MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC_BIT   (3)
#define	MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC_BITS   (1)
#define	MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC   (0x00000004u)
#define	MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC_MASK   (0x00000004u)
#define	MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC_BIT   (2)
#define	MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC_BITS   (1)
#define	MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC   (0x00000002u)
#define	MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC_MASK   (0x00000002u)
#define	MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC_BIT   (1)
#define	MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC_BITS   (1)
#define	MAC_RX_INT_SRC_RX_FRAME_SRC   (0x00000001u)
#define	MAC_RX_INT_SRC_RX_FRAME_SRC_MASK   (0x00000001u)
#define	MAC_RX_INT_SRC_RX_FRAME_SRC_BIT   (0)
#define	MAC_RX_INT_SRC_RX_FRAME_SRC_BITS   (1)
#define	MAC_TX_INT_SRC   *((volatile int32u *)0x4000A004u)
#define	MAC_TX_INT_SRC_REG   *((volatile int32u *)0x4000A004u)
#define	MAC_TX_INT_SRC_ADDR   (0x4000A004u)
#define	MAC_TX_INT_SRC_RESET   (0x00000000u)
#define	MAC_TX_INT_SRC_RX_B_ACK_SRC   (0x00000800u)
#define	MAC_TX_INT_SRC_RX_B_ACK_SRC_MASK   (0x00000800u)
#define	MAC_TX_INT_SRC_RX_B_ACK_SRC_BIT   (11)
#define	MAC_TX_INT_SRC_RX_B_ACK_SRC_BITS   (1)
#define	MAC_TX_INT_SRC_RX_A_ACK_SRC   (0x00000400u)
#define	MAC_TX_INT_SRC_RX_A_ACK_SRC_MASK   (0x00000400u)
#define	MAC_TX_INT_SRC_RX_A_ACK_SRC_BIT   (10)
#define	MAC_TX_INT_SRC_RX_A_ACK_SRC_BITS   (1)
#define	MAC_TX_INT_SRC_TX_B_UNLOAD_SRC   (0x00000200u)
#define	MAC_TX_INT_SRC_TX_B_UNLOAD_SRC_MASK   (0x00000200u)
#define	MAC_TX_INT_SRC_TX_B_UNLOAD_SRC_BIT   (9)
#define	MAC_TX_INT_SRC_TX_B_UNLOAD_SRC_BITS   (1)
#define	MAC_TX_INT_SRC_TX_A_UNLOAD_SRC   (0x00000100u)
#define	MAC_TX_INT_SRC_TX_A_UNLOAD_SRC_MASK   (0x00000100u)
#define	MAC_TX_INT_SRC_TX_A_UNLOAD_SRC_BIT   (8)
#define	MAC_TX_INT_SRC_TX_A_UNLOAD_SRC_BITS   (1)
#define	MAC_TX_INT_SRC_ACK_EXPIRED_SRC   (0x00000080u)
#define	MAC_TX_INT_SRC_ACK_EXPIRED_SRC_MASK   (0x00000080u)
#define	MAC_TX_INT_SRC_ACK_EXPIRED_SRC_BIT   (7)
#define	MAC_TX_INT_SRC_ACK_EXPIRED_SRC_BITS   (1)
#define	MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC   (0x00000040u)
#define	MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC_MASK   (0x00000040u)
#define	MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC_BIT   (6)
#define	MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC_BITS   (1)
#define	MAC_TX_INT_SRC_TX_UNDERFLOW_SRC   (0x00000020u)
#define	MAC_TX_INT_SRC_TX_UNDERFLOW_SRC_MASK   (0x00000020u)
#define	MAC_TX_INT_SRC_TX_UNDERFLOW_SRC_BIT   (5)
#define	MAC_TX_INT_SRC_TX_UNDERFLOW_SRC_BITS   (1)
#define	MAC_TX_INT_SRC_CCA_FAIL_SRC   (0x00000010u)
#define	MAC_TX_INT_SRC_CCA_FAIL_SRC_MASK   (0x00000010u)
#define	MAC_TX_INT_SRC_CCA_FAIL_SRC_BIT   (4)
#define	MAC_TX_INT_SRC_CCA_FAIL_SRC_BITS   (1)
#define	MAC_TX_INT_SRC_SFD_SENT_SRC   (0x00000008u)
#define	MAC_TX_INT_SRC_SFD_SENT_SRC_MASK   (0x00000008u)
#define	MAC_TX_INT_SRC_SFD_SENT_SRC_BIT   (3)
#define	MAC_TX_INT_SRC_SFD_SENT_SRC_BITS   (1)
#define	MAC_TX_INT_SRC_BO_COMPLETE_SRC   (0x00000004u)
#define	MAC_TX_INT_SRC_BO_COMPLETE_SRC_MASK   (0x00000004u)
#define	MAC_TX_INT_SRC_BO_COMPLETE_SRC_BIT   (2)
#define	MAC_TX_INT_SRC_BO_COMPLETE_SRC_BITS   (1)
#define	MAC_TX_INT_SRC_RX_ACK_SRC   (0x00000002u)
#define	MAC_TX_INT_SRC_RX_ACK_SRC_MASK   (0x00000002u)
#define	MAC_TX_INT_SRC_RX_ACK_SRC_BIT   (1)
#define	MAC_TX_INT_SRC_RX_ACK_SRC_BITS   (1)
#define	MAC_TX_INT_SRC_TX_COMPLETE_SRC   (0x00000001u)
#define	MAC_TX_INT_SRC_TX_COMPLETE_SRC_MASK   (0x00000001u)
#define	MAC_TX_INT_SRC_TX_COMPLETE_SRC_BIT   (0)
#define	MAC_TX_INT_SRC_TX_COMPLETE_SRC_BITS   (1)
#define	MAC_TIMER_INT_SRC   *((volatile int32u *)0x4000A008u)
#define	MAC_TIMER_INT_SRC_REG   *((volatile int32u *)0x4000A008u)
#define	MAC_TIMER_INT_SRC_ADDR   (0x4000A008u)
#define	MAC_TIMER_INT_SRC_RESET   (0x00000000u)
#define	MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC   (0x00000004u)
#define	MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC_MASK   (0x00000004u)
#define	MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC_BIT   (2)
#define	MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC_BITS   (1)
#define	MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC   (0x00000002u)
#define	MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC_MASK   (0x00000002u)
#define	MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC_BIT   (1)
#define	MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC_BITS   (1)
#define	MAC_TIMER_INT_SRC_TIMER_WRAP_SRC   (0x00000001u)
#define	MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_MASK   (0x00000001u)
#define	MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_BIT   (0)
#define	MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_BITS   (1)
#define	BB_INT_SRC   *((volatile int32u *)0x4000A00Cu)
#define	BB_INT_SRC_REG   *((volatile int32u *)0x4000A00Cu)
#define	BB_INT_SRC_ADDR   (0x4000A00Cu)
#define	BB_INT_SRC_RESET   (0x00000000u)
#define	BB_INT_SRC_RSSI_INT_SRC   (0x00000002u)
#define	BB_INT_SRC_RSSI_INT_SRC_MASK   (0x00000002u)
#define	BB_INT_SRC_RSSI_INT_SRC_BIT   (1)
#define	BB_INT_SRC_RSSI_INT_SRC_BITS   (1)
#define	BB_INT_SRC_BASEBAND_INT_SRC   (0x00000001u)
#define	BB_INT_SRC_BASEBAND_INT_SRC_MASK   (0x00000001u)
#define	BB_INT_SRC_BASEBAND_INT_SRC_BIT   (0)
#define	BB_INT_SRC_BASEBAND_INT_SRC_BITS   (1)
#define	SEC_INT_SRC   *((volatile int32u *)0x4000A010u)
#define	SEC_INT_SRC_REG   *((volatile int32u *)0x4000A010u)
#define	SEC_INT_SRC_ADDR   (0x4000A010u)
#define	SEC_INT_SRC_RESET   (0x00000000u)
#define	SEC_INT_SRC_CT_WORD_VALID_SRC   (0x00000004u)
#define	SEC_INT_SRC_CT_WORD_VALID_SRC_MASK   (0x00000004u)
#define	SEC_INT_SRC_CT_WORD_VALID_SRC_BIT   (2)
#define	SEC_INT_SRC_CT_WORD_VALID_SRC_BITS   (1)
#define	SEC_INT_SRC_PT_WORD_REQ_SRC   (0x00000002u)
#define	SEC_INT_SRC_PT_WORD_REQ_SRC_MASK   (0x00000002u)
#define	SEC_INT_SRC_PT_WORD_REQ_SRC_BIT   (1)
#define	SEC_INT_SRC_PT_WORD_REQ_SRC_BITS   (1)
#define	SEC_INT_SRC_ENC_COMPLETE_SRC   (0x00000001u)
#define	SEC_INT_SRC_ENC_COMPLETE_SRC_MASK   (0x00000001u)
#define	SEC_INT_SRC_ENC_COMPLETE_SRC_BIT   (0)
#define	SEC_INT_SRC_ENC_COMPLETE_SRC_BITS   (1)
#define	INT_SLEEPTMRFLAG   *((volatile int32u *)0x4000A014u)
#define	INT_SLEEPTMRFLAG_REG   *((volatile int32u *)0x4000A014u)
#define	INT_SLEEPTMRFLAG_ADDR   (0x4000A014u)
#define	INT_SLEEPTMRFLAG_RESET   (0x00000000u)
#define	INT_SLEEPTMRCMPB   (0x00000004u)
#define	INT_SLEEPTMRCMPB_MASK   (0x00000004u)
#define	INT_SLEEPTMRCMPB_BIT   (2)
#define	INT_SLEEPTMRCMPB_BITS   (1)
#define	INT_SLEEPTMRCMPA   (0x00000002u)
#define	INT_SLEEPTMRCMPA_MASK   (0x00000002u)
#define	INT_SLEEPTMRCMPA_BIT   (1)
#define	INT_SLEEPTMRCMPA_BITS   (1)
#define	INT_SLEEPTMRWRAP   (0x00000001u)
#define	INT_SLEEPTMRWRAP_MASK   (0x00000001u)
#define	INT_SLEEPTMRWRAP_BIT   (0)
#define	INT_SLEEPTMRWRAP_BITS   (1)
#define	INT_MGMTFLAG   *((volatile int32u *)0x4000A018u)
#define	INT_MGMTFLAG_REG   *((volatile int32u *)0x4000A018u)
#define	INT_MGMTFLAG_ADDR   (0x4000A018u)
#define	INT_MGMTFLAG_RESET   (0x00000000u)
#define	INT_MGMTDMAPROT   (0x00000010u)
#define	INT_MGMTDMAPROT_MASK   (0x00000010u)
#define	INT_MGMTDMAPROT_BIT   (4)
#define	INT_MGMTDMAPROT_BITS   (1)
#define	INT_MGMTCALADC   (0x00000008u)
#define	INT_MGMTCALADC_MASK   (0x00000008u)
#define	INT_MGMTCALADC_BIT   (3)
#define	INT_MGMTCALADC_BITS   (1)
#define	INT_MGMTFPEC   (0x00000004u)
#define	INT_MGMTFPEC_MASK   (0x00000004u)
#define	INT_MGMTFPEC_BIT   (2)
#define	INT_MGMTFPEC_BITS   (1)
#define	INT_MGMTOSC24MHI   (0x00000002u)
#define	INT_MGMTOSC24MHI_MASK   (0x00000002u)
#define	INT_MGMTOSC24MHI_BIT   (1)
#define	INT_MGMTOSC24MHI_BITS   (1)
#define	INT_MGMTOSC24MLO   (0x00000001u)
#define	INT_MGMTOSC24MLO_MASK   (0x00000001u)
#define	INT_MGMTOSC24MLO_BIT   (0)
#define	INT_MGMTOSC24MLO_BITS   (1)
#define	INT_NMIFLAG   *((volatile int32u *)0x4000A01Cu)
#define	INT_NMIFLAG_REG   *((volatile int32u *)0x4000A01Cu)
#define	INT_NMIFLAG_ADDR   (0x4000A01Cu)
#define	INT_NMIFLAG_RESET   (0x00000000u)
#define	INT_NMICLK24M   (0x00000002u)
#define	INT_NMICLK24M_MASK   (0x00000002u)
#define	INT_NMICLK24M_BIT   (1)
#define	INT_NMICLK24M_BITS   (1)
#define	INT_NMIWDOG   (0x00000001u)
#define	INT_NMIWDOG_MASK   (0x00000001u)
#define	INT_NMIWDOG_BIT   (0)
#define	INT_NMIWDOG_BITS   (1)
#define	INT_SLEEPTMRFORCE   *((volatile int32u *)0x4000A020u)
#define	INT_SLEEPTMRFORCE_REG   *((volatile int32u *)0x4000A020u)
#define	INT_SLEEPTMRFORCE_ADDR   (0x4000A020u)
#define	INT_SLEEPTMRFORCE_RESET   (0x00000000u)
#define	INT_SLEEPTMRCMPB   (0x00000004u)
#define	INT_SLEEPTMRCMPB_MASK   (0x00000004u)
#define	INT_SLEEPTMRCMPB_BIT   (2)
#define	INT_SLEEPTMRCMPB_BITS   (1)
#define	INT_SLEEPTMRCMPA   (0x00000002u)
#define	INT_SLEEPTMRCMPA_MASK   (0x00000002u)
#define	INT_SLEEPTMRCMPA_BIT   (1)
#define	INT_SLEEPTMRCMPA_BITS   (1)
#define	INT_SLEEPTMRWRAP   (0x00000001u)
#define	INT_SLEEPTMRWRAP_MASK   (0x00000001u)
#define	INT_SLEEPTMRWRAP_BIT   (0)
#define	INT_SLEEPTMRWRAP_BITS   (1)
#define	TEST_FORCE_ALL_INT   *((volatile int32u *)0x4000A024u)
#define	TEST_FORCE_ALL_INT_REG   *((volatile int32u *)0x4000A024u)
#define	TEST_FORCE_ALL_INT_ADDR   (0x4000A024u)
#define	TEST_FORCE_ALL_INT_RESET   (0x00000000u)
#define	TEST_FORCE_ALL_INT_FORCE_ALL_INT   (0x00000001u)
#define	TEST_FORCE_ALL_INT_FORCE_ALL_INT_MASK   (0x00000001u)
#define	TEST_FORCE_ALL_INT_FORCE_ALL_INT_BIT   (0)
#define	TEST_FORCE_ALL_INT_FORCE_ALL_INT_BITS   (1)
#define	MAC_RX_INT_MASK   *((volatile int32u *)0x4000A040u)
#define	MAC_RX_INT_MASK_REG   *((volatile int32u *)0x4000A040u)
#define	MAC_RX_INT_MASK_ADDR   (0x4000A040u)
#define	MAC_RX_INT_MASK_RESET   (0x00000000u)
#define	MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK   (0x00008000u)
#define	MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK_MASK   (0x00008000u)
#define	MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK_BIT   (15)
#define	MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK_BITS   (1)
#define	MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK   (0x00004000u)
#define	MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK_MASK   (0x00004000u)
#define	MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK_BIT   (14)
#define	MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK_BITS   (1)
#define	MAC_RX_INT_MASK_RX_OVFLW_MSK   (0x00002000u)
#define	MAC_RX_INT_MASK_RX_OVFLW_MSK_MASK   (0x00002000u)
#define	MAC_RX_INT_MASK_RX_OVFLW_MSK_BIT   (13)
#define	MAC_RX_INT_MASK_RX_OVFLW_MSK_BITS   (1)
#define	MAC_RX_INT_MASK_RX_ERROR_MSK   (0x00001000u)
#define	MAC_RX_INT_MASK_RX_ERROR_MSK_MASK   (0x00001000u)
#define	MAC_RX_INT_MASK_RX_ERROR_MSK_BIT   (12)
#define	MAC_RX_INT_MASK_RX_ERROR_MSK_BITS   (1)
#define	MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK   (0x00000800u)
#define	MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK_MASK   (0x00000800u)
#define	MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK_BIT   (11)
#define	MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK_BITS   (1)
#define	MAC_RX_INT_MASK_TX_COLL_RX_MSK   (0x00000400u)
#define	MAC_RX_INT_MASK_TX_COLL_RX_MSK_MASK   (0x00000400u)
#define	MAC_RX_INT_MASK_TX_COLL_RX_MSK_BIT   (10)
#define	MAC_RX_INT_MASK_TX_COLL_RX_MSK_BITS   (1)
#define	MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK   (0x00000200u)
#define	MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK_MASK   (0x00000200u)
#define	MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK_BIT   (9)
#define	MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK_BITS   (1)
#define	MAC_RX_INT_MASK_TX_B_ACK_MSK   (0x00000100u)
#define	MAC_RX_INT_MASK_TX_B_ACK_MSK_MASK   (0x00000100u)
#define	MAC_RX_INT_MASK_TX_B_ACK_MSK_BIT   (8)
#define	MAC_RX_INT_MASK_TX_B_ACK_MSK_BITS   (1)
#define	MAC_RX_INT_MASK_TX_A_ACK_MSK   (0x00000080u)
#define	MAC_RX_INT_MASK_TX_A_ACK_MSK_MASK   (0x00000080u)
#define	MAC_RX_INT_MASK_TX_A_ACK_MSK_BIT   (7)
#define	MAC_RX_INT_MASK_TX_A_ACK_MSK_BITS   (1)
#define	MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK   (0x00000040u)
#define	MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK_MASK   (0x00000040u)
#define	MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK_BIT   (6)
#define	MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK_BITS   (1)
#define	MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK   (0x00000020u)
#define	MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK_MASK   (0x00000020u)
#define	MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK_BIT   (5)
#define	MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK_BITS   (1)
#define	MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK   (0x00000010u)
#define	MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK_MASK   (0x00000010u)
#define	MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK_BIT   (4)
#define	MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK_BITS   (1)
#define	MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK   (0x00000008u)
#define	MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK_MASK   (0x00000008u)
#define	MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK_BIT   (3)
#define	MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK_BITS   (1)
#define	MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK   (0x00000004u)
#define	MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK_MASK   (0x00000004u)
#define	MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK_BIT   (2)
#define	MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK_BITS   (1)
#define	MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK   (0x00000002u)
#define	MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK_MASK   (0x00000002u)
#define	MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK_BIT   (1)
#define	MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK_BITS   (1)
#define	MAC_RX_INT_MASK_RX_FRAME_MSK   (0x00000001u)
#define	MAC_RX_INT_MASK_RX_FRAME_MSK_MASK   (0x00000001u)
#define	MAC_RX_INT_MASK_RX_FRAME_MSK_BIT   (0)
#define	MAC_RX_INT_MASK_RX_FRAME_MSK_BITS   (1)
#define	MAC_TX_INT_MASK   *((volatile int32u *)0x4000A044u)
#define	MAC_TX_INT_MASK_REG   *((volatile int32u *)0x4000A044u)
#define	MAC_TX_INT_MASK_ADDR   (0x4000A044u)
#define	MAC_TX_INT_MASK_RESET   (0x00000000u)
#define	MAC_TX_INT_MASK_RX_B_ACK_MSK   (0x00000800u)
#define	MAC_TX_INT_MASK_RX_B_ACK_MSK_MASK   (0x00000800u)
#define	MAC_TX_INT_MASK_RX_B_ACK_MSK_BIT   (11)
#define	MAC_TX_INT_MASK_RX_B_ACK_MSK_BITS   (1)
#define	MAC_TX_INT_MASK_RX_A_ACK_MSK   (0x00000400u)
#define	MAC_TX_INT_MASK_RX_A_ACK_MSK_MASK   (0x00000400u)
#define	MAC_TX_INT_MASK_RX_A_ACK_MSK_BIT   (10)
#define	MAC_TX_INT_MASK_RX_A_ACK_MSK_BITS   (1)
#define	MAC_TX_INT_MASK_TX_B_UNLOAD_MSK   (0x00000200u)
#define	MAC_TX_INT_MASK_TX_B_UNLOAD_MSK_MASK   (0x00000200u)
#define	MAC_TX_INT_MASK_TX_B_UNLOAD_MSK_BIT   (9)
#define	MAC_TX_INT_MASK_TX_B_UNLOAD_MSK_BITS   (1)
#define	MAC_TX_INT_MASK_TX_A_UNLOAD_MSK   (0x00000100u)
#define	MAC_TX_INT_MASK_TX_A_UNLOAD_MSK_MASK   (0x00000100u)
#define	MAC_TX_INT_MASK_TX_A_UNLOAD_MSK_BIT   (8)
#define	MAC_TX_INT_MASK_TX_A_UNLOAD_MSK_BITS   (1)
#define	MAC_TX_INT_MASK_ACK_EXPIRED_MSK   (0x00000080u)
#define	MAC_TX_INT_MASK_ACK_EXPIRED_MSK_MASK   (0x00000080u)
#define	MAC_TX_INT_MASK_ACK_EXPIRED_MSK_BIT   (7)
#define	MAC_TX_INT_MASK_ACK_EXPIRED_MSK_BITS   (1)
#define	MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK   (0x00000040u)
#define	MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK_MASK   (0x00000040u)
#define	MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK_BIT   (6)
#define	MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK_BITS   (1)
#define	MAC_TX_INT_MASK_TX_UNDERFLOW_MSK   (0x00000020u)
#define	MAC_TX_INT_MASK_TX_UNDERFLOW_MSK_MASK   (0x00000020u)
#define	MAC_TX_INT_MASK_TX_UNDERFLOW_MSK_BIT   (5)
#define	MAC_TX_INT_MASK_TX_UNDERFLOW_MSK_BITS   (1)
#define	MAC_TX_INT_MASK_CCA_FAIL_MSK   (0x00000010u)
#define	MAC_TX_INT_MASK_CCA_FAIL_MSK_MASK   (0x00000010u)
#define	MAC_TX_INT_MASK_CCA_FAIL_MSK_BIT   (4)
#define	MAC_TX_INT_MASK_CCA_FAIL_MSK_BITS   (1)
#define	MAC_TX_INT_MASK_SFD_SENT_MSK   (0x00000008u)
#define	MAC_TX_INT_MASK_SFD_SENT_MSK_MASK   (0x00000008u)
#define	MAC_TX_INT_MASK_SFD_SENT_MSK_BIT   (3)
#define	MAC_TX_INT_MASK_SFD_SENT_MSK_BITS   (1)
#define	MAC_TX_INT_MASK_BO_COMPLETE_MSK   (0x00000004u)
#define	MAC_TX_INT_MASK_BO_COMPLETE_MSK_MASK   (0x00000004u)
#define	MAC_TX_INT_MASK_BO_COMPLETE_MSK_BIT   (2)
#define	MAC_TX_INT_MASK_BO_COMPLETE_MSK_BITS   (1)
#define	MAC_TX_INT_MASK_RX_ACK_MSK   (0x00000002u)
#define	MAC_TX_INT_MASK_RX_ACK_MSK_MASK   (0x00000002u)
#define	MAC_TX_INT_MASK_RX_ACK_MSK_BIT   (1)
#define	MAC_TX_INT_MASK_RX_ACK_MSK_BITS   (1)
#define	MAC_TX_INT_MASK_TX_COMPLETE_MSK   (0x00000001u)
#define	MAC_TX_INT_MASK_TX_COMPLETE_MSK_MASK   (0x00000001u)
#define	MAC_TX_INT_MASK_TX_COMPLETE_MSK_BIT   (0)
#define	MAC_TX_INT_MASK_TX_COMPLETE_MSK_BITS   (1)
#define	MAC_TIMER_INT_MASK   *((volatile int32u *)0x4000A048u)
#define	MAC_TIMER_INT_MASK_REG   *((volatile int32u *)0x4000A048u)
#define	MAC_TIMER_INT_MASK_ADDR   (0x4000A048u)
#define	MAC_TIMER_INT_MASK_RESET   (0x00000000u)
#define	MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK   (0x00000004u)
#define	MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK_MASK   (0x00000004u)
#define	MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK_BIT   (2)
#define	MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK_BITS   (1)
#define	MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK   (0x00000002u)
#define	MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK_MASK   (0x00000002u)
#define	MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK_BIT   (1)
#define	MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK_BITS   (1)
#define	MAC_TIMER_INT_MASK_TIMER_WRAP_MSK   (0x00000001u)
#define	MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_MASK   (0x00000001u)
#define	MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_BIT   (0)
#define	MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_BITS   (1)
#define	BB_INT_MASK   *((volatile int32u *)0x4000A04Cu)
#define	BB_INT_MASK_REG   *((volatile int32u *)0x4000A04Cu)
#define	BB_INT_MASK_ADDR   (0x4000A04Cu)
#define	BB_INT_MASK_RESET   (0x00000000u)
#define	BB_INT_MASK_RSSI_INT_MSK   (0x00000002u)
#define	BB_INT_MASK_RSSI_INT_MSK_MASK   (0x00000002u)
#define	BB_INT_MASK_RSSI_INT_MSK_BIT   (1)
#define	BB_INT_MASK_RSSI_INT_MSK_BITS   (1)
#define	BB_INT_MASK_BASEBAND_INT_MSK   (0x00000001u)
#define	BB_INT_MASK_BASEBAND_INT_MSK_MASK   (0x00000001u)
#define	BB_INT_MASK_BASEBAND_INT_MSK_BIT   (0)
#define	BB_INT_MASK_BASEBAND_INT_MSK_BITS   (1)
#define	SEC_INT_MASK   *((volatile int32u *)0x4000A050u)
#define	SEC_INT_MASK_REG   *((volatile int32u *)0x4000A050u)
#define	SEC_INT_MASK_ADDR   (0x4000A050u)
#define	SEC_INT_MASK_RESET   (0x00000000u)
#define	SEC_INT_MASK_CT_WORD_VALID_MSK   (0x00000004u)
#define	SEC_INT_MASK_CT_WORD_VALID_MSK_MASK   (0x00000004u)
#define	SEC_INT_MASK_CT_WORD_VALID_MSK_BIT   (2)
#define	SEC_INT_MASK_CT_WORD_VALID_MSK_BITS   (1)
#define	SEC_INT_MASK_PT_WORD_REQ_MSK   (0x00000002u)
#define	SEC_INT_MASK_PT_WORD_REQ_MSK_MASK   (0x00000002u)
#define	SEC_INT_MASK_PT_WORD_REQ_MSK_BIT   (1)
#define	SEC_INT_MASK_PT_WORD_REQ_MSK_BITS   (1)
#define	SEC_INT_MASK_ENC_COMPLETE_MSK   (0x00000001u)
#define	SEC_INT_MASK_ENC_COMPLETE_MSK_MASK   (0x00000001u)
#define	SEC_INT_MASK_ENC_COMPLETE_MSK_BIT   (0)
#define	SEC_INT_MASK_ENC_COMPLETE_MSK_BITS   (1)
#define	INT_SLEEPTMRCFG   *((volatile int32u *)0x4000A054u)
#define	INT_SLEEPTMRCFG_REG   *((volatile int32u *)0x4000A054u)
#define	INT_SLEEPTMRCFG_ADDR   (0x4000A054u)
#define	INT_SLEEPTMRCFG_RESET   (0x00000000u)
#define	INT_SLEEPTMRCMPB   (0x00000004u)
#define	INT_SLEEPTMRCMPB_MASK   (0x00000004u)
#define	INT_SLEEPTMRCMPB_BIT   (2)
#define	INT_SLEEPTMRCMPB_BITS   (1)
#define	INT_SLEEPTMRCMPA   (0x00000002u)
#define	INT_SLEEPTMRCMPA_MASK   (0x00000002u)
#define	INT_SLEEPTMRCMPA_BIT   (1)
#define	INT_SLEEPTMRCMPA_BITS   (1)
#define	INT_SLEEPTMRWRAP   (0x00000001u)
#define	INT_SLEEPTMRWRAP_MASK   (0x00000001u)
#define	INT_SLEEPTMRWRAP_BIT   (0)
#define	INT_SLEEPTMRWRAP_BITS   (1)
#define	INT_MGMTCFG   *((volatile int32u *)0x4000A058u)
#define	INT_MGMTCFG_REG   *((volatile int32u *)0x4000A058u)
#define	INT_MGMTCFG_ADDR   (0x4000A058u)
#define	INT_MGMTCFG_RESET   (0x00000000u)
#define	INT_MGMTDMAPROT   (0x00000010u)
#define	INT_MGMTDMAPROT_MASK   (0x00000010u)
#define	INT_MGMTDMAPROT_BIT   (4)
#define	INT_MGMTDMAPROT_BITS   (1)
#define	INT_MGMTCALADC   (0x00000008u)
#define	INT_MGMTCALADC_MASK   (0x00000008u)
#define	INT_MGMTCALADC_BIT   (3)
#define	INT_MGMTCALADC_BITS   (1)
#define	INT_MGMTFPEC   (0x00000004u)
#define	INT_MGMTFPEC_MASK   (0x00000004u)
#define	INT_MGMTFPEC_BIT   (2)
#define	INT_MGMTFPEC_BITS   (1)
#define	INT_MGMTOSC24MHI   (0x00000002u)
#define	INT_MGMTOSC24MHI_MASK   (0x00000002u)
#define	INT_MGMTOSC24MHI_BIT   (1)
#define	INT_MGMTOSC24MHI_BITS   (1)
#define	INT_MGMTOSC24MLO   (0x00000001u)
#define	INT_MGMTOSC24MLO_MASK   (0x00000001u)
#define	INT_MGMTOSC24MLO_BIT   (0)
#define	INT_MGMTOSC24MLO_BITS   (1)
#define	INT_TIM1FLAG   *((volatile int32u *)0x4000A800u)
#define	INT_TIM1FLAG_REG   *((volatile int32u *)0x4000A800u)
#define	INT_TIM1FLAG_ADDR   (0x4000A800u)
#define	INT_TIM1FLAG_RESET   (0x00000000u)
#define	INT_TIMRSVD   (0x00001E00u)
#define	INT_TIMRSVD_MASK   (0x00001E00u)
#define	INT_TIMRSVD_BIT   (9)
#define	INT_TIMRSVD_BITS   (4)
#define	INT_TIMTIF   (0x00000040u)
#define	INT_TIMTIF_MASK   (0x00000040u)
#define	INT_TIMTIF_BIT   (6)
#define	INT_TIMTIF_BITS   (1)
#define	INT_TIMCC4IF   (0x00000010u)
#define	INT_TIMCC4IF_MASK   (0x00000010u)
#define	INT_TIMCC4IF_BIT   (4)
#define	INT_TIMCC4IF_BITS   (1)
#define	INT_TIMCC3IF   (0x00000008u)
#define	INT_TIMCC3IF_MASK   (0x00000008u)
#define	INT_TIMCC3IF_BIT   (3)
#define	INT_TIMCC3IF_BITS   (1)
#define	INT_TIMCC2IF   (0x00000004u)
#define	INT_TIMCC2IF_MASK   (0x00000004u)
#define	INT_TIMCC2IF_BIT   (2)
#define	INT_TIMCC2IF_BITS   (1)
#define	INT_TIMCC1IF   (0x00000002u)
#define	INT_TIMCC1IF_MASK   (0x00000002u)
#define	INT_TIMCC1IF_BIT   (1)
#define	INT_TIMCC1IF_BITS   (1)
#define	INT_TIMUIF   (0x00000001u)
#define	INT_TIMUIF_MASK   (0x00000001u)
#define	INT_TIMUIF_BIT   (0)
#define	INT_TIMUIF_BITS   (1)
#define	INT_TIM2FLAG   *((volatile int32u *)0x4000A804u)
#define	INT_TIM2FLAG_REG   *((volatile int32u *)0x4000A804u)
#define	INT_TIM2FLAG_ADDR   (0x4000A804u)
#define	INT_TIM2FLAG_RESET   (0x00000000u)
#define	INT_TIMRSVD   (0x00001E00u)
#define	INT_TIMRSVD_MASK   (0x00001E00u)
#define	INT_TIMRSVD_BIT   (9)
#define	INT_TIMRSVD_BITS   (4)
#define	INT_TIMTIF   (0x00000040u)
#define	INT_TIMTIF_MASK   (0x00000040u)
#define	INT_TIMTIF_BIT   (6)
#define	INT_TIMTIF_BITS   (1)
#define	INT_TIMCC4IF   (0x00000010u)
#define	INT_TIMCC4IF_MASK   (0x00000010u)
#define	INT_TIMCC4IF_BIT   (4)
#define	INT_TIMCC4IF_BITS   (1)
#define	INT_TIMCC3IF   (0x00000008u)
#define	INT_TIMCC3IF_MASK   (0x00000008u)
#define	INT_TIMCC3IF_BIT   (3)
#define	INT_TIMCC3IF_BITS   (1)
#define	INT_TIMCC2IF   (0x00000004u)
#define	INT_TIMCC2IF_MASK   (0x00000004u)
#define	INT_TIMCC2IF_BIT   (2)
#define	INT_TIMCC2IF_BITS   (1)
#define	INT_TIMCC1IF   (0x00000002u)
#define	INT_TIMCC1IF_MASK   (0x00000002u)
#define	INT_TIMCC1IF_BIT   (1)
#define	INT_TIMCC1IF_BITS   (1)
#define	INT_TIMUIF   (0x00000001u)
#define	INT_TIMUIF_MASK   (0x00000001u)
#define	INT_TIMUIF_BIT   (0)
#define	INT_TIMUIF_BITS   (1)
#define	INT_SC1FLAG   *((volatile int32u *)0x4000A808u)
#define	INT_SC1FLAG_REG   *((volatile int32u *)0x4000A808u)
#define	INT_SC1FLAG_ADDR   (0x4000A808u)
#define	INT_SC1FLAG_RESET   (0x00000000u)
#define	INT_SC1PARERR   (0x00004000u)
#define	INT_SC1PARERR_MASK   (0x00004000u)
#define	INT_SC1PARERR_BIT   (14)
#define	INT_SC1PARERR_BITS   (1)
#define	INT_SC1FRMERR   (0x00002000u)
#define	INT_SC1FRMERR_MASK   (0x00002000u)
#define	INT_SC1FRMERR_BIT   (13)
#define	INT_SC1FRMERR_BITS   (1)
#define	INT_SCTXULDB   (0x00001000u)
#define	INT_SCTXULDB_MASK   (0x00001000u)
#define	INT_SCTXULDB_BIT   (12)
#define	INT_SCTXULDB_BITS   (1)
#define	INT_SCTXULDA   (0x00000800u)
#define	INT_SCTXULDA_MASK   (0x00000800u)
#define	INT_SCTXULDA_BIT   (11)
#define	INT_SCTXULDA_BITS   (1)
#define	INT_SCRXULDB   (0x00000400u)
#define	INT_SCRXULDB_MASK   (0x00000400u)
#define	INT_SCRXULDB_BIT   (10)
#define	INT_SCRXULDB_BITS   (1)
#define	INT_SCRXULDA   (0x00000200u)
#define	INT_SCRXULDA_MASK   (0x00000200u)
#define	INT_SCRXULDA_BIT   (9)
#define	INT_SCRXULDA_BITS   (1)
#define	INT_SCNAK   (0x00000100u)
#define	INT_SCNAK_MASK   (0x00000100u)
#define	INT_SCNAK_BIT   (8)
#define	INT_SCNAK_BITS   (1)
#define	INT_SCCMDFIN   (0x00000080u)
#define	INT_SCCMDFIN_MASK   (0x00000080u)
#define	INT_SCCMDFIN_BIT   (7)
#define	INT_SCCMDFIN_BITS   (1)
#define	INT_SCTXFIN   (0x00000040u)
#define	INT_SCTXFIN_MASK   (0x00000040u)
#define	INT_SCTXFIN_BIT   (6)
#define	INT_SCTXFIN_BITS   (1)
#define	INT_SCRXFIN   (0x00000020u)
#define	INT_SCRXFIN_MASK   (0x00000020u)
#define	INT_SCRXFIN_BIT   (5)
#define	INT_SCRXFIN_BITS   (1)
#define	INT_SCTXUND   (0x00000010u)
#define	INT_SCTXUND_MASK   (0x00000010u)
#define	INT_SCTXUND_BIT   (4)
#define	INT_SCTXUND_BITS   (1)
#define	INT_SCRXOVF   (0x00000008u)
#define	INT_SCRXOVF_MASK   (0x00000008u)
#define	INT_SCRXOVF_BIT   (3)
#define	INT_SCRXOVF_BITS   (1)
#define	INT_SCTXIDLE   (0x00000004u)
#define	INT_SCTXIDLE_MASK   (0x00000004u)
#define	INT_SCTXIDLE_BIT   (2)
#define	INT_SCTXIDLE_BITS   (1)
#define	INT_SCTXFREE   (0x00000002u)
#define	INT_SCTXFREE_MASK   (0x00000002u)
#define	INT_SCTXFREE_BIT   (1)
#define	INT_SCTXFREE_BITS   (1)
#define	INT_SCRXVAL   (0x00000001u)
#define	INT_SCRXVAL_MASK   (0x00000001u)
#define	INT_SCRXVAL_BIT   (0)
#define	INT_SCRXVAL_BITS   (1)
#define	INT_SC2FLAG   *((volatile int32u *)0x4000A80Cu)
#define	INT_SC2FLAG_REG   *((volatile int32u *)0x4000A80Cu)
#define	INT_SC2FLAG_ADDR   (0x4000A80Cu)
#define	INT_SC2FLAG_RESET   (0x00000000u)
#define	INT_SCTXULDB   (0x00001000u)
#define	INT_SCTXULDB_MASK   (0x00001000u)
#define	INT_SCTXULDB_BIT   (12)
#define	INT_SCTXULDB_BITS   (1)
#define	INT_SCTXULDA   (0x00000800u)
#define	INT_SCTXULDA_MASK   (0x00000800u)
#define	INT_SCTXULDA_BIT   (11)
#define	INT_SCTXULDA_BITS   (1)
#define	INT_SCRXULDB   (0x00000400u)
#define	INT_SCRXULDB_MASK   (0x00000400u)
#define	INT_SCRXULDB_BIT   (10)
#define	INT_SCRXULDB_BITS   (1)
#define	INT_SCRXULDA   (0x00000200u)
#define	INT_SCRXULDA_MASK   (0x00000200u)
#define	INT_SCRXULDA_BIT   (9)
#define	INT_SCRXULDA_BITS   (1)
#define	INT_SCNAK   (0x00000100u)
#define	INT_SCNAK_MASK   (0x00000100u)
#define	INT_SCNAK_BIT   (8)
#define	INT_SCNAK_BITS   (1)
#define	INT_SCCMDFIN   (0x00000080u)
#define	INT_SCCMDFIN_MASK   (0x00000080u)
#define	INT_SCCMDFIN_BIT   (7)
#define	INT_SCCMDFIN_BITS   (1)
#define	INT_SCTXFIN   (0x00000040u)
#define	INT_SCTXFIN_MASK   (0x00000040u)
#define	INT_SCTXFIN_BIT   (6)
#define	INT_SCTXFIN_BITS   (1)
#define	INT_SCRXFIN   (0x00000020u)
#define	INT_SCRXFIN_MASK   (0x00000020u)
#define	INT_SCRXFIN_BIT   (5)
#define	INT_SCRXFIN_BITS   (1)
#define	INT_SCTXUND   (0x00000010u)
#define	INT_SCTXUND_MASK   (0x00000010u)
#define	INT_SCTXUND_BIT   (4)
#define	INT_SCTXUND_BITS   (1)
#define	INT_SCRXOVF   (0x00000008u)
#define	INT_SCRXOVF_MASK   (0x00000008u)
#define	INT_SCRXOVF_BIT   (3)
#define	INT_SCRXOVF_BITS   (1)
#define	INT_SCTXIDLE   (0x00000004u)
#define	INT_SCTXIDLE_MASK   (0x00000004u)
#define	INT_SCTXIDLE_BIT   (2)
#define	INT_SCTXIDLE_BITS   (1)
#define	INT_SCTXFREE   (0x00000002u)
#define	INT_SCTXFREE_MASK   (0x00000002u)
#define	INT_SCTXFREE_BIT   (1)
#define	INT_SCTXFREE_BITS   (1)
#define	INT_SCRXVAL   (0x00000001u)
#define	INT_SCRXVAL_MASK   (0x00000001u)
#define	INT_SCRXVAL_BIT   (0)
#define	INT_SCRXVAL_BITS   (1)
#define	INT_ADCFLAG   *((volatile int32u *)0x4000A810u)
#define	INT_ADCFLAG_REG   *((volatile int32u *)0x4000A810u)
#define	INT_ADCFLAG_ADDR   (0x4000A810u)
#define	INT_ADCFLAG_RESET   (0x00000000u)
#define	INT_ADCOVF   (0x00000010u)
#define	INT_ADCOVF_MASK   (0x00000010u)
#define	INT_ADCOVF_BIT   (4)
#define	INT_ADCOVF_BITS   (1)
#define	INT_ADCSAT   (0x00000008u)
#define	INT_ADCSAT_MASK   (0x00000008u)
#define	INT_ADCSAT_BIT   (3)
#define	INT_ADCSAT_BITS   (1)
#define	INT_ADCULDFULL   (0x00000004u)
#define	INT_ADCULDFULL_MASK   (0x00000004u)
#define	INT_ADCULDFULL_BIT   (2)
#define	INT_ADCULDFULL_BITS   (1)
#define	INT_ADCULDHALF   (0x00000002u)
#define	INT_ADCULDHALF_MASK   (0x00000002u)
#define	INT_ADCULDHALF_BIT   (1)
#define	INT_ADCULDHALF_BITS   (1)
#define	INT_ADCFLAGRSVD   (0x00000001u)
#define	INT_ADCFLAGRSVD_MASK   (0x00000001u)
#define	INT_ADCFLAGRSVD_BIT   (0)
#define	INT_ADCFLAGRSVD_BITS   (1)
#define	INT_GPIOFLAG   *((volatile int32u *)0x4000A814u)
#define	INT_GPIOFLAG_REG   *((volatile int32u *)0x4000A814u)
#define	INT_GPIOFLAG_ADDR   (0x4000A814u)
#define	INT_GPIOFLAG_RESET   (0x00000000u)
#define	INT_IRQDFLAG   (0x00000008u)
#define	INT_IRQDFLAG_MASK   (0x00000008u)
#define	INT_IRQDFLAG_BIT   (3)
#define	INT_IRQDFLAG_BITS   (1)
#define	INT_IRQCFLAG   (0x00000004u)
#define	INT_IRQCFLAG_MASK   (0x00000004u)
#define	INT_IRQCFLAG_BIT   (2)
#define	INT_IRQCFLAG_BITS   (1)
#define	INT_IRQBFLAG   (0x00000002u)
#define	INT_IRQBFLAG_MASK   (0x00000002u)
#define	INT_IRQBFLAG_BIT   (1)
#define	INT_IRQBFLAG_BITS   (1)
#define	INT_IRQAFLAG   (0x00000001u)
#define	INT_IRQAFLAG_MASK   (0x00000001u)
#define	INT_IRQAFLAG_BIT   (0)
#define	INT_IRQAFLAG_BITS   (1)
#define	INT_TIM1MISS   *((volatile int32u *)0x4000A818u)
#define	INT_TIM1MISS_REG   *((volatile int32u *)0x4000A818u)
#define	INT_TIM1MISS_ADDR   (0x4000A818u)
#define	INT_TIM1MISS_RESET   (0x00000000u)
#define	INT_TIMMISSCC4IF   (0x00001000u)
#define	INT_TIMMISSCC4IF_MASK   (0x00001000u)
#define	INT_TIMMISSCC4IF_BIT   (12)
#define	INT_TIMMISSCC4IF_BITS   (1)
#define	INT_TIMMISSCC3IF   (0x00000800u)
#define	INT_TIMMISSCC3IF_MASK   (0x00000800u)
#define	INT_TIMMISSCC3IF_BIT   (11)
#define	INT_TIMMISSCC3IF_BITS   (1)
#define	INT_TIMMISSCC2IF   (0x00000400u)
#define	INT_TIMMISSCC2IF_MASK   (0x00000400u)
#define	INT_TIMMISSCC2IF_BIT   (10)
#define	INT_TIMMISSCC2IF_BITS   (1)
#define	INT_TIMMISSCC1IF   (0x00000200u)
#define	INT_TIMMISSCC1IF_MASK   (0x00000200u)
#define	INT_TIMMISSCC1IF_BIT   (9)
#define	INT_TIMMISSCC1IF_BITS   (1)
#define	INT_TIMMISSRSVD   (0x0000007Fu)
#define	INT_TIMMISSRSVD_MASK   (0x0000007Fu)
#define	INT_TIMMISSRSVD_BIT   (0)
#define	INT_TIMMISSRSVD_BITS   (7)
#define	INT_TIM2MISS   *((volatile int32u *)0x4000A81Cu)
#define	INT_TIM2MISS_REG   *((volatile int32u *)0x4000A81Cu)
#define	INT_TIM2MISS_ADDR   (0x4000A81Cu)
#define	INT_TIM2MISS_RESET   (0x00000000u)
#define	INT_TIMMISSCC4IF   (0x00001000u)
#define	INT_TIMMISSCC4IF_MASK   (0x00001000u)
#define	INT_TIMMISSCC4IF_BIT   (12)
#define	INT_TIMMISSCC4IF_BITS   (1)
#define	INT_TIMMISSCC3IF   (0x00000800u)
#define	INT_TIMMISSCC3IF_MASK   (0x00000800u)
#define	INT_TIMMISSCC3IF_BIT   (11)
#define	INT_TIMMISSCC3IF_BITS   (1)
#define	INT_TIMMISSCC2IF   (0x00000400u)
#define	INT_TIMMISSCC2IF_MASK   (0x00000400u)
#define	INT_TIMMISSCC2IF_BIT   (10)
#define	INT_TIMMISSCC2IF_BITS   (1)
#define	INT_TIMMISSCC1IF   (0x00000200u)
#define	INT_TIMMISSCC1IF_MASK   (0x00000200u)
#define	INT_TIMMISSCC1IF_BIT   (9)
#define	INT_TIMMISSCC1IF_BITS   (1)
#define	INT_TIMMISSRSVD   (0x0000007Fu)
#define	INT_TIMMISSRSVD_MASK   (0x0000007Fu)
#define	INT_TIMMISSRSVD_BIT   (0)
#define	INT_TIMMISSRSVD_BITS   (7)
#define	INT_MISS   *((volatile int32u *)0x4000A820u)
#define	INT_MISS_REG   *((volatile int32u *)0x4000A820u)
#define	INT_MISS_ADDR   (0x4000A820u)
#define	INT_MISS_RESET   (0x00000000u)
#define	INT_MISSIRQD   (0x00008000u)
#define	INT_MISSIRQD_MASK   (0x00008000u)
#define	INT_MISSIRQD_BIT   (15)
#define	INT_MISSIRQD_BITS   (1)
#define	INT_MISSIRQC   (0x00004000u)
#define	INT_MISSIRQC_MASK   (0x00004000u)
#define	INT_MISSIRQC_BIT   (14)
#define	INT_MISSIRQC_BITS   (1)
#define	INT_MISSIRQB   (0x00002000u)
#define	INT_MISSIRQB_MASK   (0x00002000u)
#define	INT_MISSIRQB_BIT   (13)
#define	INT_MISSIRQB_BITS   (1)
#define	INT_MISSIRQA   (0x00001000u)
#define	INT_MISSIRQA_MASK   (0x00001000u)
#define	INT_MISSIRQA_BIT   (12)
#define	INT_MISSIRQA_BITS   (1)
#define	INT_MISSADC   (0x00000800u)
#define	INT_MISSADC_MASK   (0x00000800u)
#define	INT_MISSADC_BIT   (11)
#define	INT_MISSADC_BITS   (1)
#define	INT_MISSMACRX   (0x00000400u)
#define	INT_MISSMACRX_MASK   (0x00000400u)
#define	INT_MISSMACRX_BIT   (10)
#define	INT_MISSMACRX_BITS   (1)
#define	INT_MISSMACTX   (0x00000200u)
#define	INT_MISSMACTX_MASK   (0x00000200u)
#define	INT_MISSMACTX_BIT   (9)
#define	INT_MISSMACTX_BITS   (1)
#define	INT_MISSMACTMR   (0x00000100u)
#define	INT_MISSMACTMR_MASK   (0x00000100u)
#define	INT_MISSMACTMR_BIT   (8)
#define	INT_MISSMACTMR_BITS   (1)
#define	INT_MISSSEC   (0x00000080u)
#define	INT_MISSSEC_MASK   (0x00000080u)
#define	INT_MISSSEC_BIT   (7)
#define	INT_MISSSEC_BITS   (1)
#define	INT_MISSSC2   (0x00000040u)
#define	INT_MISSSC2_MASK   (0x00000040u)
#define	INT_MISSSC2_BIT   (6)
#define	INT_MISSSC2_BITS   (1)
#define	INT_MISSSC1   (0x00000020u)
#define	INT_MISSSC1_MASK   (0x00000020u)
#define	INT_MISSSC1_BIT   (5)
#define	INT_MISSSC1_BITS   (1)
#define	INT_MISSSLEEP   (0x00000010u)
#define	INT_MISSSLEEP_MASK   (0x00000010u)
#define	INT_MISSSLEEP_BIT   (4)
#define	INT_MISSSLEEP_BITS   (1)
#define	INT_MISSBB   (0x00000008u)
#define	INT_MISSBB_MASK   (0x00000008u)
#define	INT_MISSBB_BIT   (3)
#define	INT_MISSBB_BITS   (1)
#define	INT_MISSMGMT   (0x00000004u)
#define	INT_MISSMGMT_MASK   (0x00000004u)
#define	INT_MISSMGMT_BIT   (2)
#define	INT_MISSMGMT_BITS   (1)
#define	INT_TIM1CFG   *((volatile int32u *)0x4000A840u)
#define	INT_TIM1CFG_REG   *((volatile int32u *)0x4000A840u)
#define	INT_TIM1CFG_ADDR   (0x4000A840u)
#define	INT_TIM1CFG_RESET   (0x00000000u)
#define	INT_TIMTIF   (0x00000040u)
#define	INT_TIMTIF_MASK   (0x00000040u)
#define	INT_TIMTIF_BIT   (6)
#define	INT_TIMTIF_BITS   (1)
#define	INT_TIMCC4IF   (0x00000010u)
#define	INT_TIMCC4IF_MASK   (0x00000010u)
#define	INT_TIMCC4IF_BIT   (4)
#define	INT_TIMCC4IF_BITS   (1)
#define	INT_TIMCC3IF   (0x00000008u)
#define	INT_TIMCC3IF_MASK   (0x00000008u)
#define	INT_TIMCC3IF_BIT   (3)
#define	INT_TIMCC3IF_BITS   (1)
#define	INT_TIMCC2IF   (0x00000004u)
#define	INT_TIMCC2IF_MASK   (0x00000004u)
#define	INT_TIMCC2IF_BIT   (2)
#define	INT_TIMCC2IF_BITS   (1)
#define	INT_TIMCC1IF   (0x00000002u)
#define	INT_TIMCC1IF_MASK   (0x00000002u)
#define	INT_TIMCC1IF_BIT   (1)
#define	INT_TIMCC1IF_BITS   (1)
#define	INT_TIMUIF   (0x00000001u)
#define	INT_TIMUIF_MASK   (0x00000001u)
#define	INT_TIMUIF_BIT   (0)
#define	INT_TIMUIF_BITS   (1)
#define	INT_TIM2CFG   *((volatile int32u *)0x4000A844u)
#define	INT_TIM2CFG_REG   *((volatile int32u *)0x4000A844u)
#define	INT_TIM2CFG_ADDR   (0x4000A844u)
#define	INT_TIM2CFG_RESET   (0x00000000u)
#define	INT_TIMTIF   (0x00000040u)
#define	INT_TIMTIF_MASK   (0x00000040u)
#define	INT_TIMTIF_BIT   (6)
#define	INT_TIMTIF_BITS   (1)
#define	INT_TIMCC4IF   (0x00000010u)
#define	INT_TIMCC4IF_MASK   (0x00000010u)
#define	INT_TIMCC4IF_BIT   (4)
#define	INT_TIMCC4IF_BITS   (1)
#define	INT_TIMCC3IF   (0x00000008u)
#define	INT_TIMCC3IF_MASK   (0x00000008u)
#define	INT_TIMCC3IF_BIT   (3)
#define	INT_TIMCC3IF_BITS   (1)
#define	INT_TIMCC2IF   (0x00000004u)
#define	INT_TIMCC2IF_MASK   (0x00000004u)
#define	INT_TIMCC2IF_BIT   (2)
#define	INT_TIMCC2IF_BITS   (1)
#define	INT_TIMCC1IF   (0x00000002u)
#define	INT_TIMCC1IF_MASK   (0x00000002u)
#define	INT_TIMCC1IF_BIT   (1)
#define	INT_TIMCC1IF_BITS   (1)
#define	INT_TIMUIF   (0x00000001u)
#define	INT_TIMUIF_MASK   (0x00000001u)
#define	INT_TIMUIF_BIT   (0)
#define	INT_TIMUIF_BITS   (1)
#define	INT_SC1CFG   *((volatile int32u *)0x4000A848u)
#define	INT_SC1CFG_REG   *((volatile int32u *)0x4000A848u)
#define	INT_SC1CFG_ADDR   (0x4000A848u)
#define	INT_SC1CFG_RESET   (0x00000000u)
#define	INT_SC1PARERR   (0x00004000u)
#define	INT_SC1PARERR_MASK   (0x00004000u)
#define	INT_SC1PARERR_BIT   (14)
#define	INT_SC1PARERR_BITS   (1)
#define	INT_SC1FRMERR   (0x00002000u)
#define	INT_SC1FRMERR_MASK   (0x00002000u)
#define	INT_SC1FRMERR_BIT   (13)
#define	INT_SC1FRMERR_BITS   (1)
#define	INT_SCTXULDB   (0x00001000u)
#define	INT_SCTXULDB_MASK   (0x00001000u)
#define	INT_SCTXULDB_BIT   (12)
#define	INT_SCTXULDB_BITS   (1)
#define	INT_SCTXULDA   (0x00000800u)
#define	INT_SCTXULDA_MASK   (0x00000800u)
#define	INT_SCTXULDA_BIT   (11)
#define	INT_SCTXULDA_BITS   (1)
#define	INT_SCRXULDB   (0x00000400u)
#define	INT_SCRXULDB_MASK   (0x00000400u)
#define	INT_SCRXULDB_BIT   (10)
#define	INT_SCRXULDB_BITS   (1)
#define	INT_SCRXULDA   (0x00000200u)
#define	INT_SCRXULDA_MASK   (0x00000200u)
#define	INT_SCRXULDA_BIT   (9)
#define	INT_SCRXULDA_BITS   (1)
#define	INT_SCNAK   (0x00000100u)
#define	INT_SCNAK_MASK   (0x00000100u)
#define	INT_SCNAK_BIT   (8)
#define	INT_SCNAK_BITS   (1)
#define	INT_SCCMDFIN   (0x00000080u)
#define	INT_SCCMDFIN_MASK   (0x00000080u)
#define	INT_SCCMDFIN_BIT   (7)
#define	INT_SCCMDFIN_BITS   (1)
#define	INT_SCTXFIN   (0x00000040u)
#define	INT_SCTXFIN_MASK   (0x00000040u)
#define	INT_SCTXFIN_BIT   (6)
#define	INT_SCTXFIN_BITS   (1)
#define	INT_SCRXFIN   (0x00000020u)
#define	INT_SCRXFIN_MASK   (0x00000020u)
#define	INT_SCRXFIN_BIT   (5)
#define	INT_SCRXFIN_BITS   (1)
#define	INT_SCTXUND   (0x00000010u)
#define	INT_SCTXUND_MASK   (0x00000010u)
#define	INT_SCTXUND_BIT   (4)
#define	INT_SCTXUND_BITS   (1)
#define	INT_SCRXOVF   (0x00000008u)
#define	INT_SCRXOVF_MASK   (0x00000008u)
#define	INT_SCRXOVF_BIT   (3)
#define	INT_SCRXOVF_BITS   (1)
#define	INT_SCTXIDLE   (0x00000004u)
#define	INT_SCTXIDLE_MASK   (0x00000004u)
#define	INT_SCTXIDLE_BIT   (2)
#define	INT_SCTXIDLE_BITS   (1)
#define	INT_SCTXFREE   (0x00000002u)
#define	INT_SCTXFREE_MASK   (0x00000002u)
#define	INT_SCTXFREE_BIT   (1)
#define	INT_SCTXFREE_BITS   (1)
#define	INT_SCRXVAL   (0x00000001u)
#define	INT_SCRXVAL_MASK   (0x00000001u)
#define	INT_SCRXVAL_BIT   (0)
#define	INT_SCRXVAL_BITS   (1)
#define	INT_SC2CFG   *((volatile int32u *)0x4000A84Cu)
#define	INT_SC2CFG_REG   *((volatile int32u *)0x4000A84Cu)
#define	INT_SC2CFG_ADDR   (0x4000A84Cu)
#define	INT_SC2CFG_RESET   (0x00000000u)
#define	INT_SCTXULDB   (0x00001000u)
#define	INT_SCTXULDB_MASK   (0x00001000u)
#define	INT_SCTXULDB_BIT   (12)
#define	INT_SCTXULDB_BITS   (1)
#define	INT_SCTXULDA   (0x00000800u)
#define	INT_SCTXULDA_MASK   (0x00000800u)
#define	INT_SCTXULDA_BIT   (11)
#define	INT_SCTXULDA_BITS   (1)
#define	INT_SCRXULDB   (0x00000400u)
#define	INT_SCRXULDB_MASK   (0x00000400u)
#define	INT_SCRXULDB_BIT   (10)
#define	INT_SCRXULDB_BITS   (1)
#define	INT_SCRXULDA   (0x00000200u)
#define	INT_SCRXULDA_MASK   (0x00000200u)
#define	INT_SCRXULDA_BIT   (9)
#define	INT_SCRXULDA_BITS   (1)
#define	INT_SCNAK   (0x00000100u)
#define	INT_SCNAK_MASK   (0x00000100u)
#define	INT_SCNAK_BIT   (8)
#define	INT_SCNAK_BITS   (1)
#define	INT_SCCMDFIN   (0x00000080u)
#define	INT_SCCMDFIN_MASK   (0x00000080u)
#define	INT_SCCMDFIN_BIT   (7)
#define	INT_SCCMDFIN_BITS   (1)
#define	INT_SCTXFIN   (0x00000040u)
#define	INT_SCTXFIN_MASK   (0x00000040u)
#define	INT_SCTXFIN_BIT   (6)
#define	INT_SCTXFIN_BITS   (1)
#define	INT_SCRXFIN   (0x00000020u)
#define	INT_SCRXFIN_MASK   (0x00000020u)
#define	INT_SCRXFIN_BIT   (5)
#define	INT_SCRXFIN_BITS   (1)
#define	INT_SCTXUND   (0x00000010u)
#define	INT_SCTXUND_MASK   (0x00000010u)
#define	INT_SCTXUND_BIT   (4)
#define	INT_SCTXUND_BITS   (1)
#define	INT_SCRXOVF   (0x00000008u)
#define	INT_SCRXOVF_MASK   (0x00000008u)
#define	INT_SCRXOVF_BIT   (3)
#define	INT_SCRXOVF_BITS   (1)
#define	INT_SCTXIDLE   (0x00000004u)
#define	INT_SCTXIDLE_MASK   (0x00000004u)
#define	INT_SCTXIDLE_BIT   (2)
#define	INT_SCTXIDLE_BITS   (1)
#define	INT_SCTXFREE   (0x00000002u)
#define	INT_SCTXFREE_MASK   (0x00000002u)
#define	INT_SCTXFREE_BIT   (1)
#define	INT_SCTXFREE_BITS   (1)
#define	INT_SCRXVAL   (0x00000001u)
#define	INT_SCRXVAL_MASK   (0x00000001u)
#define	INT_SCRXVAL_BIT   (0)
#define	INT_SCRXVAL_BITS   (1)
#define	INT_ADCCFG   *((volatile int32u *)0x4000A850u)
#define	INT_ADCCFG_REG   *((volatile int32u *)0x4000A850u)
#define	INT_ADCCFG_ADDR   (0x4000A850u)
#define	INT_ADCCFG_RESET   (0x00000000u)
#define	INT_ADCOVF   (0x00000010u)
#define	INT_ADCOVF_MASK   (0x00000010u)
#define	INT_ADCOVF_BIT   (4)
#define	INT_ADCOVF_BITS   (1)
#define	INT_ADCSAT   (0x00000008u)
#define	INT_ADCSAT_MASK   (0x00000008u)
#define	INT_ADCSAT_BIT   (3)
#define	INT_ADCSAT_BITS   (1)
#define	INT_ADCULDFULL   (0x00000004u)
#define	INT_ADCULDFULL_MASK   (0x00000004u)
#define	INT_ADCULDFULL_BIT   (2)
#define	INT_ADCULDFULL_BITS   (1)
#define	INT_ADCULDHALF   (0x00000002u)
#define	INT_ADCULDHALF_MASK   (0x00000002u)
#define	INT_ADCULDHALF_BIT   (1)
#define	INT_ADCULDHALF_BITS   (1)
#define	INT_ADCCFGRSVD   (0x00000001u)
#define	INT_ADCCFGRSVD_MASK   (0x00000001u)
#define	INT_ADCCFGRSVD_BIT   (0)
#define	INT_ADCCFGRSVD_BITS   (1)
#define	SC1_INTMODE   *((volatile int32u *)0x4000A854u)
#define	SC1_INTMODE_REG   *((volatile int32u *)0x4000A854u)
#define	SC1_INTMODE_ADDR   (0x4000A854u)
#define	SC1_INTMODE_RESET   (0x00000000u)
#define	SC_TXIDLELEVEL   (0x00000004u)
#define	SC_TXIDLELEVEL_MASK   (0x00000004u)
#define	SC_TXIDLELEVEL_BIT   (2)
#define	SC_TXIDLELEVEL_BITS   (1)
#define	SC_TXFREELEVEL   (0x00000002u)
#define	SC_TXFREELEVEL_MASK   (0x00000002u)
#define	SC_TXFREELEVEL_BIT   (1)
#define	SC_TXFREELEVEL_BITS   (1)
#define	SC_RXVALLEVEL   (0x00000001u)
#define	SC_RXVALLEVEL_MASK   (0x00000001u)
#define	SC_RXVALLEVEL_BIT   (0)
#define	SC_RXVALLEVEL_BITS   (1)
#define	SC2_INTMODE   *((volatile int32u *)0x4000A858u)
#define	SC2_INTMODE_REG   *((volatile int32u *)0x4000A858u)
#define	SC2_INTMODE_ADDR   (0x4000A858u)
#define	SC2_INTMODE_RESET   (0x00000000u)
#define	SC_TXIDLELEVEL   (0x00000004u)
#define	SC_TXIDLELEVEL_MASK   (0x00000004u)
#define	SC_TXIDLELEVEL_BIT   (2)
#define	SC_TXIDLELEVEL_BITS   (1)
#define	SC_TXFREELEVEL   (0x00000002u)
#define	SC_TXFREELEVEL_MASK   (0x00000002u)
#define	SC_TXFREELEVEL_BIT   (1)
#define	SC_TXFREELEVEL_BITS   (1)
#define	SC_RXVALLEVEL   (0x00000001u)
#define	SC_RXVALLEVEL_MASK   (0x00000001u)
#define	SC_RXVALLEVEL_BIT   (0)
#define	SC_RXVALLEVEL_BITS   (1)
#define	GPIO_INTCFGA   *((volatile int32u *)0x4000A860u)
#define	GPIO_INTCFGA_REG   *((volatile int32u *)0x4000A860u)
#define	GPIO_INTCFGA_ADDR   (0x4000A860u)
#define	GPIO_INTCFGA_RESET   (0x00000000u)
#define	GPIO_INTFILT   (0x00000100u)
#define	GPIO_INTFILT_MASK   (0x00000100u)
#define	GPIO_INTFILT_BIT   (8)
#define	GPIO_INTFILT_BITS   (1)
#define	GPIO_INTMOD   (0x000000E0u)
#define	GPIO_INTMOD_MASK   (0x000000E0u)
#define	GPIO_INTMOD_BIT   (5)
#define	GPIO_INTMOD_BITS   (3)
#define	GPIO_INTCFGB   *((volatile int32u *)0x4000A864u)
#define	GPIO_INTCFGB_REG   *((volatile int32u *)0x4000A864u)
#define	GPIO_INTCFGB_ADDR   (0x4000A864u)
#define	GPIO_INTCFGB_RESET   (0x00000000u)
#define	GPIO_INTFILT   (0x00000100u)
#define	GPIO_INTFILT_MASK   (0x00000100u)
#define	GPIO_INTFILT_BIT   (8)
#define	GPIO_INTFILT_BITS   (1)
#define	GPIO_INTMOD   (0x000000E0u)
#define	GPIO_INTMOD_MASK   (0x000000E0u)
#define	GPIO_INTMOD_BIT   (5)
#define	GPIO_INTMOD_BITS   (3)
#define	GPIO_INTCFGC   *((volatile int32u *)0x4000A868u)
#define	GPIO_INTCFGC_REG   *((volatile int32u *)0x4000A868u)
#define	GPIO_INTCFGC_ADDR   (0x4000A868u)
#define	GPIO_INTCFGC_RESET   (0x00000000u)
#define	GPIO_INTFILT   (0x00000100u)
#define	GPIO_INTFILT_MASK   (0x00000100u)
#define	GPIO_INTFILT_BIT   (8)
#define	GPIO_INTFILT_BITS   (1)
#define	GPIO_INTMOD   (0x000000E0u)
#define	GPIO_INTMOD_MASK   (0x000000E0u)
#define	GPIO_INTMOD_BIT   (5)
#define	GPIO_INTMOD_BITS   (3)
#define	GPIO_INTCFGD   *((volatile int32u *)0x4000A86Cu)
#define	GPIO_INTCFGD_REG   *((volatile int32u *)0x4000A86Cu)
#define	GPIO_INTCFGD_ADDR   (0x4000A86Cu)
#define	GPIO_INTCFGD_RESET   (0x00000000u)
#define	GPIO_INTFILT   (0x00000100u)
#define	GPIO_INTFILT_MASK   (0x00000100u)
#define	GPIO_INTFILT_BIT   (8)
#define	GPIO_INTFILT_BITS   (1)
#define	GPIO_INTMOD   (0x000000E0u)
#define	GPIO_INTMOD_MASK   (0x000000E0u)
#define	GPIO_INTMOD_BIT   (5)
#define	GPIO_INTMOD_BITS   (3)
#define	BLOCK_GPIO_BASE   (0x4000B000u)
#define	BLOCK_GPIO_END   (0x4000BC1Cu)
#define	BLOCK_GPIO_SIZE   (BLOCK_GPIO_END - BLOCK_GPIO_BASE + 1)
#define	GPIO_PACFGL   *((volatile int32u *)0x4000B000u)
#define	GPIO_PACFGL_REG   *((volatile int32u *)0x4000B000u)
#define	GPIO_PACFGL_ADDR   (0x4000B000u)
#define	GPIO_PACFGL_RESET   (0x00004444u)
#define	PA3_CFG   (0x0000F000u)
#define	PA3_CFG_MASK   (0x0000F000u)
#define	PA3_CFG_BIT   (12)
#define	PA3_CFG_BITS   (4)
#define	PA2_CFG   (0x00000F00u)
#define	PA2_CFG_MASK   (0x00000F00u)
#define	PA2_CFG_BIT   (8)
#define	PA2_CFG_BITS   (4)
#define	PA1_CFG   (0x000000F0u)
#define	PA1_CFG_MASK   (0x000000F0u)
#define	PA1_CFG_BIT   (4)
#define	PA1_CFG_BITS   (4)
#define	PA0_CFG   (0x0000000Fu)
#define	PA0_CFG_MASK   (0x0000000Fu)
#define	PA0_CFG_BIT   (0)
#define	PA0_CFG_BITS   (4)
#define	GPIOCFG_OUT   (0x1u)
#define	GPIOCFG_OUT_OD   (0x5u)
#define	GPIOCFG_OUT_ALT   (0x9u)
#define	GPIOCFG_OUT_ALT_OD   (0xDu)
#define	GPIOCFG_ANALOG   (0x0u)
#define	GPIOCFG_IN   (0x4u)
#define	GPIOCFG_IN_PUD   (0x8u)
#define	GPIO_PACFGH   *((volatile int32u *)0x4000B004u)
#define	GPIO_PACFGH_REG   *((volatile int32u *)0x4000B004u)
#define	GPIO_PACFGH_ADDR   (0x4000B004u)
#define	GPIO_PACFGH_RESET   (0x00004444u)
#define	PA7_CFG   (0x0000F000u)
#define	PA7_CFG_MASK   (0x0000F000u)
#define	PA7_CFG_BIT   (12)
#define	PA7_CFG_BITS   (4)
#define	PA6_CFG   (0x00000F00u)
#define	PA6_CFG_MASK   (0x00000F00u)
#define	PA6_CFG_BIT   (8)
#define	PA6_CFG_BITS   (4)
#define	PA5_CFG   (0x000000F0u)
#define	PA5_CFG_MASK   (0x000000F0u)
#define	PA5_CFG_BIT   (4)
#define	PA5_CFG_BITS   (4)
#define	PA4_CFG   (0x0000000Fu)
#define	PA4_CFG_MASK   (0x0000000Fu)
#define	PA4_CFG_BIT   (0)
#define	PA4_CFG_BITS   (4)
#define	GPIO_PAIN   *((volatile int32u *)0x4000B008u)
#define	GPIO_PAIN_REG   *((volatile int32u *)0x4000B008u)
#define	GPIO_PAIN_ADDR   (0x4000B008u)
#define	GPIO_PAIN_RESET   (0x00000000u)
#define	PA7   (0x00000080u)
#define	PA7_MASK   (0x00000080u)
#define	PA7_BIT   (7)
#define	PA7_BITS   (1)
#define	PA6   (0x00000040u)
#define	PA6_MASK   (0x00000040u)
#define	PA6_BIT   (6)
#define	PA6_BITS   (1)
#define	PA5   (0x00000020u)
#define	PA5_MASK   (0x00000020u)
#define	PA5_BIT   (5)
#define	PA5_BITS   (1)
#define	PA4   (0x00000010u)
#define	PA4_MASK   (0x00000010u)
#define	PA4_BIT   (4)
#define	PA4_BITS   (1)
#define	PA3   (0x00000008u)
#define	PA3_MASK   (0x00000008u)
#define	PA3_BIT   (3)
#define	PA3_BITS   (1)
#define	PA2   (0x00000004u)
#define	PA2_MASK   (0x00000004u)
#define	PA2_BIT   (2)
#define	PA2_BITS   (1)
#define	PA1   (0x00000002u)
#define	PA1_MASK   (0x00000002u)
#define	PA1_BIT   (1)
#define	PA1_BITS   (1)
#define	PA0   (0x00000001u)
#define	PA0_MASK   (0x00000001u)
#define	PA0_BIT   (0)
#define	PA0_BITS   (1)
#define	GPIO_PAOUT   *((volatile int32u *)0x4000B00Cu)
#define	GPIO_PAOUT_REG   *((volatile int32u *)0x4000B00Cu)
#define	GPIO_PAOUT_ADDR   (0x4000B00Cu)
#define	GPIO_PAOUT_RESET   (0x00000000u)
#define	PA7   (0x00000080u)
#define	PA7_MASK   (0x00000080u)
#define	PA7_BIT   (7)
#define	PA7_BITS   (1)
#define	PA6   (0x00000040u)
#define	PA6_MASK   (0x00000040u)
#define	PA6_BIT   (6)
#define	PA6_BITS   (1)
#define	PA5   (0x00000020u)
#define	PA5_MASK   (0x00000020u)
#define	PA5_BIT   (5)
#define	PA5_BITS   (1)
#define	PA4   (0x00000010u)
#define	PA4_MASK   (0x00000010u)
#define	PA4_BIT   (4)
#define	PA4_BITS   (1)
#define	PA3   (0x00000008u)
#define	PA3_MASK   (0x00000008u)
#define	PA3_BIT   (3)
#define	PA3_BITS   (1)
#define	PA2   (0x00000004u)
#define	PA2_MASK   (0x00000004u)
#define	PA2_BIT   (2)
#define	PA2_BITS   (1)
#define	PA1   (0x00000002u)
#define	PA1_MASK   (0x00000002u)
#define	PA1_BIT   (1)
#define	PA1_BITS   (1)
#define	PA0   (0x00000001u)
#define	PA0_MASK   (0x00000001u)
#define	PA0_BIT   (0)
#define	PA0_BITS   (1)
#define	GPIOOUT_PULLUP   (0x1u)
#define	GPIOOUT_PULLDOWN   (0x0u)
#define	GPIO_PASET   *((volatile int32u *)0x4000B010u)
#define	GPIO_PASET_REG   *((volatile int32u *)0x4000B010u)
#define	GPIO_PASET_ADDR   (0x4000B010u)
#define	GPIO_PASET_RESET   (0x00000000u)
#define	GPIO_PXSETRSVD   (0x0000FF00u)
#define	GPIO_PXSETRSVD_MASK   (0x0000FF00u)
#define	GPIO_PXSETRSVD_BIT   (8)
#define	GPIO_PXSETRSVD_BITS   (8)
#define	PA7   (0x00000080u)
#define	PA7_MASK   (0x00000080u)
#define	PA7_BIT   (7)
#define	PA7_BITS   (1)
#define	PA6   (0x00000040u)
#define	PA6_MASK   (0x00000040u)
#define	PA6_BIT   (6)
#define	PA6_BITS   (1)
#define	PA5   (0x00000020u)
#define	PA5_MASK   (0x00000020u)
#define	PA5_BIT   (5)
#define	PA5_BITS   (1)
#define	PA4   (0x00000010u)
#define	PA4_MASK   (0x00000010u)
#define	PA4_BIT   (4)
#define	PA4_BITS   (1)
#define	PA3   (0x00000008u)
#define	PA3_MASK   (0x00000008u)
#define	PA3_BIT   (3)
#define	PA3_BITS   (1)
#define	PA2   (0x00000004u)
#define	PA2_MASK   (0x00000004u)
#define	PA2_BIT   (2)
#define	PA2_BITS   (1)
#define	PA1   (0x00000002u)
#define	PA1_MASK   (0x00000002u)
#define	PA1_BIT   (1)
#define	PA1_BITS   (1)
#define	PA0   (0x00000001u)
#define	PA0_MASK   (0x00000001u)
#define	PA0_BIT   (0)
#define	PA0_BITS   (1)
#define	GPIO_PACLR   *((volatile int32u *)0x4000B014u)
#define	GPIO_PACLR_REG   *((volatile int32u *)0x4000B014u)
#define	GPIO_PACLR_ADDR   (0x4000B014u)
#define	GPIO_PACLR_RESET   (0x00000000u)
#define	PA7   (0x00000080u)
#define	PA7_MASK   (0x00000080u)
#define	PA7_BIT   (7)
#define	PA7_BITS   (1)
#define	PA6   (0x00000040u)
#define	PA6_MASK   (0x00000040u)
#define	PA6_BIT   (6)
#define	PA6_BITS   (1)
#define	PA5   (0x00000020u)
#define	PA5_MASK   (0x00000020u)
#define	PA5_BIT   (5)
#define	PA5_BITS   (1)
#define	PA4   (0x00000010u)
#define	PA4_MASK   (0x00000010u)
#define	PA4_BIT   (4)
#define	PA4_BITS   (1)
#define	PA3   (0x00000008u)
#define	PA3_MASK   (0x00000008u)
#define	PA3_BIT   (3)
#define	PA3_BITS   (1)
#define	PA2   (0x00000004u)
#define	PA2_MASK   (0x00000004u)
#define	PA2_BIT   (2)
#define	PA2_BITS   (1)
#define	PA1   (0x00000002u)
#define	PA1_MASK   (0x00000002u)
#define	PA1_BIT   (1)
#define	PA1_BITS   (1)
#define	PA0   (0x00000001u)
#define	PA0_MASK   (0x00000001u)
#define	PA0_BIT   (0)
#define	PA0_BITS   (1)
#define	GPIO_PBCFGL   *((volatile int32u *)0x4000B400u)
#define	GPIO_PBCFGL_REG   *((volatile int32u *)0x4000B400u)
#define	GPIO_PBCFGL_ADDR   (0x4000B400u)
#define	GPIO_PBCFGL_RESET   (0x00004444u)
#define	PB3_CFG   (0x0000F000u)
#define	PB3_CFG_MASK   (0x0000F000u)
#define	PB3_CFG_BIT   (12)
#define	PB3_CFG_BITS   (4)
#define	PB2_CFG   (0x00000F00u)
#define	PB2_CFG_MASK   (0x00000F00u)
#define	PB2_CFG_BIT   (8)
#define	PB2_CFG_BITS   (4)
#define	PB1_CFG   (0x000000F0u)
#define	PB1_CFG_MASK   (0x000000F0u)
#define	PB1_CFG_BIT   (4)
#define	PB1_CFG_BITS   (4)
#define	PB0_CFG   (0x0000000Fu)
#define	PB0_CFG_MASK   (0x0000000Fu)
#define	PB0_CFG_BIT   (0)
#define	PB0_CFG_BITS   (4)
#define	GPIO_PBCFGH   *((volatile int32u *)0x4000B404u)
#define	GPIO_PBCFGH_REG   *((volatile int32u *)0x4000B404u)
#define	GPIO_PBCFGH_ADDR   (0x4000B404u)
#define	GPIO_PBCFGH_RESET   (0x00004444u)
#define	PB7_CFG   (0x0000F000u)
#define	PB7_CFG_MASK   (0x0000F000u)
#define	PB7_CFG_BIT   (12)
#define	PB7_CFG_BITS   (4)
#define	PB6_CFG   (0x00000F00u)
#define	PB6_CFG_MASK   (0x00000F00u)
#define	PB6_CFG_BIT   (8)
#define	PB6_CFG_BITS   (4)
#define	PB5_CFG   (0x000000F0u)
#define	PB5_CFG_MASK   (0x000000F0u)
#define	PB5_CFG_BIT   (4)
#define	PB5_CFG_BITS   (4)
#define	PB4_CFG   (0x0000000Fu)
#define	PB4_CFG_MASK   (0x0000000Fu)
#define	PB4_CFG_BIT   (0)
#define	PB4_CFG_BITS   (4)
#define	GPIO_PBIN   *((volatile int32u *)0x4000B408u)
#define	GPIO_PBIN_REG   *((volatile int32u *)0x4000B408u)
#define	GPIO_PBIN_ADDR   (0x4000B408u)
#define	GPIO_PBIN_RESET   (0x00000000u)
#define	PB7   (0x00000080u)
#define	PB7_MASK   (0x00000080u)
#define	PB7_BIT   (7)
#define	PB7_BITS   (1)
#define	PB6   (0x00000040u)
#define	PB6_MASK   (0x00000040u)
#define	PB6_BIT   (6)
#define	PB6_BITS   (1)
#define	PB5   (0x00000020u)
#define	PB5_MASK   (0x00000020u)
#define	PB5_BIT   (5)
#define	PB5_BITS   (1)
#define	PB4   (0x00000010u)
#define	PB4_MASK   (0x00000010u)
#define	PB4_BIT   (4)
#define	PB4_BITS   (1)
#define	PB3   (0x00000008u)
#define	PB3_MASK   (0x00000008u)
#define	PB3_BIT   (3)
#define	PB3_BITS   (1)
#define	PB2   (0x00000004u)
#define	PB2_MASK   (0x00000004u)
#define	PB2_BIT   (2)
#define	PB2_BITS   (1)
#define	PB1   (0x00000002u)
#define	PB1_MASK   (0x00000002u)
#define	PB1_BIT   (1)
#define	PB1_BITS   (1)
#define	PB0   (0x00000001u)
#define	PB0_MASK   (0x00000001u)
#define	PB0_BIT   (0)
#define	PB0_BITS   (1)
#define	GPIO_PBOUT   *((volatile int32u *)0x4000B40Cu)
#define	GPIO_PBOUT_REG   *((volatile int32u *)0x4000B40Cu)
#define	GPIO_PBOUT_ADDR   (0x4000B40Cu)
#define	GPIO_PBOUT_RESET   (0x00000000u)
#define	PB7   (0x00000080u)
#define	PB7_MASK   (0x00000080u)
#define	PB7_BIT   (7)
#define	PB7_BITS   (1)
#define	PB6   (0x00000040u)
#define	PB6_MASK   (0x00000040u)
#define	PB6_BIT   (6)
#define	PB6_BITS   (1)
#define	PB5   (0x00000020u)
#define	PB5_MASK   (0x00000020u)
#define	PB5_BIT   (5)
#define	PB5_BITS   (1)
#define	PB4   (0x00000010u)
#define	PB4_MASK   (0x00000010u)
#define	PB4_BIT   (4)
#define	PB4_BITS   (1)
#define	PB3   (0x00000008u)
#define	PB3_MASK   (0x00000008u)
#define	PB3_BIT   (3)
#define	PB3_BITS   (1)
#define	PB2   (0x00000004u)
#define	PB2_MASK   (0x00000004u)
#define	PB2_BIT   (2)
#define	PB2_BITS   (1)
#define	PB1   (0x00000002u)
#define	PB1_MASK   (0x00000002u)
#define	PB1_BIT   (1)
#define	PB1_BITS   (1)
#define	PB0   (0x00000001u)
#define	PB0_MASK   (0x00000001u)
#define	PB0_BIT   (0)
#define	PB0_BITS   (1)
#define	GPIO_PBSET   *((volatile int32u *)0x4000B410u)
#define	GPIO_PBSET_REG   *((volatile int32u *)0x4000B410u)
#define	GPIO_PBSET_ADDR   (0x4000B410u)
#define	GPIO_PBSET_RESET   (0x00000000u)
#define	GPIO_PXSETRSVD   (0x0000FF00u)
#define	GPIO_PXSETRSVD_MASK   (0x0000FF00u)
#define	GPIO_PXSETRSVD_BIT   (8)
#define	GPIO_PXSETRSVD_BITS   (8)
#define	PB7   (0x00000080u)
#define	PB7_MASK   (0x00000080u)
#define	PB7_BIT   (7)
#define	PB7_BITS   (1)
#define	PB6   (0x00000040u)
#define	PB6_MASK   (0x00000040u)
#define	PB6_BIT   (6)
#define	PB6_BITS   (1)
#define	PB5   (0x00000020u)
#define	PB5_MASK   (0x00000020u)
#define	PB5_BIT   (5)
#define	PB5_BITS   (1)
#define	PB4   (0x00000010u)
#define	PB4_MASK   (0x00000010u)
#define	PB4_BIT   (4)
#define	PB4_BITS   (1)
#define	PB3   (0x00000008u)
#define	PB3_MASK   (0x00000008u)
#define	PB3_BIT   (3)
#define	PB3_BITS   (1)
#define	PB2   (0x00000004u)
#define	PB2_MASK   (0x00000004u)
#define	PB2_BIT   (2)
#define	PB2_BITS   (1)
#define	PB1   (0x00000002u)
#define	PB1_MASK   (0x00000002u)
#define	PB1_BIT   (1)
#define	PB1_BITS   (1)
#define	PB0   (0x00000001u)
#define	PB0_MASK   (0x00000001u)
#define	PB0_BIT   (0)
#define	PB0_BITS   (1)
#define	GPIO_PBCLR   *((volatile int32u *)0x4000B414u)
#define	GPIO_PBCLR_REG   *((volatile int32u *)0x4000B414u)
#define	GPIO_PBCLR_ADDR   (0x4000B414u)
#define	GPIO_PBCLR_RESET   (0x00000000u)
#define	PB7   (0x00000080u)
#define	PB7_MASK   (0x00000080u)
#define	PB7_BIT   (7)
#define	PB7_BITS   (1)
#define	PB6   (0x00000040u)
#define	PB6_MASK   (0x00000040u)
#define	PB6_BIT   (6)
#define	PB6_BITS   (1)
#define	PB5   (0x00000020u)
#define	PB5_MASK   (0x00000020u)
#define	PB5_BIT   (5)
#define	PB5_BITS   (1)
#define	PB4   (0x00000010u)
#define	PB4_MASK   (0x00000010u)
#define	PB4_BIT   (4)
#define	PB4_BITS   (1)
#define	PB3   (0x00000008u)
#define	PB3_MASK   (0x00000008u)
#define	PB3_BIT   (3)
#define	PB3_BITS   (1)
#define	PB2   (0x00000004u)
#define	PB2_MASK   (0x00000004u)
#define	PB2_BIT   (2)
#define	PB2_BITS   (1)
#define	PB1   (0x00000002u)
#define	PB1_MASK   (0x00000002u)
#define	PB1_BIT   (1)
#define	PB1_BITS   (1)
#define	PB0   (0x00000001u)
#define	PB0_MASK   (0x00000001u)
#define	PB0_BIT   (0)
#define	PB0_BITS   (1)
#define	GPIO_PCCFGL   *((volatile int32u *)0x4000B800u)
#define	GPIO_PCCFGL_REG   *((volatile int32u *)0x4000B800u)
#define	GPIO_PCCFGL_ADDR   (0x4000B800u)
#define	GPIO_PCCFGL_RESET   (0x00004444u)
#define	PC3_CFG   (0x0000F000u)
#define	PC3_CFG_MASK   (0x0000F000u)
#define	PC3_CFG_BIT   (12)
#define	PC3_CFG_BITS   (4)
#define	PC2_CFG   (0x00000F00u)
#define	PC2_CFG_MASK   (0x00000F00u)
#define	PC2_CFG_BIT   (8)
#define	PC2_CFG_BITS   (4)
#define	PC1_CFG   (0x000000F0u)
#define	PC1_CFG_MASK   (0x000000F0u)
#define	PC1_CFG_BIT   (4)
#define	PC1_CFG_BITS   (4)
#define	PC0_CFG   (0x0000000Fu)
#define	PC0_CFG_MASK   (0x0000000Fu)
#define	PC0_CFG_BIT   (0)
#define	PC0_CFG_BITS   (4)
#define	GPIO_PCCFGH   *((volatile int32u *)0x4000B804u)
#define	GPIO_PCCFGH_REG   *((volatile int32u *)0x4000B804u)
#define	GPIO_PCCFGH_ADDR   (0x4000B804u)
#define	GPIO_PCCFGH_RESET   (0x00004444u)
#define	PC7_CFG   (0x0000F000u)
#define	PC7_CFG_MASK   (0x0000F000u)
#define	PC7_CFG_BIT   (12)
#define	PC7_CFG_BITS   (4)
#define	PC6_CFG   (0x00000F00u)
#define	PC6_CFG_MASK   (0x00000F00u)
#define	PC6_CFG_BIT   (8)
#define	PC6_CFG_BITS   (4)
#define	PC5_CFG   (0x000000F0u)
#define	PC5_CFG_MASK   (0x000000F0u)
#define	PC5_CFG_BIT   (4)
#define	PC5_CFG_BITS   (4)
#define	PC4_CFG   (0x0000000Fu)
#define	PC4_CFG_MASK   (0x0000000Fu)
#define	PC4_CFG_BIT   (0)
#define	PC4_CFG_BITS   (4)
#define	GPIO_PCIN   *((volatile int32u *)0x4000B808u)
#define	GPIO_PCIN_REG   *((volatile int32u *)0x4000B808u)
#define	GPIO_PCIN_ADDR   (0x4000B808u)
#define	GPIO_PCIN_RESET   (0x00000000u)
#define	PC7   (0x00000080u)
#define	PC7_MASK   (0x00000080u)
#define	PC7_BIT   (7)
#define	PC7_BITS   (1)
#define	PC6   (0x00000040u)
#define	PC6_MASK   (0x00000040u)
#define	PC6_BIT   (6)
#define	PC6_BITS   (1)
#define	PC5   (0x00000020u)
#define	PC5_MASK   (0x00000020u)
#define	PC5_BIT   (5)
#define	PC5_BITS   (1)
#define	PC4   (0x00000010u)
#define	PC4_MASK   (0x00000010u)
#define	PC4_BIT   (4)
#define	PC4_BITS   (1)
#define	PC3   (0x00000008u)
#define	PC3_MASK   (0x00000008u)
#define	PC3_BIT   (3)
#define	PC3_BITS   (1)
#define	PC2   (0x00000004u)
#define	PC2_MASK   (0x00000004u)
#define	PC2_BIT   (2)
#define	PC2_BITS   (1)
#define	PC1   (0x00000002u)
#define	PC1_MASK   (0x00000002u)
#define	PC1_BIT   (1)
#define	PC1_BITS   (1)
#define	PC0   (0x00000001u)
#define	PC0_MASK   (0x00000001u)
#define	PC0_BIT   (0)
#define	PC0_BITS   (1)
#define	GPIO_PCOUT   *((volatile int32u *)0x4000B80Cu)
#define	GPIO_PCOUT_REG   *((volatile int32u *)0x4000B80Cu)
#define	GPIO_PCOUT_ADDR   (0x4000B80Cu)
#define	GPIO_PCOUT_RESET   (0x00000000u)
#define	PC7   (0x00000080u)
#define	PC7_MASK   (0x00000080u)
#define	PC7_BIT   (7)
#define	PC7_BITS   (1)
#define	PC6   (0x00000040u)
#define	PC6_MASK   (0x00000040u)
#define	PC6_BIT   (6)
#define	PC6_BITS   (1)
#define	PC5   (0x00000020u)
#define	PC5_MASK   (0x00000020u)
#define	PC5_BIT   (5)
#define	PC5_BITS   (1)
#define	PC4   (0x00000010u)
#define	PC4_MASK   (0x00000010u)
#define	PC4_BIT   (4)
#define	PC4_BITS   (1)
#define	PC3   (0x00000008u)
#define	PC3_MASK   (0x00000008u)
#define	PC3_BIT   (3)
#define	PC3_BITS   (1)
#define	PC2   (0x00000004u)
#define	PC2_MASK   (0x00000004u)
#define	PC2_BIT   (2)
#define	PC2_BITS   (1)
#define	PC1   (0x00000002u)
#define	PC1_MASK   (0x00000002u)
#define	PC1_BIT   (1)
#define	PC1_BITS   (1)
#define	PC0   (0x00000001u)
#define	PC0_MASK   (0x00000001u)
#define	PC0_BIT   (0)
#define	PC0_BITS   (1)
#define	GPIO_PCSET   *((volatile int32u *)0x4000B810u)
#define	GPIO_PCSET_REG   *((volatile int32u *)0x4000B810u)
#define	GPIO_PCSET_ADDR   (0x4000B810u)
#define	GPIO_PCSET_RESET   (0x00000000u)
#define	GPIO_PXSETRSVD   (0x0000FF00u)
#define	GPIO_PXSETRSVD_MASK   (0x0000FF00u)
#define	GPIO_PXSETRSVD_BIT   (8)
#define	GPIO_PXSETRSVD_BITS   (8)
#define	PC7   (0x00000080u)
#define	PC7_MASK   (0x00000080u)
#define	PC7_BIT   (7)
#define	PC7_BITS   (1)
#define	PC6   (0x00000040u)
#define	PC6_MASK   (0x00000040u)
#define	PC6_BIT   (6)
#define	PC6_BITS   (1)
#define	PC5   (0x00000020u)
#define	PC5_MASK   (0x00000020u)
#define	PC5_BIT   (5)
#define	PC5_BITS   (1)
#define	PC4   (0x00000010u)
#define	PC4_MASK   (0x00000010u)
#define	PC4_BIT   (4)
#define	PC4_BITS   (1)
#define	PC3   (0x00000008u)
#define	PC3_MASK   (0x00000008u)
#define	PC3_BIT   (3)
#define	PC3_BITS   (1)
#define	PC2   (0x00000004u)
#define	PC2_MASK   (0x00000004u)
#define	PC2_BIT   (2)
#define	PC2_BITS   (1)
#define	PC1   (0x00000002u)
#define	PC1_MASK   (0x00000002u)
#define	PC1_BIT   (1)
#define	PC1_BITS   (1)
#define	PC0   (0x00000001u)
#define	PC0_MASK   (0x00000001u)
#define	PC0_BIT   (0)
#define	PC0_BITS   (1)
#define	GPIO_PCCLR   *((volatile int32u *)0x4000B814u)
#define	GPIO_PCCLR_REG   *((volatile int32u *)0x4000B814u)
#define	GPIO_PCCLR_ADDR   (0x4000B814u)
#define	GPIO_PCCLR_RESET   (0x00000000u)
#define	PC7   (0x00000080u)
#define	PC7_MASK   (0x00000080u)
#define	PC7_BIT   (7)
#define	PC7_BITS   (1)
#define	PC6   (0x00000040u)
#define	PC6_MASK   (0x00000040u)
#define	PC6_BIT   (6)
#define	PC6_BITS   (1)
#define	PC5   (0x00000020u)
#define	PC5_MASK   (0x00000020u)
#define	PC5_BIT   (5)
#define	PC5_BITS   (1)
#define	PC4   (0x00000010u)
#define	PC4_MASK   (0x00000010u)
#define	PC4_BIT   (4)
#define	PC4_BITS   (1)
#define	PC3   (0x00000008u)
#define	PC3_MASK   (0x00000008u)
#define	PC3_BIT   (3)
#define	PC3_BITS   (1)
#define	PC2   (0x00000004u)
#define	PC2_MASK   (0x00000004u)
#define	PC2_BIT   (2)
#define	PC2_BITS   (1)
#define	PC1   (0x00000002u)
#define	PC1_MASK   (0x00000002u)
#define	PC1_BIT   (1)
#define	PC1_BITS   (1)
#define	PC0   (0x00000001u)
#define	PC0_MASK   (0x00000001u)
#define	PC0_BIT   (0)
#define	PC0_BITS   (1)
#define	GPIO_DBGCFG   *((volatile int32u *)0x4000BC00u)
#define	GPIO_DBGCFG_REG   *((volatile int32u *)0x4000BC00u)
#define	GPIO_DBGCFG_ADDR   (0x4000BC00u)
#define	GPIO_DBGCFG_RESET   (0x00000010u)
#define	GPIO_DEBUGDIS   (0x00000020u)
#define	GPIO_DEBUGDIS_MASK   (0x00000020u)
#define	GPIO_DEBUGDIS_BIT   (5)
#define	GPIO_DEBUGDIS_BITS   (1)
#define	GPIO_EXTREGEN   (0x00000010u)
#define	GPIO_EXTREGEN_MASK   (0x00000010u)
#define	GPIO_EXTREGEN_BIT   (4)
#define	GPIO_EXTREGEN_BITS   (1)
#define	GPIO_DBGCFGRSVD   (0x00000008u)
#define	GPIO_DBGCFGRSVD_MASK   (0x00000008u)
#define	GPIO_DBGCFGRSVD_BIT   (3)
#define	GPIO_DBGCFGRSVD_BITS   (1)
#define	GPIO_DBGSTAT   *((volatile int32u *)0x4000BC04u)
#define	GPIO_DBGSTAT_REG   *((volatile int32u *)0x4000BC04u)
#define	GPIO_DBGSTAT_ADDR   (0x4000BC04u)
#define	GPIO_DBGSTAT_RESET   (0x00000000u)
#define	GPIO_BOOTMODE   (0x00000008u)
#define	GPIO_BOOTMODE_MASK   (0x00000008u)
#define	GPIO_BOOTMODE_BIT   (3)
#define	GPIO_BOOTMODE_BITS   (1)
#define	GPIO_FORCEDBG   (0x00000002u)
#define	GPIO_FORCEDBG_MASK   (0x00000002u)
#define	GPIO_FORCEDBG_BIT   (1)
#define	GPIO_FORCEDBG_BITS   (1)
#define	GPIO_SWEN   (0x00000001u)
#define	GPIO_SWEN_MASK   (0x00000001u)
#define	GPIO_SWEN_BIT   (0)
#define	GPIO_SWEN_BITS   (1)
#define	GPIO_PAWAKE   *((volatile int32u *)0x4000BC08u)
#define	GPIO_PAWAKE_REG   *((volatile int32u *)0x4000BC08u)
#define	GPIO_PAWAKE_ADDR   (0x4000BC08u)
#define	GPIO_PAWAKE_RESET   (0x00000000u)
#define	PA7   (0x00000080u)
#define	PA7_MASK   (0x00000080u)
#define	PA7_BIT   (7)
#define	PA7_BITS   (1)
#define	PA6   (0x00000040u)
#define	PA6_MASK   (0x00000040u)
#define	PA6_BIT   (6)
#define	PA6_BITS   (1)
#define	PA5   (0x00000020u)
#define	PA5_MASK   (0x00000020u)
#define	PA5_BIT   (5)
#define	PA5_BITS   (1)
#define	PA4   (0x00000010u)
#define	PA4_MASK   (0x00000010u)
#define	PA4_BIT   (4)
#define	PA4_BITS   (1)
#define	PA3   (0x00000008u)
#define	PA3_MASK   (0x00000008u)
#define	PA3_BIT   (3)
#define	PA3_BITS   (1)
#define	PA2   (0x00000004u)
#define	PA2_MASK   (0x00000004u)
#define	PA2_BIT   (2)
#define	PA2_BITS   (1)
#define	PA1   (0x00000002u)
#define	PA1_MASK   (0x00000002u)
#define	PA1_BIT   (1)
#define	PA1_BITS   (1)
#define	PA0   (0x00000001u)
#define	PA0_MASK   (0x00000001u)
#define	PA0_BIT   (0)
#define	PA0_BITS   (1)
#define	GPIO_PBWAKE   *((volatile int32u *)0x4000BC0Cu)
#define	GPIO_PBWAKE_REG   *((volatile int32u *)0x4000BC0Cu)
#define	GPIO_PBWAKE_ADDR   (0x4000BC0Cu)
#define	GPIO_PBWAKE_RESET   (0x00000000u)
#define	PB7   (0x00000080u)
#define	PB7_MASK   (0x00000080u)
#define	PB7_BIT   (7)
#define	PB7_BITS   (1)
#define	PB6   (0x00000040u)
#define	PB6_MASK   (0x00000040u)
#define	PB6_BIT   (6)
#define	PB6_BITS   (1)
#define	PB5   (0x00000020u)
#define	PB5_MASK   (0x00000020u)
#define	PB5_BIT   (5)
#define	PB5_BITS   (1)
#define	PB4   (0x00000010u)
#define	PB4_MASK   (0x00000010u)
#define	PB4_BIT   (4)
#define	PB4_BITS   (1)
#define	PB3   (0x00000008u)
#define	PB3_MASK   (0x00000008u)
#define	PB3_BIT   (3)
#define	PB3_BITS   (1)
#define	PB2   (0x00000004u)
#define	PB2_MASK   (0x00000004u)
#define	PB2_BIT   (2)
#define	PB2_BITS   (1)
#define	PB1   (0x00000002u)
#define	PB1_MASK   (0x00000002u)
#define	PB1_BIT   (1)
#define	PB1_BITS   (1)
#define	PB0   (0x00000001u)
#define	PB0_MASK   (0x00000001u)
#define	PB0_BIT   (0)
#define	PB0_BITS   (1)
#define	GPIO_PCWAKE   *((volatile int32u *)0x4000BC10u)
#define	GPIO_PCWAKE_REG   *((volatile int32u *)0x4000BC10u)
#define	GPIO_PCWAKE_ADDR   (0x4000BC10u)
#define	GPIO_PCWAKE_RESET   (0x00000000u)
#define	PC7   (0x00000080u)
#define	PC7_MASK   (0x00000080u)
#define	PC7_BIT   (7)
#define	PC7_BITS   (1)
#define	PC6   (0x00000040u)
#define	PC6_MASK   (0x00000040u)
#define	PC6_BIT   (6)
#define	PC6_BITS   (1)
#define	PC5   (0x00000020u)
#define	PC5_MASK   (0x00000020u)
#define	PC5_BIT   (5)
#define	PC5_BITS   (1)
#define	PC4   (0x00000010u)
#define	PC4_MASK   (0x00000010u)
#define	PC4_BIT   (4)
#define	PC4_BITS   (1)
#define	PC3   (0x00000008u)
#define	PC3_MASK   (0x00000008u)
#define	PC3_BIT   (3)
#define	PC3_BITS   (1)
#define	PC2   (0x00000004u)
#define	PC2_MASK   (0x00000004u)
#define	PC2_BIT   (2)
#define	PC2_BITS   (1)
#define	PC1   (0x00000002u)
#define	PC1_MASK   (0x00000002u)
#define	PC1_BIT   (1)
#define	PC1_BITS   (1)
#define	PC0   (0x00000001u)
#define	PC0_MASK   (0x00000001u)
#define	PC0_BIT   (0)
#define	PC0_BITS   (1)
#define	GPIO_IRQCSEL   *((volatile int32u *)0x4000BC14u)
#define	GPIO_IRQCSEL_REG   *((volatile int32u *)0x4000BC14u)
#define	GPIO_IRQCSEL_ADDR   (0x4000BC14u)
#define	GPIO_IRQCSEL_RESET   (0x0000000Fu)
#define	SEL_GPIO   (0x0000001Fu)
#define	SEL_GPIO_MASK   (0x0000001Fu)
#define	SEL_GPIO_BIT   (0)
#define	SEL_GPIO_BITS   (5)
#define	GPIO_IRQDSEL   *((volatile int32u *)0x4000BC18u)
#define	GPIO_IRQDSEL_REG   *((volatile int32u *)0x4000BC18u)
#define	GPIO_IRQDSEL_ADDR   (0x4000BC18u)
#define	GPIO_IRQDSEL_RESET   (0x00000010u)
#define	SEL_GPIO   (0x0000001Fu)
#define	SEL_GPIO_MASK   (0x0000001Fu)
#define	SEL_GPIO_BIT   (0)
#define	SEL_GPIO_BITS   (5)
#define	GPIO_WAKEFILT   *((volatile int32u *)0x4000BC1Cu)
#define	GPIO_WAKEFILT_REG   *((volatile int32u *)0x4000BC1Cu)
#define	GPIO_WAKEFILT_ADDR   (0x4000BC1Cu)
#define	GPIO_WAKEFILT_RESET   (0x00000000u)
#define	IRQD_WAKE_FILTER   (0x00000008u)
#define	IRQD_WAKE_FILTER_MASK   (0x00000008u)
#define	IRQD_WAKE_FILTER_BIT   (3)
#define	IRQD_WAKE_FILTER_BITS   (1)
#define	SC2_WAKE_FILTER   (0x00000004u)
#define	SC2_WAKE_FILTER_MASK   (0x00000004u)
#define	SC2_WAKE_FILTER_BIT   (2)
#define	SC2_WAKE_FILTER_BITS   (1)
#define	SC1_WAKE_FILTER   (0x00000002u)
#define	SC1_WAKE_FILTER_MASK   (0x00000002u)
#define	SC1_WAKE_FILTER_BIT   (1)
#define	SC1_WAKE_FILTER_BITS   (1)
#define	GPIO_WAKE_FILTER   (0x00000001u)
#define	GPIO_WAKE_FILTER_MASK   (0x00000001u)
#define	GPIO_WAKE_FILTER_BIT   (0)
#define	GPIO_WAKE_FILTER_BITS   (1)
#define	BLOCK_SERIAL_BASE   (0x4000C000u)
#define	BLOCK_SERIAL_END   (0x4000C870u)
#define	BLOCK_SERIAL_SIZE   (BLOCK_SERIAL_END - BLOCK_SERIAL_BASE + 1)
#define	SC2_RXBEGA   *((volatile int32u *)0x4000C000u)
#define	SC2_RXBEGA_REG   *((volatile int32u *)0x4000C000u)
#define	SC2_RXBEGA_ADDR   (0x4000C000u)
#define	SC2_RXBEGA_RESET   (0x20000000u)
#define	SC2_RXBEGA_FIXED   (0xFFFFE000u)
#define	SC2_RXBEGA_FIXED_MASK   (0xFFFFE000u)
#define	SC2_RXBEGA_FIXED_BIT   (13)
#define	SC2_RXBEGA_FIXED_BITS   (19)
#define	SC_RXBEGA   (0x00001FFFu)
#define	SC_RXBEGA_MASK   (0x00001FFFu)
#define	SC_RXBEGA_BIT   (0)
#define	SC_RXBEGA_BITS   (13)
#define	SC2_RXENDA   *((volatile int32u *)0x4000C004u)
#define	SC2_RXENDA_REG   *((volatile int32u *)0x4000C004u)
#define	SC2_RXENDA_ADDR   (0x4000C004u)
#define	SC2_RXENDA_RESET   (0x20000000u)
#define	SC2_RXENDA_FIXED   (0xFFFFE000u)
#define	SC2_RXENDA_FIXED_MASK   (0xFFFFE000u)
#define	SC2_RXENDA_FIXED_BIT   (13)
#define	SC2_RXENDA_FIXED_BITS   (19)
#define	SC_RXENDA   (0x00001FFFu)
#define	SC_RXENDA_MASK   (0x00001FFFu)
#define	SC_RXENDA_BIT   (0)
#define	SC_RXENDA_BITS   (13)
#define	SC2_RXBEGB   *((volatile int32u *)0x4000C008u)
#define	SC2_RXBEGB_REG   *((volatile int32u *)0x4000C008u)
#define	SC2_RXBEGB_ADDR   (0x4000C008u)
#define	SC2_RXBEGB_RESET   (0x20000000u)
#define	SC2_RXBEGB_FIXED   (0xFFFFE000u)
#define	SC2_RXBEGB_FIXED_MASK   (0xFFFFE000u)
#define	SC2_RXBEGB_FIXED_BIT   (13)
#define	SC2_RXBEGB_FIXED_BITS   (19)
#define	SC_RXBEGB   (0x00001FFFu)
#define	SC_RXBEGB_MASK   (0x00001FFFu)
#define	SC_RXBEGB_BIT   (0)
#define	SC_RXBEGB_BITS   (13)
#define	SC2_RXENDB   *((volatile int32u *)0x4000C00Cu)
#define	SC2_RXENDB_REG   *((volatile int32u *)0x4000C00Cu)
#define	SC2_RXENDB_ADDR   (0x4000C00Cu)
#define	SC2_RXENDB_RESET   (0x20000000u)
#define	SC2_RXENDB_FIXED   (0xFFFFE000u)
#define	SC2_RXENDB_FIXED_MASK   (0xFFFFE000u)
#define	SC2_RXENDB_FIXED_BIT   (13)
#define	SC2_RXENDB_FIXED_BITS   (19)
#define	SC_RXENDB   (0x00001FFFu)
#define	SC_RXENDB_MASK   (0x00001FFFu)
#define	SC_RXENDB_BIT   (0)
#define	SC_RXENDB_BITS   (13)
#define	SC2_TXBEGA   *((volatile int32u *)0x4000C010u)
#define	SC2_TXBEGA_REG   *((volatile int32u *)0x4000C010u)
#define	SC2_TXBEGA_ADDR   (0x4000C010u)
#define	SC2_TXBEGA_RESET   (0x20000000u)
#define	SC2_TXBEGA_FIXED   (0xFFFFE000u)
#define	SC2_TXBEGA_FIXED_MASK   (0xFFFFE000u)
#define	SC2_TXBEGA_FIXED_BIT   (13)
#define	SC2_TXBEGA_FIXED_BITS   (19)
#define	SC_TXBEGA   (0x00001FFFu)
#define	SC_TXBEGA_MASK   (0x00001FFFu)
#define	SC_TXBEGA_BIT   (0)
#define	SC_TXBEGA_BITS   (13)
#define	SC2_TXENDA   *((volatile int32u *)0x4000C014u)
#define	SC2_TXENDA_REG   *((volatile int32u *)0x4000C014u)
#define	SC2_TXENDA_ADDR   (0x4000C014u)
#define	SC2_TXENDA_RESET   (0x20000000u)
#define	SC2_TXENDA_FIXED   (0xFFFFE000u)
#define	SC2_TXENDA_FIXED_MASK   (0xFFFFE000u)
#define	SC2_TXENDA_FIXED_BIT   (13)
#define	SC2_TXENDA_FIXED_BITS   (19)
#define	SC_TXENDA   (0x00001FFFu)
#define	SC_TXENDA_MASK   (0x00001FFFu)
#define	SC_TXENDA_BIT   (0)
#define	SC_TXENDA_BITS   (13)
#define	SC2_TXBEGB   *((volatile int32u *)0x4000C018u)
#define	SC2_TXBEGB_REG   *((volatile int32u *)0x4000C018u)
#define	SC2_TXBEGB_ADDR   (0x4000C018u)
#define	SC2_TXBEGB_RESET   (0x20000000u)
#define	SC2_TXBEGB_FIXED   (0xFFFFE000u)
#define	SC2_TXBEGB_FIXED_MASK   (0xFFFFE000u)
#define	SC2_TXBEGB_FIXED_BIT   (13)
#define	SC2_TXBEGB_FIXED_BITS   (19)
#define	SC_TXBEGB   (0x00001FFFu)
#define	SC_TXBEGB_MASK   (0x00001FFFu)
#define	SC_TXBEGB_BIT   (0)
#define	SC_TXBEGB_BITS   (13)
#define	SC2_TXENDB   *((volatile int32u *)0x4000C01Cu)
#define	SC2_TXENDB_REG   *((volatile int32u *)0x4000C01Cu)
#define	SC2_TXENDB_ADDR   (0x4000C01Cu)
#define	SC2_TXENDB_RESET   (0x20000000u)
#define	SC2_TXENDB_FIXED   (0xFFFFE000u)
#define	SC2_TXENDB_FIXED_MASK   (0xFFFFE000u)
#define	SC2_TXENDB_FIXED_BIT   (13)
#define	SC2_TXENDB_FIXED_BITS   (19)
#define	SC_TXENDB   (0x00001FFFu)
#define	SC_TXENDB_MASK   (0x00001FFFu)
#define	SC_TXENDB_BIT   (0)
#define	SC_TXENDB_BITS   (13)
#define	SC2_RXCNTA   *((volatile int32u *)0x4000C020u)
#define	SC2_RXCNTA_REG   *((volatile int32u *)0x4000C020u)
#define	SC2_RXCNTA_ADDR   (0x4000C020u)
#define	SC2_RXCNTA_RESET   (0x00000000u)
#define	SC_RXCNTA   (0x00001FFFu)
#define	SC_RXCNTA_MASK   (0x00001FFFu)
#define	SC_RXCNTA_BIT   (0)
#define	SC_RXCNTA_BITS   (13)
#define	SC2_RXCNTB   *((volatile int32u *)0x4000C024u)
#define	SC2_RXCNTB_REG   *((volatile int32u *)0x4000C024u)
#define	SC2_RXCNTB_ADDR   (0x4000C024u)
#define	SC2_RXCNTB_RESET   (0x00000000u)
#define	SC_RXCNTB   (0x00001FFFu)
#define	SC_RXCNTB_MASK   (0x00001FFFu)
#define	SC_RXCNTB_BIT   (0)
#define	SC_RXCNTB_BITS   (13)
#define	SC2_TXCNT   *((volatile int32u *)0x4000C028u)
#define	SC2_TXCNT_REG   *((volatile int32u *)0x4000C028u)
#define	SC2_TXCNT_ADDR   (0x4000C028u)
#define	SC2_TXCNT_RESET   (0x00000000u)
#define	SC_TXCNT   (0x00001FFFu)
#define	SC_TXCNT_MASK   (0x00001FFFu)
#define	SC_TXCNT_BIT   (0)
#define	SC_TXCNT_BITS   (13)
#define	SC2_DMASTAT   *((volatile int32u *)0x4000C02Cu)
#define	SC2_DMASTAT_REG   *((volatile int32u *)0x4000C02Cu)
#define	SC2_DMASTAT_ADDR   (0x4000C02Cu)
#define	SC2_DMASTAT_RESET   (0x00000000u)
#define	SC_RXSSEL   (0x00001C00u)
#define	SC_RXSSEL_MASK   (0x00001C00u)
#define	SC_RXSSEL_BIT   (10)
#define	SC_RXSSEL_BITS   (3)
#define	SC_RXOVFB   (0x00000020u)
#define	SC_RXOVFB_MASK   (0x00000020u)
#define	SC_RXOVFB_BIT   (5)
#define	SC_RXOVFB_BITS   (1)
#define	SC_RXOVFA   (0x00000010u)
#define	SC_RXOVFA_MASK   (0x00000010u)
#define	SC_RXOVFA_BIT   (4)
#define	SC_RXOVFA_BITS   (1)
#define	SC_TXACTB   (0x00000008u)
#define	SC_TXACTB_MASK   (0x00000008u)
#define	SC_TXACTB_BIT   (3)
#define	SC_TXACTB_BITS   (1)
#define	SC_TXACTA   (0x00000004u)
#define	SC_TXACTA_MASK   (0x00000004u)
#define	SC_TXACTA_BIT   (2)
#define	SC_TXACTA_BITS   (1)
#define	SC_RXACTB   (0x00000002u)
#define	SC_RXACTB_MASK   (0x00000002u)
#define	SC_RXACTB_BIT   (1)
#define	SC_RXACTB_BITS   (1)
#define	SC_RXACTA   (0x00000001u)
#define	SC_RXACTA_MASK   (0x00000001u)
#define	SC_RXACTA_BIT   (0)
#define	SC_RXACTA_BITS   (1)
#define	SC2_DMACTRL   *((volatile int32u *)0x4000C030u)
#define	SC2_DMACTRL_REG   *((volatile int32u *)0x4000C030u)
#define	SC2_DMACTRL_ADDR   (0x4000C030u)
#define	SC2_DMACTRL_RESET   (0x00000000u)
#define	SC_TXDMARST   (0x00000020u)
#define	SC_TXDMARST_MASK   (0x00000020u)
#define	SC_TXDMARST_BIT   (5)
#define	SC_TXDMARST_BITS   (1)
#define	SC_RXDMARST   (0x00000010u)
#define	SC_RXDMARST_MASK   (0x00000010u)
#define	SC_RXDMARST_BIT   (4)
#define	SC_RXDMARST_BITS   (1)
#define	SC_TXLODB   (0x00000008u)
#define	SC_TXLODB_MASK   (0x00000008u)
#define	SC_TXLODB_BIT   (3)
#define	SC_TXLODB_BITS   (1)
#define	SC_TXLODA   (0x00000004u)
#define	SC_TXLODA_MASK   (0x00000004u)
#define	SC_TXLODA_BIT   (2)
#define	SC_TXLODA_BITS   (1)
#define	SC_RXLODB   (0x00000002u)
#define	SC_RXLODB_MASK   (0x00000002u)
#define	SC_RXLODB_BIT   (1)
#define	SC_RXLODB_BITS   (1)
#define	SC_RXLODA   (0x00000001u)
#define	SC_RXLODA_MASK   (0x00000001u)
#define	SC_RXLODA_BIT   (0)
#define	SC_RXLODA_BITS   (1)
#define	SC2_RXERRA   *((volatile int32u *)0x4000C034u)
#define	SC2_RXERRA_REG   *((volatile int32u *)0x4000C034u)
#define	SC2_RXERRA_ADDR   (0x4000C034u)
#define	SC2_RXERRA_RESET   (0x00000000u)
#define	SC_RXERRA   (0x00001FFFu)
#define	SC_RXERRA_MASK   (0x00001FFFu)
#define	SC_RXERRA_BIT   (0)
#define	SC_RXERRA_BITS   (13)
#define	SC2_RXERRB   *((volatile int32u *)0x4000C038u)
#define	SC2_RXERRB_REG   *((volatile int32u *)0x4000C038u)
#define	SC2_RXERRB_ADDR   (0x4000C038u)
#define	SC2_RXERRB_RESET   (0x00000000u)
#define	SC_RXERRB   (0x00001FFFu)
#define	SC_RXERRB_MASK   (0x00001FFFu)
#define	SC_RXERRB_BIT   (0)
#define	SC_RXERRB_BITS   (13)
#define	SC2_DATA   *((volatile int32u *)0x4000C03Cu)
#define	SC2_DATA_REG   *((volatile int32u *)0x4000C03Cu)
#define	SC2_DATA_ADDR   (0x4000C03Cu)
#define	SC2_DATA_RESET   (0x00000000u)
#define	SC_DATA   (0x000000FFu)
#define	SC_DATA_MASK   (0x000000FFu)
#define	SC_DATA_BIT   (0)
#define	SC_DATA_BITS   (8)
#define	SC2_SPISTAT   *((volatile int32u *)0x4000C040u)
#define	SC2_SPISTAT_REG   *((volatile int32u *)0x4000C040u)
#define	SC2_SPISTAT_ADDR   (0x4000C040u)
#define	SC2_SPISTAT_RESET   (0x00000000u)
#define	SC_SPITXIDLE   (0x00000008u)
#define	SC_SPITXIDLE_MASK   (0x00000008u)
#define	SC_SPITXIDLE_BIT   (3)
#define	SC_SPITXIDLE_BITS   (1)
#define	SC_SPITXFREE   (0x00000004u)
#define	SC_SPITXFREE_MASK   (0x00000004u)
#define	SC_SPITXFREE_BIT   (2)
#define	SC_SPITXFREE_BITS   (1)
#define	SC_SPIRXVAL   (0x00000002u)
#define	SC_SPIRXVAL_MASK   (0x00000002u)
#define	SC_SPIRXVAL_BIT   (1)
#define	SC_SPIRXVAL_BITS   (1)
#define	SC_SPIRXOVF   (0x00000001u)
#define	SC_SPIRXOVF_MASK   (0x00000001u)
#define	SC_SPIRXOVF_BIT   (0)
#define	SC_SPIRXOVF_BITS   (1)
#define	SC2_TWISTAT   *((volatile int32u *)0x4000C044u)
#define	SC2_TWISTAT_REG   *((volatile int32u *)0x4000C044u)
#define	SC2_TWISTAT_ADDR   (0x4000C044u)
#define	SC2_TWISTAT_RESET   (0x00000000u)
#define	SC_TWICMDFIN   (0x00000008u)
#define	SC_TWICMDFIN_MASK   (0x00000008u)
#define	SC_TWICMDFIN_BIT   (3)
#define	SC_TWICMDFIN_BITS   (1)
#define	SC_TWIRXFIN   (0x00000004u)
#define	SC_TWIRXFIN_MASK   (0x00000004u)
#define	SC_TWIRXFIN_BIT   (2)
#define	SC_TWIRXFIN_BITS   (1)
#define	SC_TWITXFIN   (0x00000002u)
#define	SC_TWITXFIN_MASK   (0x00000002u)
#define	SC_TWITXFIN_BIT   (1)
#define	SC_TWITXFIN_BITS   (1)
#define	SC_TWIRXNAK   (0x00000001u)
#define	SC_TWIRXNAK_MASK   (0x00000001u)
#define	SC_TWIRXNAK_BIT   (0)
#define	SC_TWIRXNAK_BITS   (1)
#define	SC2_TWICTRL1   *((volatile int32u *)0x4000C04Cu)
#define	SC2_TWICTRL1_REG   *((volatile int32u *)0x4000C04Cu)
#define	SC2_TWICTRL1_ADDR   (0x4000C04Cu)
#define	SC2_TWICTRL1_RESET   (0x00000000u)
#define	SC_TWISTOP   (0x00000008u)
#define	SC_TWISTOP_MASK   (0x00000008u)
#define	SC_TWISTOP_BIT   (3)
#define	SC_TWISTOP_BITS   (1)
#define	SC_TWISTART   (0x00000004u)
#define	SC_TWISTART_MASK   (0x00000004u)
#define	SC_TWISTART_BIT   (2)
#define	SC_TWISTART_BITS   (1)
#define	SC_TWISEND   (0x00000002u)
#define	SC_TWISEND_MASK   (0x00000002u)
#define	SC_TWISEND_BIT   (1)
#define	SC_TWISEND_BITS   (1)
#define	SC_TWIRECV   (0x00000001u)
#define	SC_TWIRECV_MASK   (0x00000001u)
#define	SC_TWIRECV_BIT   (0)
#define	SC_TWIRECV_BITS   (1)
#define	SC2_TWICTRL2   *((volatile int32u *)0x4000C050u)
#define	SC2_TWICTRL2_REG   *((volatile int32u *)0x4000C050u)
#define	SC2_TWICTRL2_ADDR   (0x4000C050u)
#define	SC2_TWICTRL2_RESET   (0x00000000u)
#define	SC_TWIACK   (0x00000001u)
#define	SC_TWIACK_MASK   (0x00000001u)
#define	SC_TWIACK_BIT   (0)
#define	SC_TWIACK_BITS   (1)
#define	SC2_MODE   *((volatile int32u *)0x4000C054u)
#define	SC2_MODE_REG   *((volatile int32u *)0x4000C054u)
#define	SC2_MODE_ADDR   (0x4000C054u)
#define	SC2_MODE_RESET   (0x00000000u)
#define	SC_MODE   (0x00000003u)
#define	SC_MODE_MASK   (0x00000003u)
#define	SC_MODE_BIT   (0)
#define	SC_MODE_BITS   (2)
#define	SC2_MODE_DISABLED   (0)
#define	SC2_MODE_SPI   (2)
#define	SC2_MODE_I2C   (3)
#define	SC2_SPICFG   *((volatile int32u *)0x4000C058u)
#define	SC2_SPICFG_REG   *((volatile int32u *)0x4000C058u)
#define	SC2_SPICFG_ADDR   (0x4000C058u)
#define	SC2_SPICFG_RESET   (0x00000000u)
#define	SC_SPIRXDRV   (0x00000020u)
#define	SC_SPIRXDRV_MASK   (0x00000020u)
#define	SC_SPIRXDRV_BIT   (5)
#define	SC_SPIRXDRV_BITS   (1)
#define	SC_SPIMST   (0x00000010u)
#define	SC_SPIMST_MASK   (0x00000010u)
#define	SC_SPIMST_BIT   (4)
#define	SC_SPIMST_BITS   (1)
#define	SC_SPIRPT   (0x00000008u)
#define	SC_SPIRPT_MASK   (0x00000008u)
#define	SC_SPIRPT_BIT   (3)
#define	SC_SPIRPT_BITS   (1)
#define	SC_SPIORD   (0x00000004u)
#define	SC_SPIORD_MASK   (0x00000004u)
#define	SC_SPIORD_BIT   (2)
#define	SC_SPIORD_BITS   (1)
#define	SC_SPIPHA   (0x00000002u)
#define	SC_SPIPHA_MASK   (0x00000002u)
#define	SC_SPIPHA_BIT   (1)
#define	SC_SPIPHA_BITS   (1)
#define	SC_SPIPOL   (0x00000001u)
#define	SC_SPIPOL_MASK   (0x00000001u)
#define	SC_SPIPOL_BIT   (0)
#define	SC_SPIPOL_BITS   (1)
#define	SC2_RATELIN   *((volatile int32u *)0x4000C060u)
#define	SC2_RATELIN_REG   *((volatile int32u *)0x4000C060u)
#define	SC2_RATELIN_ADDR   (0x4000C060u)
#define	SC2_RATELIN_RESET   (0x00000000u)
#define	SC_RATELIN   (0x0000000Fu)
#define	SC_RATELIN_MASK   (0x0000000Fu)
#define	SC_RATELIN_BIT   (0)
#define	SC_RATELIN_BITS   (4)
#define	SC2_RATEEXP   *((volatile int32u *)0x4000C064u)
#define	SC2_RATEEXP_REG   *((volatile int32u *)0x4000C064u)
#define	SC2_RATEEXP_ADDR   (0x4000C064u)
#define	SC2_RATEEXP_RESET   (0x00000000u)
#define	SC_RATEEXP   (0x0000000Fu)
#define	SC_RATEEXP_MASK   (0x0000000Fu)
#define	SC_RATEEXP_BIT   (0)
#define	SC_RATEEXP_BITS   (4)
#define	SC2_RXCNTSAVED   *((volatile int32u *)0x4000C070u)
#define	SC2_RXCNTSAVED_REG   *((volatile int32u *)0x4000C070u)
#define	SC2_RXCNTSAVED_ADDR   (0x4000C070u)
#define	SC2_RXCNTSAVED_RESET   (0x00000000u)
#define	SC_RXCNTSAVED   (0x00001FFFu)
#define	SC_RXCNTSAVED_MASK   (0x00001FFFu)
#define	SC_RXCNTSAVED_BIT   (0)
#define	SC_RXCNTSAVED_BITS   (13)
#define	SC1_RXBEGA   *((volatile int32u *)0x4000C800u)
#define	SC1_RXBEGA_REG   *((volatile int32u *)0x4000C800u)
#define	SC1_RXBEGA_ADDR   (0x4000C800u)
#define	SC1_RXBEGA_RESET   (0x20000000u)
#define	SC1_RXBEGA_FIXED   (0xFFFFE000u)
#define	SC1_RXBEGA_FIXED_MASK   (0xFFFFE000u)
#define	SC1_RXBEGA_FIXED_BIT   (13)
#define	SC1_RXBEGA_FIXED_BITS   (19)
#define	SC_RXBEGA   (0x00001FFFu)
#define	SC_RXBEGA_MASK   (0x00001FFFu)
#define	SC_RXBEGA_BIT   (0)
#define	SC_RXBEGA_BITS   (13)
#define	SC1_RXENDA   *((volatile int32u *)0x4000C804u)
#define	SC1_RXENDA_REG   *((volatile int32u *)0x4000C804u)
#define	SC1_RXENDA_ADDR   (0x4000C804u)
#define	SC1_RXENDA_RESET   (0x20000000u)
#define	SC1_RXENDA_FIXED   (0xFFFFE000u)
#define	SC1_RXENDA_FIXED_MASK   (0xFFFFE000u)
#define	SC1_RXENDA_FIXED_BIT   (13)
#define	SC1_RXENDA_FIXED_BITS   (19)
#define	SC_RXENDA   (0x00001FFFu)
#define	SC_RXENDA_MASK   (0x00001FFFu)
#define	SC_RXENDA_BIT   (0)
#define	SC_RXENDA_BITS   (13)
#define	SC1_RXBEGB   *((volatile int32u *)0x4000C808u)
#define	SC1_RXBEGB_REG   *((volatile int32u *)0x4000C808u)
#define	SC1_RXBEGB_ADDR   (0x4000C808u)
#define	SC1_RXBEGB_RESET   (0x20000000u)
#define	SC1_RXBEGB_FIXED   (0xFFFFE000u)
#define	SC1_RXBEGB_FIXED_MASK   (0xFFFFE000u)
#define	SC1_RXBEGB_FIXED_BIT   (13)
#define	SC1_RXBEGB_FIXED_BITS   (19)
#define	SC_RXBEGB   (0x00001FFFu)
#define	SC_RXBEGB_MASK   (0x00001FFFu)
#define	SC_RXBEGB_BIT   (0)
#define	SC_RXBEGB_BITS   (13)
#define	SC1_RXENDB   *((volatile int32u *)0x4000C80Cu)
#define	SC1_RXENDB_REG   *((volatile int32u *)0x4000C80Cu)
#define	SC1_RXENDB_ADDR   (0x4000C80Cu)
#define	SC1_RXENDB_RESET   (0x20000000u)
#define	SC1_RXENDB_FIXED   (0xFFFFE000u)
#define	SC1_RXENDB_FIXED_MASK   (0xFFFFE000u)
#define	SC1_RXENDB_FIXED_BIT   (13)
#define	SC1_RXENDB_FIXED_BITS   (19)
#define	SC_RXENDB   (0x00001FFFu)
#define	SC_RXENDB_MASK   (0x00001FFFu)
#define	SC_RXENDB_BIT   (0)
#define	SC_RXENDB_BITS   (13)
#define	SC1_TXBEGA   *((volatile int32u *)0x4000C810u)
#define	SC1_TXBEGA_REG   *((volatile int32u *)0x4000C810u)
#define	SC1_TXBEGA_ADDR   (0x4000C810u)
#define	SC1_TXBEGA_RESET   (0x20000000u)
#define	SC1_TXBEGA_FIXED   (0xFFFFE000u)
#define	SC1_TXBEGA_FIXED_MASK   (0xFFFFE000u)
#define	SC1_TXBEGA_FIXED_BIT   (13)
#define	SC1_TXBEGA_FIXED_BITS   (19)
#define	SC_TXBEGA   (0x00001FFFu)
#define	SC_TXBEGA_MASK   (0x00001FFFu)
#define	SC_TXBEGA_BIT   (0)
#define	SC_TXBEGA_BITS   (13)
#define	SC1_TXENDA   *((volatile int32u *)0x4000C814u)
#define	SC1_TXENDA_REG   *((volatile int32u *)0x4000C814u)
#define	SC1_TXENDA_ADDR   (0x4000C814u)
#define	SC1_TXENDA_RESET   (0x20000000u)
#define	SC1_TXENDA_FIXED   (0xFFFFE000u)
#define	SC1_TXENDA_FIXED_MASK   (0xFFFFE000u)
#define	SC1_TXENDA_FIXED_BIT   (13)
#define	SC1_TXENDA_FIXED_BITS   (19)
#define	SC_TXENDA   (0x00001FFFu)
#define	SC_TXENDA_MASK   (0x00001FFFu)
#define	SC_TXENDA_BIT   (0)
#define	SC_TXENDA_BITS   (13)
#define	SC1_TXBEGB   *((volatile int32u *)0x4000C818u)
#define	SC1_TXBEGB_REG   *((volatile int32u *)0x4000C818u)
#define	SC1_TXBEGB_ADDR   (0x4000C818u)
#define	SC1_TXBEGB_RESET   (0x20000000u)
#define	SC1_TXBEGB_FIXED   (0xFFFFE000u)
#define	SC1_TXBEGB_FIXED_MASK   (0xFFFFE000u)
#define	SC1_TXBEGB_FIXED_BIT   (13)
#define	SC1_TXBEGB_FIXED_BITS   (19)
#define	SC_TXBEGB   (0x00001FFFu)
#define	SC_TXBEGB_MASK   (0x00001FFFu)
#define	SC_TXBEGB_BIT   (0)
#define	SC_TXBEGB_BITS   (13)
#define	SC1_TXENDB   *((volatile int32u *)0x4000C81Cu)
#define	SC1_TXENDB_REG   *((volatile int32u *)0x4000C81Cu)
#define	SC1_TXENDB_ADDR   (0x4000C81Cu)
#define	SC1_TXENDB_RESET   (0x20000000u)
#define	SC1_TXENDB_FIXED   (0xFFFFE000u)
#define	SC1_TXENDB_FIXED_MASK   (0xFFFFE000u)
#define	SC1_TXENDB_FIXED_BIT   (13)
#define	SC1_TXENDB_FIXED_BITS   (19)
#define	SC_TXENDB   (0x00001FFFu)
#define	SC_TXENDB_MASK   (0x00001FFFu)
#define	SC_TXENDB_BIT   (0)
#define	SC_TXENDB_BITS   (13)
#define	SC1_RXCNTA   *((volatile int32u *)0x4000C820u)
#define	SC1_RXCNTA_REG   *((volatile int32u *)0x4000C820u)
#define	SC1_RXCNTA_ADDR   (0x4000C820u)
#define	SC1_RXCNTA_RESET   (0x00000000u)
#define	SC_RXCNTA   (0x00001FFFu)
#define	SC_RXCNTA_MASK   (0x00001FFFu)
#define	SC_RXCNTA_BIT   (0)
#define	SC_RXCNTA_BITS   (13)
#define	SC1_RXCNTB   *((volatile int32u *)0x4000C824u)
#define	SC1_RXCNTB_REG   *((volatile int32u *)0x4000C824u)
#define	SC1_RXCNTB_ADDR   (0x4000C824u)
#define	SC1_RXCNTB_RESET   (0x00000000u)
#define	SC_RXCNTB   (0x00001FFFu)
#define	SC_RXCNTB_MASK   (0x00001FFFu)
#define	SC_RXCNTB_BIT   (0)
#define	SC_RXCNTB_BITS   (13)
#define	SC1_TXCNT   *((volatile int32u *)0x4000C828u)
#define	SC1_TXCNT_REG   *((volatile int32u *)0x4000C828u)
#define	SC1_TXCNT_ADDR   (0x4000C828u)
#define	SC1_TXCNT_RESET   (0x00000000u)
#define	SC_TXCNT   (0x00001FFFu)
#define	SC_TXCNT_MASK   (0x00001FFFu)
#define	SC_TXCNT_BIT   (0)
#define	SC_TXCNT_BITS   (13)
#define	SC1_DMASTAT   *((volatile int32u *)0x4000C82Cu)
#define	SC1_DMASTAT_REG   *((volatile int32u *)0x4000C82Cu)
#define	SC1_DMASTAT_ADDR   (0x4000C82Cu)
#define	SC1_DMASTAT_RESET   (0x00000000u)
#define	SC_RXSSEL   (0x00001C00u)
#define	SC_RXSSEL_MASK   (0x00001C00u)
#define	SC_RXSSEL_BIT   (10)
#define	SC_RXSSEL_BITS   (3)
#define	SC_RXFRMB   (0x00000200u)
#define	SC_RXFRMB_MASK   (0x00000200u)
#define	SC_RXFRMB_BIT   (9)
#define	SC_RXFRMB_BITS   (1)
#define	SC_RXFRMA   (0x00000100u)
#define	SC_RXFRMA_MASK   (0x00000100u)
#define	SC_RXFRMA_BIT   (8)
#define	SC_RXFRMA_BITS   (1)
#define	SC_RXPARB   (0x00000080u)
#define	SC_RXPARB_MASK   (0x00000080u)
#define	SC_RXPARB_BIT   (7)
#define	SC_RXPARB_BITS   (1)
#define	SC_RXPARA   (0x00000040u)
#define	SC_RXPARA_MASK   (0x00000040u)
#define	SC_RXPARA_BIT   (6)
#define	SC_RXPARA_BITS   (1)
#define	SC_RXOVFB   (0x00000020u)
#define	SC_RXOVFB_MASK   (0x00000020u)
#define	SC_RXOVFB_BIT   (5)
#define	SC_RXOVFB_BITS   (1)
#define	SC_RXOVFA   (0x00000010u)
#define	SC_RXOVFA_MASK   (0x00000010u)
#define	SC_RXOVFA_BIT   (4)
#define	SC_RXOVFA_BITS   (1)
#define	SC_TXACTB   (0x00000008u)
#define	SC_TXACTB_MASK   (0x00000008u)
#define	SC_TXACTB_BIT   (3)
#define	SC_TXACTB_BITS   (1)
#define	SC_TXACTA   (0x00000004u)
#define	SC_TXACTA_MASK   (0x00000004u)
#define	SC_TXACTA_BIT   (2)
#define	SC_TXACTA_BITS   (1)
#define	SC_RXACTB   (0x00000002u)
#define	SC_RXACTB_MASK   (0x00000002u)
#define	SC_RXACTB_BIT   (1)
#define	SC_RXACTB_BITS   (1)
#define	SC_RXACTA   (0x00000001u)
#define	SC_RXACTA_MASK   (0x00000001u)
#define	SC_RXACTA_BIT   (0)
#define	SC_RXACTA_BITS   (1)
#define	SC1_DMACTRL   *((volatile int32u *)0x4000C830u)
#define	SC1_DMACTRL_REG   *((volatile int32u *)0x4000C830u)
#define	SC1_DMACTRL_ADDR   (0x4000C830u)
#define	SC1_DMACTRL_RESET   (0x00000000u)
#define	SC_TXDMARST   (0x00000020u)
#define	SC_TXDMARST_MASK   (0x00000020u)
#define	SC_TXDMARST_BIT   (5)
#define	SC_TXDMARST_BITS   (1)
#define	SC_RXDMARST   (0x00000010u)
#define	SC_RXDMARST_MASK   (0x00000010u)
#define	SC_RXDMARST_BIT   (4)
#define	SC_RXDMARST_BITS   (1)
#define	SC_TXLODB   (0x00000008u)
#define	SC_TXLODB_MASK   (0x00000008u)
#define	SC_TXLODB_BIT   (3)
#define	SC_TXLODB_BITS   (1)
#define	SC_TXLODA   (0x00000004u)
#define	SC_TXLODA_MASK   (0x00000004u)
#define	SC_TXLODA_BIT   (2)
#define	SC_TXLODA_BITS   (1)
#define	SC_RXLODB   (0x00000002u)
#define	SC_RXLODB_MASK   (0x00000002u)
#define	SC_RXLODB_BIT   (1)
#define	SC_RXLODB_BITS   (1)
#define	SC_RXLODA   (0x00000001u)
#define	SC_RXLODA_MASK   (0x00000001u)
#define	SC_RXLODA_BIT   (0)
#define	SC_RXLODA_BITS   (1)
#define	SC1_RXERRA   *((volatile int32u *)0x4000C834u)
#define	SC1_RXERRA_REG   *((volatile int32u *)0x4000C834u)
#define	SC1_RXERRA_ADDR   (0x4000C834u)
#define	SC1_RXERRA_RESET   (0x00000000u)
#define	SC_RXERRA   (0x00001FFFu)
#define	SC_RXERRA_MASK   (0x00001FFFu)
#define	SC_RXERRA_BIT   (0)
#define	SC_RXERRA_BITS   (13)
#define	SC1_RXERRB   *((volatile int32u *)0x4000C838u)
#define	SC1_RXERRB_REG   *((volatile int32u *)0x4000C838u)
#define	SC1_RXERRB_ADDR   (0x4000C838u)
#define	SC1_RXERRB_RESET   (0x00000000u)
#define	SC_RXERRB   (0x00001FFFu)
#define	SC_RXERRB_MASK   (0x00001FFFu)
#define	SC_RXERRB_BIT   (0)
#define	SC_RXERRB_BITS   (13)
#define	SC1_DATA   *((volatile int32u *)0x4000C83Cu)
#define	SC1_DATA_REG   *((volatile int32u *)0x4000C83Cu)
#define	SC1_DATA_ADDR   (0x4000C83Cu)
#define	SC1_DATA_RESET   (0x00000000u)
#define	SC_DATA   (0x000000FFu)
#define	SC_DATA_MASK   (0x000000FFu)
#define	SC_DATA_BIT   (0)
#define	SC_DATA_BITS   (8)
#define	SC1_SPISTAT   *((volatile int32u *)0x4000C840u)
#define	SC1_SPISTAT_REG   *((volatile int32u *)0x4000C840u)
#define	SC1_SPISTAT_ADDR   (0x4000C840u)
#define	SC1_SPISTAT_RESET   (0x00000000u)
#define	SC_SPITXIDLE   (0x00000008u)
#define	SC_SPITXIDLE_MASK   (0x00000008u)
#define	SC_SPITXIDLE_BIT   (3)
#define	SC_SPITXIDLE_BITS   (1)
#define	SC_SPITXFREE   (0x00000004u)
#define	SC_SPITXFREE_MASK   (0x00000004u)
#define	SC_SPITXFREE_BIT   (2)
#define	SC_SPITXFREE_BITS   (1)
#define	SC_SPIRXVAL   (0x00000002u)
#define	SC_SPIRXVAL_MASK   (0x00000002u)
#define	SC_SPIRXVAL_BIT   (1)
#define	SC_SPIRXVAL_BITS   (1)
#define	SC_SPIRXOVF   (0x00000001u)
#define	SC_SPIRXOVF_MASK   (0x00000001u)
#define	SC_SPIRXOVF_BIT   (0)
#define	SC_SPIRXOVF_BITS   (1)
#define	SC1_TWISTAT   *((volatile int32u *)0x4000C844u)
#define	SC1_TWISTAT_REG   *((volatile int32u *)0x4000C844u)
#define	SC1_TWISTAT_ADDR   (0x4000C844u)
#define	SC1_TWISTAT_RESET   (0x00000000u)
#define	SC_TWICMDFIN   (0x00000008u)
#define	SC_TWICMDFIN_MASK   (0x00000008u)
#define	SC_TWICMDFIN_BIT   (3)
#define	SC_TWICMDFIN_BITS   (1)
#define	SC_TWIRXFIN   (0x00000004u)
#define	SC_TWIRXFIN_MASK   (0x00000004u)
#define	SC_TWIRXFIN_BIT   (2)
#define	SC_TWIRXFIN_BITS   (1)
#define	SC_TWITXFIN   (0x00000002u)
#define	SC_TWITXFIN_MASK   (0x00000002u)
#define	SC_TWITXFIN_BIT   (1)
#define	SC_TWITXFIN_BITS   (1)
#define	SC_TWIRXNAK   (0x00000001u)
#define	SC_TWIRXNAK_MASK   (0x00000001u)
#define	SC_TWIRXNAK_BIT   (0)
#define	SC_TWIRXNAK_BITS   (1)
#define	SC1_UARTSTAT   *((volatile int32u *)0x4000C848u)
#define	SC1_UARTSTAT_REG   *((volatile int32u *)0x4000C848u)
#define	SC1_UARTSTAT_ADDR   (0x4000C848u)
#define	SC1_UARTSTAT_RESET   (0x00000040u)
#define	SC_UARTTXIDLE   (0x00000040u)
#define	SC_UARTTXIDLE_MASK   (0x00000040u)
#define	SC_UARTTXIDLE_BIT   (6)
#define	SC_UARTTXIDLE_BITS   (1)
#define	SC_UARTPARERR   (0x00000020u)
#define	SC_UARTPARERR_MASK   (0x00000020u)
#define	SC_UARTPARERR_BIT   (5)
#define	SC_UARTPARERR_BITS   (1)
#define	SC_UARTFRMERR   (0x00000010u)
#define	SC_UARTFRMERR_MASK   (0x00000010u)
#define	SC_UARTFRMERR_BIT   (4)
#define	SC_UARTFRMERR_BITS   (1)
#define	SC_UARTRXOVF   (0x00000008u)
#define	SC_UARTRXOVF_MASK   (0x00000008u)
#define	SC_UARTRXOVF_BIT   (3)
#define	SC_UARTRXOVF_BITS   (1)
#define	SC_UARTTXFREE   (0x00000004u)
#define	SC_UARTTXFREE_MASK   (0x00000004u)
#define	SC_UARTTXFREE_BIT   (2)
#define	SC_UARTTXFREE_BITS   (1)
#define	SC_UARTRXVAL   (0x00000002u)
#define	SC_UARTRXVAL_MASK   (0x00000002u)
#define	SC_UARTRXVAL_BIT   (1)
#define	SC_UARTRXVAL_BITS   (1)
#define	SC_UARTCTS   (0x00000001u)
#define	SC_UARTCTS_MASK   (0x00000001u)
#define	SC_UARTCTS_BIT   (0)
#define	SC_UARTCTS_BITS   (1)
#define	SC1_TWICTRL1   *((volatile int32u *)0x4000C84Cu)
#define	SC1_TWICTRL1_REG   *((volatile int32u *)0x4000C84Cu)
#define	SC1_TWICTRL1_ADDR   (0x4000C84Cu)
#define	SC1_TWICTRL1_RESET   (0x00000000u)
#define	SC_TWISTOP   (0x00000008u)
#define	SC_TWISTOP_MASK   (0x00000008u)
#define	SC_TWISTOP_BIT   (3)
#define	SC_TWISTOP_BITS   (1)
#define	SC_TWISTART   (0x00000004u)
#define	SC_TWISTART_MASK   (0x00000004u)
#define	SC_TWISTART_BIT   (2)
#define	SC_TWISTART_BITS   (1)
#define	SC_TWISEND   (0x00000002u)
#define	SC_TWISEND_MASK   (0x00000002u)
#define	SC_TWISEND_BIT   (1)
#define	SC_TWISEND_BITS   (1)
#define	SC_TWIRECV   (0x00000001u)
#define	SC_TWIRECV_MASK   (0x00000001u)
#define	SC_TWIRECV_BIT   (0)
#define	SC_TWIRECV_BITS   (1)
#define	SC1_TWICTRL2   *((volatile int32u *)0x4000C850u)
#define	SC1_TWICTRL2_REG   *((volatile int32u *)0x4000C850u)
#define	SC1_TWICTRL2_ADDR   (0x4000C850u)
#define	SC1_TWICTRL2_RESET   (0x00000000u)
#define	SC_TWIACK   (0x00000001u)
#define	SC_TWIACK_MASK   (0x00000001u)
#define	SC_TWIACK_BIT   (0)
#define	SC_TWIACK_BITS   (1)
#define	SC1_MODE   *((volatile int32u *)0x4000C854u)
#define	SC1_MODE_REG   *((volatile int32u *)0x4000C854u)
#define	SC1_MODE_ADDR   (0x4000C854u)
#define	SC1_MODE_RESET   (0x00000000u)
#define	SC_MODE   (0x00000003u)
#define	SC_MODE_MASK   (0x00000003u)
#define	SC_MODE_BIT   (0)
#define	SC_MODE_BITS   (2)
#define	SC1_MODE_DISABLED   (0)
#define	SC1_MODE_UART   (1)
#define	SC1_MODE_SPI   (2)
#define	SC1_MODE_I2C   (3)
#define	SC1_SPICFG   *((volatile int32u *)0x4000C858u)
#define	SC1_SPICFG_REG   *((volatile int32u *)0x4000C858u)
#define	SC1_SPICFG_ADDR   (0x4000C858u)
#define	SC1_SPICFG_RESET   (0x00000000u)
#define	SC_SPIRXDRV   (0x00000020u)
#define	SC_SPIRXDRV_MASK   (0x00000020u)
#define	SC_SPIRXDRV_BIT   (5)
#define	SC_SPIRXDRV_BITS   (1)
#define	SC_SPIMST   (0x00000010u)
#define	SC_SPIMST_MASK   (0x00000010u)
#define	SC_SPIMST_BIT   (4)
#define	SC_SPIMST_BITS   (1)
#define	SC_SPIRPT   (0x00000008u)
#define	SC_SPIRPT_MASK   (0x00000008u)
#define	SC_SPIRPT_BIT   (3)
#define	SC_SPIRPT_BITS   (1)
#define	SC_SPIORD   (0x00000004u)
#define	SC_SPIORD_MASK   (0x00000004u)
#define	SC_SPIORD_BIT   (2)
#define	SC_SPIORD_BITS   (1)
#define	SC_SPIPHA   (0x00000002u)
#define	SC_SPIPHA_MASK   (0x00000002u)
#define	SC_SPIPHA_BIT   (1)
#define	SC_SPIPHA_BITS   (1)
#define	SC_SPIPOL   (0x00000001u)
#define	SC_SPIPOL_MASK   (0x00000001u)
#define	SC_SPIPOL_BIT   (0)
#define	SC_SPIPOL_BITS   (1)
#define	SC1_UARTCFG   *((volatile int32u *)0x4000C85Cu)
#define	SC1_UARTCFG_REG   *((volatile int32u *)0x4000C85Cu)
#define	SC1_UARTCFG_ADDR   (0x4000C85Cu)
#define	SC1_UARTCFG_RESET   (0x00000000u)
#define	SC_UARTAUTO   (0x00000040u)
#define	SC_UARTAUTO_MASK   (0x00000040u)
#define	SC_UARTAUTO_BIT   (6)
#define	SC_UARTAUTO_BITS   (1)
#define	SC_UARTFLOW   (0x00000020u)
#define	SC_UARTFLOW_MASK   (0x00000020u)
#define	SC_UARTFLOW_BIT   (5)
#define	SC_UARTFLOW_BITS   (1)
#define	SC_UARTODD   (0x00000010u)
#define	SC_UARTODD_MASK   (0x00000010u)
#define	SC_UARTODD_BIT   (4)
#define	SC_UARTODD_BITS   (1)
#define	SC_UARTPAR   (0x00000008u)
#define	SC_UARTPAR_MASK   (0x00000008u)
#define	SC_UARTPAR_BIT   (3)
#define	SC_UARTPAR_BITS   (1)
#define	SC_UART2STP   (0x00000004u)
#define	SC_UART2STP_MASK   (0x00000004u)
#define	SC_UART2STP_BIT   (2)
#define	SC_UART2STP_BITS   (1)
#define	SC_UART8BIT   (0x00000002u)
#define	SC_UART8BIT_MASK   (0x00000002u)
#define	SC_UART8BIT_BIT   (1)
#define	SC_UART8BIT_BITS   (1)
#define	SC_UARTRTS   (0x00000001u)
#define	SC_UARTRTS_MASK   (0x00000001u)
#define	SC_UARTRTS_BIT   (0)
#define	SC_UARTRTS_BITS   (1)
#define	SC1_RATELIN   *((volatile int32u *)0x4000C860u)
#define	SC1_RATELIN_REG   *((volatile int32u *)0x4000C860u)
#define	SC1_RATELIN_ADDR   (0x4000C860u)
#define	SC1_RATELIN_RESET   (0x00000000u)
#define	SC_RATELIN   (0x0000000Fu)
#define	SC_RATELIN_MASK   (0x0000000Fu)
#define	SC_RATELIN_BIT   (0)
#define	SC_RATELIN_BITS   (4)
#define	SC1_RATEEXP   *((volatile int32u *)0x4000C864u)
#define	SC1_RATEEXP_REG   *((volatile int32u *)0x4000C864u)
#define	SC1_RATEEXP_ADDR   (0x4000C864u)
#define	SC1_RATEEXP_RESET   (0x00000000u)
#define	SC_RATEEXP   (0x0000000Fu)
#define	SC_RATEEXP_MASK   (0x0000000Fu)
#define	SC_RATEEXP_BIT   (0)
#define	SC_RATEEXP_BITS   (4)
#define	SC1_UARTPER   *((volatile int32u *)0x4000C868u)
#define	SC1_UARTPER_REG   *((volatile int32u *)0x4000C868u)
#define	SC1_UARTPER_ADDR   (0x4000C868u)
#define	SC1_UARTPER_RESET   (0x00000000u)
#define	SC_UARTPER   (0x0000FFFFu)
#define	SC_UARTPER_MASK   (0x0000FFFFu)
#define	SC_UARTPER_BIT   (0)
#define	SC_UARTPER_BITS   (16)
#define	SC1_UARTFRAC   *((volatile int32u *)0x4000C86Cu)
#define	SC1_UARTFRAC_REG   *((volatile int32u *)0x4000C86Cu)
#define	SC1_UARTFRAC_ADDR   (0x4000C86Cu)
#define	SC1_UARTFRAC_RESET   (0x00000000u)
#define	SC_UARTFRAC   (0x00000001u)
#define	SC_UARTFRAC_MASK   (0x00000001u)
#define	SC_UARTFRAC_BIT   (0)
#define	SC_UARTFRAC_BITS   (1)
#define	SC1_RXCNTSAVED   *((volatile int32u *)0x4000C870u)
#define	SC1_RXCNTSAVED_REG   *((volatile int32u *)0x4000C870u)
#define	SC1_RXCNTSAVED_ADDR   (0x4000C870u)
#define	SC1_RXCNTSAVED_RESET   (0x00000000u)
#define	SC_RXCNTSAVED   (0x00001FFFu)
#define	SC_RXCNTSAVED_MASK   (0x00001FFFu)
#define	SC_RXCNTSAVED_BIT   (0)
#define	SC_RXCNTSAVED_BITS   (13)
#define	BLOCK_ADC_BASE   (0x4000D000u)
#define	BLOCK_ADC_END   (0x4000D024u)
#define	BLOCK_ADC_SIZE   (BLOCK_ADC_END - BLOCK_ADC_BASE + 1)
#define	ADC_DATA   *((volatile int32u *)0x4000D000u)
#define	ADC_DATA_REG   *((volatile int32u *)0x4000D000u)
#define	ADC_DATA_ADDR   (0x4000D000u)
#define	ADC_DATA_RESET   (0x00000000u)
#define	ADC_DATA_FIELD   (0x0000FFFFu)
#define	ADC_DATA_FIELD_MASK   (0x0000FFFFu)
#define	ADC_DATA_FIELD_BIT   (0)
#define	ADC_DATA_FIELD_BITS   (16)
#define	ADC_CFG   *((volatile int32u *)0x4000D004u)
#define	ADC_CFG_REG   *((volatile int32u *)0x4000D004u)
#define	ADC_CFG_ADDR   (0x4000D004u)
#define	ADC_CFG_RESET   (0x00001800u)
#define	ADC_PERIOD   (0x0000E000u)
#define	ADC_PERIOD_MASK   (0x0000E000u)
#define	ADC_PERIOD_BIT   (13)
#define	ADC_PERIOD_BITS   (3)
#define	ADC_HVSELP   (0x00001000u)
#define	ADC_HVSELP_MASK   (0x00001000u)
#define	ADC_HVSELP_BIT   (12)
#define	ADC_HVSELP_BITS   (1)
#define	ADC_HVSELN   (0x00000800u)
#define	ADC_HVSELN_MASK   (0x00000800u)
#define	ADC_HVSELN_BIT   (11)
#define	ADC_HVSELN_BITS   (1)
#define	ADC_MUXP   (0x00000780u)
#define	ADC_MUXP_MASK   (0x00000780u)
#define	ADC_MUXP_BIT   (7)
#define	ADC_MUXP_BITS   (4)
#define	ADC_MUXN   (0x00000078u)
#define	ADC_MUXN_MASK   (0x00000078u)
#define	ADC_MUXN_BIT   (3)
#define	ADC_MUXN_BITS   (4)
#define	ADC_1MHZCLK   (0x00000004u)
#define	ADC_1MHZCLK_MASK   (0x00000004u)
#define	ADC_1MHZCLK_BIT   (2)
#define	ADC_1MHZCLK_BITS   (1)
#define	ADC_CFGRSVD   (0x00000002u)
#define	ADC_CFGRSVD_MASK   (0x00000002u)
#define	ADC_CFGRSVD_BIT   (1)
#define	ADC_CFGRSVD_BITS   (1)
#define	ADC_ENABLE   (0x00000001u)
#define	ADC_ENABLE_MASK   (0x00000001u)
#define	ADC_ENABLE_BIT   (0)
#define	ADC_ENABLE_BITS   (1)
#define	ADC_OFFSET   *((volatile int32u *)0x4000D008u)
#define	ADC_OFFSET_REG   *((volatile int32u *)0x4000D008u)
#define	ADC_OFFSET_ADDR   (0x4000D008u)
#define	ADC_OFFSET_RESET   (0x00000000u)
#define	ADC_OFFSET_FIELD   (0x0000FFFFu)
#define	ADC_OFFSET_FIELD_MASK   (0x0000FFFFu)
#define	ADC_OFFSET_FIELD_BIT   (0)
#define	ADC_OFFSET_FIELD_BITS   (16)
#define	ADC_GAIN   *((volatile int32u *)0x4000D00Cu)
#define	ADC_GAIN_REG   *((volatile int32u *)0x4000D00Cu)
#define	ADC_GAIN_ADDR   (0x4000D00Cu)
#define	ADC_GAIN_RESET   (0x00008000u)
#define	ADC_GAIN_FIELD   (0x0000FFFFu)
#define	ADC_GAIN_FIELD_MASK   (0x0000FFFFu)
#define	ADC_GAIN_FIELD_BIT   (0)
#define	ADC_GAIN_FIELD_BITS   (16)
#define	ADC_DMACFG   *((volatile int32u *)0x4000D010u)
#define	ADC_DMACFG_REG   *((volatile int32u *)0x4000D010u)
#define	ADC_DMACFG_ADDR   (0x4000D010u)
#define	ADC_DMACFG_RESET   (0x00000000u)
#define	ADC_DMARST   (0x00000010u)
#define	ADC_DMARST_MASK   (0x00000010u)
#define	ADC_DMARST_BIT   (4)
#define	ADC_DMARST_BITS   (1)
#define	ADC_DMAAUTOWRAP   (0x00000002u)
#define	ADC_DMAAUTOWRAP_MASK   (0x00000002u)
#define	ADC_DMAAUTOWRAP_BIT   (1)
#define	ADC_DMAAUTOWRAP_BITS   (1)
#define	ADC_DMALOAD   (0x00000001u)
#define	ADC_DMALOAD_MASK   (0x00000001u)
#define	ADC_DMALOAD_BIT   (0)
#define	ADC_DMALOAD_BITS   (1)
#define	ADC_DMASTAT   *((volatile int32u *)0x4000D014u)
#define	ADC_DMASTAT_REG   *((volatile int32u *)0x4000D014u)
#define	ADC_DMASTAT_ADDR   (0x4000D014u)
#define	ADC_DMASTAT_RESET   (0x00000000u)
#define	ADC_DMAOVF   (0x00000002u)
#define	ADC_DMAOVF_MASK   (0x00000002u)
#define	ADC_DMAOVF_BIT   (1)
#define	ADC_DMAOVF_BITS   (1)
#define	ADC_DMAACT   (0x00000001u)
#define	ADC_DMAACT_MASK   (0x00000001u)
#define	ADC_DMAACT_BIT   (0)
#define	ADC_DMAACT_BITS   (1)
#define	ADC_DMABEG   *((volatile int32u *)0x4000D018u)
#define	ADC_DMABEG_REG   *((volatile int32u *)0x4000D018u)
#define	ADC_DMABEG_ADDR   (0x4000D018u)
#define	ADC_DMABEG_RESET   (0x20000000u)
#define	ADC_DMABEG_FIXED   (0xFFFFE000u)
#define	ADC_DMABEG_FIXED_MASK   (0xFFFFE000u)
#define	ADC_DMABEG_FIXED_BIT   (13)
#define	ADC_DMABEG_FIXED_BITS   (19)
#define	ADC_DMABEG_FIELD   (0x00001FFFu)
#define	ADC_DMABEG_FIELD_MASK   (0x00001FFFu)
#define	ADC_DMABEG_FIELD_BIT   (0)
#define	ADC_DMABEG_FIELD_BITS   (13)
#define	ADC_DMASIZE   *((volatile int32u *)0x4000D01Cu)
#define	ADC_DMASIZE_REG   *((volatile int32u *)0x4000D01Cu)
#define	ADC_DMASIZE_ADDR   (0x4000D01Cu)
#define	ADC_DMASIZE_RESET   (0x00000000u)
#define	ADC_DMASIZE_FIELD   (0x00000FFFu)
#define	ADC_DMASIZE_FIELD_MASK   (0x00000FFFu)
#define	ADC_DMASIZE_FIELD_BIT   (0)
#define	ADC_DMASIZE_FIELD_BITS   (12)
#define	ADC_DMACUR   *((volatile int32u *)0x4000D020u)
#define	ADC_DMACUR_REG   *((volatile int32u *)0x4000D020u)
#define	ADC_DMACUR_ADDR   (0x4000D020u)
#define	ADC_DMACUR_RESET   (0x20000000u)
#define	ADC_DMACUR_FIXED   (0xFFFFE000u)
#define	ADC_DMACUR_FIXED_MASK   (0xFFFFE000u)
#define	ADC_DMACUR_FIXED_BIT   (13)
#define	ADC_DMACUR_FIXED_BITS   (19)
#define	ADC_DMACUR_FIELD   (0x00001FFFu)
#define	ADC_DMACUR_FIELD_MASK   (0x00001FFFu)
#define	ADC_DMACUR_FIELD_BIT   (0)
#define	ADC_DMACUR_FIELD_BITS   (13)
#define	ADC_DMACNT   *((volatile int32u *)0x4000D024u)
#define	ADC_DMACNT_REG   *((volatile int32u *)0x4000D024u)
#define	ADC_DMACNT_ADDR   (0x4000D024u)
#define	ADC_DMACNT_RESET   (0x00000000u)
#define	ADC_DMACNT_FIELD   (0x00000FFFu)
#define	ADC_DMACNT_FIELD_MASK   (0x00000FFFu)
#define	ADC_DMACNT_FIELD_BIT   (0)
#define	ADC_DMACNT_FIELD_BITS   (12)
#define	BLOCK_TIM1_BASE   (0x4000E000u)
#define	BLOCK_TIM1_END   (0x4000E050u)
#define	BLOCK_TIM1_SIZE   (BLOCK_TIM1_END - BLOCK_TIM1_BASE + 1)
#define	TIM1_CR1   *((volatile int32u *)0x4000E000u)
#define	TIM1_CR1_REG   *((volatile int32u *)0x4000E000u)
#define	TIM1_CR1_ADDR   (0x4000E000u)
#define	TIM1_CR1_RESET   (0x00000000u)
#define	TIM_ARBE   (0x00000080u)
#define	TIM_ARBE_MASK   (0x00000080u)
#define	TIM_ARBE_BIT   (7)
#define	TIM_ARBE_BITS   (1)
#define	TIM_CMS   (0x00000060u)
#define	TIM_CMS_MASK   (0x00000060u)
#define	TIM_CMS_BIT   (5)
#define	TIM_CMS_BITS   (2)
#define	TIM_DIR   (0x00000010u)
#define	TIM_DIR_MASK   (0x00000010u)
#define	TIM_DIR_BIT   (4)
#define	TIM_DIR_BITS   (1)
#define	TIM_OPM   (0x00000008u)
#define	TIM_OPM_MASK   (0x00000008u)
#define	TIM_OPM_BIT   (3)
#define	TIM_OPM_BITS   (1)
#define	TIM_URS   (0x00000004u)
#define	TIM_URS_MASK   (0x00000004u)
#define	TIM_URS_BIT   (2)
#define	TIM_URS_BITS   (1)
#define	TIM_UDIS   (0x00000002u)
#define	TIM_UDIS_MASK   (0x00000002u)
#define	TIM_UDIS_BIT   (1)
#define	TIM_UDIS_BITS   (1)
#define	TIM_CEN   (0x00000001u)
#define	TIM_CEN_MASK   (0x00000001u)
#define	TIM_CEN_BIT   (0)
#define	TIM_CEN_BITS   (1)
#define	TIM1_CR2   *((volatile int32u *)0x4000E004u)
#define	TIM1_CR2_REG   *((volatile int32u *)0x4000E004u)
#define	TIM1_CR2_ADDR   (0x4000E004u)
#define	TIM1_CR2_RESET   (0x00000000u)
#define	TIM_TI1S   (0x00000080u)
#define	TIM_TI1S_MASK   (0x00000080u)
#define	TIM_TI1S_BIT   (7)
#define	TIM_TI1S_BITS   (1)
#define	TIM_MMS   (0x00000070u)
#define	TIM_MMS_MASK   (0x00000070u)
#define	TIM_MMS_BIT   (4)
#define	TIM_MMS_BITS   (3)
#define	TIM1_SMCR   *((volatile int32u *)0x4000E008u)
#define	TIM1_SMCR_REG   *((volatile int32u *)0x4000E008u)
#define	TIM1_SMCR_ADDR   (0x4000E008u)
#define	TIM1_SMCR_RESET   (0x00000000u)
#define	TIM_ETP   (0x00008000u)
#define	TIM_ETP_MASK   (0x00008000u)
#define	TIM_ETP_BIT   (15)
#define	TIM_ETP_BITS   (1)
#define	TIM_ECE   (0x00004000u)
#define	TIM_ECE_MASK   (0x00004000u)
#define	TIM_ECE_BIT   (14)
#define	TIM_ECE_BITS   (1)
#define	TIM_ETPS   (0x00003000u)
#define	TIM_ETPS_MASK   (0x00003000u)
#define	TIM_ETPS_BIT   (12)
#define	TIM_ETPS_BITS   (2)
#define	TIM_ETF   (0x00000F00u)
#define	TIM_ETF_MASK   (0x00000F00u)
#define	TIM_ETF_BIT   (8)
#define	TIM_ETF_BITS   (4)
#define	TIM_MSM   (0x00000080u)
#define	TIM_MSM_MASK   (0x00000080u)
#define	TIM_MSM_BIT   (7)
#define	TIM_MSM_BITS   (1)
#define	TIM_TS   (0x00000070u)
#define	TIM_TS_MASK   (0x00000070u)
#define	TIM_TS_BIT   (4)
#define	TIM_TS_BITS   (3)
#define	TIM_SMS   (0x00000007u)
#define	TIM_SMS_MASK   (0x00000007u)
#define	TIM_SMS_BIT   (0)
#define	TIM_SMS_BITS   (3)
#define	TMR1_DIER   *((volatile int32u *)0x4000E00Cu)
#define	TMR1_DIER_REG   *((volatile int32u *)0x4000E00Cu)
#define	TMR1_DIER_ADDR   (0x4000E00Cu)
#define	TMR1_DIER_RESET   (0x00000000u)
#define	TMR1_DIER_TIE   (0x00000040u)
#define	TMR1_DIER_TIE_MASK   (0x00000040u)
#define	TMR1_DIER_TIE_BIT   (6)
#define	TMR1_DIER_TIE_BITS   (1)
#define	TMR1_DIER_CC4IE   (0x00000010u)
#define	TMR1_DIER_CC4IE_MASK   (0x00000010u)
#define	TMR1_DIER_CC4IE_BIT   (4)
#define	TMR1_DIER_CC4IE_BITS   (1)
#define	TMR1_DIER_CC3IE   (0x00000008u)
#define	TMR1_DIER_CC3IE_MASK   (0x00000008u)
#define	TMR1_DIER_CC3IE_BIT   (3)
#define	TMR1_DIER_CC3IE_BITS   (1)
#define	TMR1_DIER_CC2IE   (0x00000004u)
#define	TMR1_DIER_CC2IE_MASK   (0x00000004u)
#define	TMR1_DIER_CC2IE_BIT   (2)
#define	TMR1_DIER_CC2IE_BITS   (1)
#define	TMR1_DIER_CC1IE   (0x00000002u)
#define	TMR1_DIER_CC1IE_MASK   (0x00000002u)
#define	TMR1_DIER_CC1IE_BIT   (1)
#define	TMR1_DIER_CC1IE_BITS   (1)
#define	TMR1_DIER_UIE   (0x00000001u)
#define	TMR1_DIER_UIE_MASK   (0x00000001u)
#define	TMR1_DIER_UIE_BIT   (0)
#define	TMR1_DIER_UIE_BITS   (1)
#define	TMR1_SR   *((volatile int32u *)0x4000E010u)
#define	TMR1_SR_REG   *((volatile int32u *)0x4000E010u)
#define	TMR1_SR_ADDR   (0x4000E010u)
#define	TMR1_SR_RESET   (0x00000000u)
#define	TMR1_SR_CC4OF   (0x00001000u)
#define	TMR1_SR_CC4OF_MASK   (0x00001000u)
#define	TMR1_SR_CC4OF_BIT   (12)
#define	TMR1_SR_CC4OF_BITS   (1)
#define	TMR1_SR_CC3OF   (0x00000800u)
#define	TMR1_SR_CC3OF_MASK   (0x00000800u)
#define	TMR1_SR_CC3OF_BIT   (11)
#define	TMR1_SR_CC3OF_BITS   (1)
#define	TMR1_SR_CC2OF   (0x00000400u)
#define	TMR1_SR_CC2OF_MASK   (0x00000400u)
#define	TMR1_SR_CC2OF_BIT   (10)
#define	TMR1_SR_CC2OF_BITS   (1)
#define	TMR1_SR_CC1OF   (0x00000200u)
#define	TMR1_SR_CC1OF_MASK   (0x00000200u)
#define	TMR1_SR_CC1OF_BIT   (9)
#define	TMR1_SR_CC1OF_BITS   (1)
#define	TMR1_SR_TIF   (0x00000040u)
#define	TMR1_SR_TIF_MASK   (0x00000040u)
#define	TMR1_SR_TIF_BIT   (6)
#define	TMR1_SR_TIF_BITS   (1)
#define	TMR1_SR_CC4IF   (0x00000010u)
#define	TMR1_SR_CC4IF_MASK   (0x00000010u)
#define	TMR1_SR_CC4IF_BIT   (4)
#define	TMR1_SR_CC4IF_BITS   (1)
#define	TMR1_SR_CC3IF   (0x00000008u)
#define	TMR1_SR_CC3IF_MASK   (0x00000008u)
#define	TMR1_SR_CC3IF_BIT   (3)
#define	TMR1_SR_CC3IF_BITS   (1)
#define	TMR1_SR_CC2IF   (0x00000004u)
#define	TMR1_SR_CC2IF_MASK   (0x00000004u)
#define	TMR1_SR_CC2IF_BIT   (2)
#define	TMR1_SR_CC2IF_BITS   (1)
#define	TMR1_SR_CC1IF   (0x00000002u)
#define	TMR1_SR_CC1IF_MASK   (0x00000002u)
#define	TMR1_SR_CC1IF_BIT   (1)
#define	TMR1_SR_CC1IF_BITS   (1)
#define	TMR1_SR_UIF   (0x00000001u)
#define	TMR1_SR_UIF_MASK   (0x00000001u)
#define	TMR1_SR_UIF_BIT   (0)
#define	TMR1_SR_UIF_BITS   (1)
#define	TIM1_EGR   *((volatile int32u *)0x4000E014u)
#define	TIM1_EGR_REG   *((volatile int32u *)0x4000E014u)
#define	TIM1_EGR_ADDR   (0x4000E014u)
#define	TIM1_EGR_RESET   (0x00000000u)
#define	TIM_TG   (0x00000040u)
#define	TIM_TG_MASK   (0x00000040u)
#define	TIM_TG_BIT   (6)
#define	TIM_TG_BITS   (1)
#define	TIM_CC4G   (0x00000010u)
#define	TIM_CC4G_MASK   (0x00000010u)
#define	TIM_CC4G_BIT   (4)
#define	TIM_CC4G_BITS   (1)
#define	TIM_CC3G   (0x00000008u)
#define	TIM_CC3G_MASK   (0x00000008u)
#define	TIM_CC3G_BIT   (3)
#define	TIM_CC3G_BITS   (1)
#define	TIM_CC2G   (0x00000004u)
#define	TIM_CC2G_MASK   (0x00000004u)
#define	TIM_CC2G_BIT   (2)
#define	TIM_CC2G_BITS   (1)
#define	TIM_CC1G   (0x00000002u)
#define	TIM_CC1G_MASK   (0x00000002u)
#define	TIM_CC1G_BIT   (1)
#define	TIM_CC1G_BITS   (1)
#define	TIM_UG   (0x00000001u)
#define	TIM_UG_MASK   (0x00000001u)
#define	TIM_UG_BIT   (0)
#define	TIM_UG_BITS   (1)
#define	TIM1_CCMR1   *((volatile int32u *)0x4000E018u)
#define	TIM1_CCMR1_REG   *((volatile int32u *)0x4000E018u)
#define	TIM1_CCMR1_ADDR   (0x4000E018u)
#define	TIM1_CCMR1_RESET   (0x00000000u)
#define	TIM_IC2F   (0x0000F000u)
#define	TIM_IC2F_MASK   (0x0000F000u)
#define	TIM_IC2F_BIT   (12)
#define	TIM_IC2F_BITS   (4)
#define	TIM_IC2PSC   (0x00000C00u)
#define	TIM_IC2PSC_MASK   (0x00000C00u)
#define	TIM_IC2PSC_BIT   (10)
#define	TIM_IC2PSC_BITS   (2)
#define	TIM_IC1F   (0x000000F0u)
#define	TIM_IC1F_MASK   (0x000000F0u)
#define	TIM_IC1F_BIT   (4)
#define	TIM_IC1F_BITS   (4)
#define	TIM_IC1PSC   (0x0000000Cu)
#define	TIM_IC1PSC_MASK   (0x0000000Cu)
#define	TIM_IC1PSC_BIT   (2)
#define	TIM_IC1PSC_BITS   (2)
#define	TIM_OC2CE   (0x00008000u)
#define	TIM_OC2CE_MASK   (0x00008000u)
#define	TIM_OC2CE_BIT   (15)
#define	TIM_OC2CE_BITS   (1)
#define	TIM_OC2M   (0x00007000u)
#define	TIM_OC2M_MASK   (0x00007000u)
#define	TIM_OC2M_BIT   (12)
#define	TIM_OC2M_BITS   (3)
#define	TIM_OC2BE   (0x00000800u)
#define	TIM_OC2BE_MASK   (0x00000800u)
#define	TIM_OC2BE_BIT   (11)
#define	TIM_OC2BE_BITS   (1)
#define	TIM_OC2FE   (0x00000400u)
#define	TIM_OC2FE_MASK   (0x00000400u)
#define	TIM_OC2FE_BIT   (10)
#define	TIM_OC2FE_BITS   (1)
#define	TIM_CC2S   (0x00000300u)
#define	TIM_CC2S_MASK   (0x00000300u)
#define	TIM_CC2S_BIT   (8)
#define	TIM_CC2S_BITS   (2)
#define	TIM_OC1CE   (0x00000080u)
#define	TIM_OC1CE_MASK   (0x00000080u)
#define	TIM_OC1CE_BIT   (7)
#define	TIM_OC1CE_BITS   (1)
#define	TIM_OC1M   (0x00000070u)
#define	TIM_OC1M_MASK   (0x00000070u)
#define	TIM_OC1M_BIT   (4)
#define	TIM_OC1M_BITS   (3)
#define	TIM_OC1PE   (0x00000008u)
#define	TIM_OC1PE_MASK   (0x00000008u)
#define	TIM_OC1PE_BIT   (3)
#define	TIM_OC1PE_BITS   (1)
#define	TIM_OC1FE   (0x00000004u)
#define	TIM_OC1FE_MASK   (0x00000004u)
#define	TIM_OC1FE_BIT   (2)
#define	TIM_OC1FE_BITS   (1)
#define	TIM_CC1S   (0x00000003u)
#define	TIM_CC1S_MASK   (0x00000003u)
#define	TIM_CC1S_BIT   (0)
#define	TIM_CC1S_BITS   (2)
#define	TIM1_CCMR2   *((volatile int32u *)0x4000E01Cu)
#define	TIM1_CCMR2_REG   *((volatile int32u *)0x4000E01Cu)
#define	TIM1_CCMR2_ADDR   (0x4000E01Cu)
#define	TIM1_CCMR2_RESET   (0x00000000u)
#define	TIM_IC4F   (0x0000F000u)
#define	TIM_IC4F_MASK   (0x0000F000u)
#define	TIM_IC4F_BIT   (12)
#define	TIM_IC4F_BITS   (4)
#define	TIM_IC4PSC   (0x00000C00u)
#define	TIM_IC4PSC_MASK   (0x00000C00u)
#define	TIM_IC4PSC_BIT   (10)
#define	TIM_IC4PSC_BITS   (2)
#define	TIM_IC3F   (0x000000F0u)
#define	TIM_IC3F_MASK   (0x000000F0u)
#define	TIM_IC3F_BIT   (4)
#define	TIM_IC3F_BITS   (4)
#define	TIM_IC3PSC   (0x0000000Cu)
#define	TIM_IC3PSC_MASK   (0x0000000Cu)
#define	TIM_IC3PSC_BIT   (2)
#define	TIM_IC3PSC_BITS   (2)
#define	TIM_OC4CE   (0x00008000u)
#define	TIM_OC4CE_MASK   (0x00008000u)
#define	TIM_OC4CE_BIT   (15)
#define	TIM_OC4CE_BITS   (1)
#define	TIM_OC4M   (0x00007000u)
#define	TIM_OC4M_MASK   (0x00007000u)
#define	TIM_OC4M_BIT   (12)
#define	TIM_OC4M_BITS   (3)
#define	TIM_OC4BE   (0x00000800u)
#define	TIM_OC4BE_MASK   (0x00000800u)
#define	TIM_OC4BE_BIT   (11)
#define	TIM_OC4BE_BITS   (1)
#define	TIM_OC4FE   (0x00000400u)
#define	TIM_OC4FE_MASK   (0x00000400u)
#define	TIM_OC4FE_BIT   (10)
#define	TIM_OC4FE_BITS   (1)
#define	TIM_CC4S   (0x00000300u)
#define	TIM_CC4S_MASK   (0x00000300u)
#define	TIM_CC4S_BIT   (8)
#define	TIM_CC4S_BITS   (2)
#define	TIM_OC3CE   (0x00000080u)
#define	TIM_OC3CE_MASK   (0x00000080u)
#define	TIM_OC3CE_BIT   (7)
#define	TIM_OC3CE_BITS   (1)
#define	TIM_OC3M   (0x00000070u)
#define	TIM_OC3M_MASK   (0x00000070u)
#define	TIM_OC3M_BIT   (4)
#define	TIM_OC3M_BITS   (3)
#define	TIM_OC3BE   (0x00000008u)
#define	TIM_OC3BE_MASK   (0x00000008u)
#define	TIM_OC3BE_BIT   (3)
#define	TIM_OC3BE_BITS   (1)
#define	TIM_OC3FE   (0x00000004u)
#define	TIM_OC3FE_MASK   (0x00000004u)
#define	TIM_OC3FE_BIT   (2)
#define	TIM_OC3FE_BITS   (1)
#define	TIM_CC3S   (0x00000003u)
#define	TIM_CC3S_MASK   (0x00000003u)
#define	TIM_CC3S_BIT   (0)
#define	TIM_CC3S_BITS   (2)
#define	TIM1_CCER   *((volatile int32u *)0x4000E020u)
#define	TIM1_CCER_REG   *((volatile int32u *)0x4000E020u)
#define	TIM1_CCER_ADDR   (0x4000E020u)
#define	TIM1_CCER_RESET   (0x00000000u)
#define	TIM_CC4P   (0x00002000u)
#define	TIM_CC4P_MASK   (0x00002000u)
#define	TIM_CC4P_BIT   (13)
#define	TIM_CC4P_BITS   (1)
#define	TIM_CC4E   (0x00001000u)
#define	TIM_CC4E_MASK   (0x00001000u)
#define	TIM_CC4E_BIT   (12)
#define	TIM_CC4E_BITS   (1)
#define	TIM_CC3P   (0x00000200u)
#define	TIM_CC3P_MASK   (0x00000200u)
#define	TIM_CC3P_BIT   (9)
#define	TIM_CC3P_BITS   (1)
#define	TIM_CC3E   (0x00000100u)
#define	TIM_CC3E_MASK   (0x00000100u)
#define	TIM_CC3E_BIT   (8)
#define	TIM_CC3E_BITS   (1)
#define	TIM_CC2P   (0x00000020u)
#define	TIM_CC2P_MASK   (0x00000020u)
#define	TIM_CC2P_BIT   (5)
#define	TIM_CC2P_BITS   (1)
#define	TIM_CC2E   (0x00000010u)
#define	TIM_CC2E_MASK   (0x00000010u)
#define	TIM_CC2E_BIT   (4)
#define	TIM_CC2E_BITS   (1)
#define	TIM_CC1P   (0x00000002u)
#define	TIM_CC1P_MASK   (0x00000002u)
#define	TIM_CC1P_BIT   (1)
#define	TIM_CC1P_BITS   (1)
#define	TIM_CC1E   (0x00000001u)
#define	TIM_CC1E_MASK   (0x00000001u)
#define	TIM_CC1E_BIT   (0)
#define	TIM_CC1E_BITS   (1)
#define	TIM1_CNT   *((volatile int32u *)0x4000E024u)
#define	TIM1_CNT_REG   *((volatile int32u *)0x4000E024u)
#define	TIM1_CNT_ADDR   (0x4000E024u)
#define	TIM1_CNT_RESET   (0x00000000u)
#define	TIM_CNT   (0x0000FFFFu)
#define	TIM_CNT_MASK   (0x0000FFFFu)
#define	TIM_CNT_BIT   (0)
#define	TIM_CNT_BITS   (16)
#define	TIM1_PSC   *((volatile int32u *)0x4000E028u)
#define	TIM1_PSC_REG   *((volatile int32u *)0x4000E028u)
#define	TIM1_PSC_ADDR   (0x4000E028u)
#define	TIM1_PSC_RESET   (0x00000000u)
#define	TIM_PSC   (0x0000000Fu)
#define	TIM_PSC_MASK   (0x0000000Fu)
#define	TIM_PSC_BIT   (0)
#define	TIM_PSC_BITS   (4)
#define	TIM1_ARR   *((volatile int32u *)0x4000E02Cu)
#define	TIM1_ARR_REG   *((volatile int32u *)0x4000E02Cu)
#define	TIM1_ARR_ADDR   (0x4000E02Cu)
#define	TIM1_ARR_RESET   (0x0000FFFFu)
#define	TIM_ARR   (0x0000FFFFu)
#define	TIM_ARR_MASK   (0x0000FFFFu)
#define	TIM_ARR_BIT   (0)
#define	TIM_ARR_BITS   (16)
#define	TIM1_CCR1   *((volatile int32u *)0x4000E034u)
#define	TIM1_CCR1_REG   *((volatile int32u *)0x4000E034u)
#define	TIM1_CCR1_ADDR   (0x4000E034u)
#define	TIM1_CCR1_RESET   (0x00000000u)
#define	TIM_CCR   (0x0000FFFFu)
#define	TIM_CCR_MASK   (0x0000FFFFu)
#define	TIM_CCR_BIT   (0)
#define	TIM_CCR_BITS   (16)
#define	TIM1_CCR2   *((volatile int32u *)0x4000E038u)
#define	TIM1_CCR2_REG   *((volatile int32u *)0x4000E038u)
#define	TIM1_CCR2_ADDR   (0x4000E038u)
#define	TIM1_CCR2_RESET   (0x00000000u)
#define	TIM_CCR   (0x0000FFFFu)
#define	TIM_CCR_MASK   (0x0000FFFFu)
#define	TIM_CCR_BIT   (0)
#define	TIM_CCR_BITS   (16)
#define	TIM1_CCR3   *((volatile int32u *)0x4000E03Cu)
#define	TIM1_CCR3_REG   *((volatile int32u *)0x4000E03Cu)
#define	TIM1_CCR3_ADDR   (0x4000E03Cu)
#define	TIM1_CCR3_RESET   (0x00000000u)
#define	TIM_CCR   (0x0000FFFFu)
#define	TIM_CCR_MASK   (0x0000FFFFu)
#define	TIM_CCR_BIT   (0)
#define	TIM_CCR_BITS   (16)
#define	TIM1_CCR4   *((volatile int32u *)0x4000E040u)
#define	TIM1_CCR4_REG   *((volatile int32u *)0x4000E040u)
#define	TIM1_CCR4_ADDR   (0x4000E040u)
#define	TIM1_CCR4_RESET   (0x00000000u)
#define	TIM_CCR   (0x0000FFFFu)
#define	TIM_CCR_MASK   (0x0000FFFFu)
#define	TIM_CCR_BIT   (0)
#define	TIM_CCR_BITS   (16)
#define	TIM1_OR   *((volatile int32u *)0x4000E050u)
#define	TIM1_OR_REG   *((volatile int32u *)0x4000E050u)
#define	TIM1_OR_ADDR   (0x4000E050u)
#define	TIM1_OR_RESET   (0x00000000u)
#define	TIM_ORRSVD   (0x00000008u)
#define	TIM_ORRSVD_MASK   (0x00000008u)
#define	TIM_ORRSVD_BIT   (3)
#define	TIM_ORRSVD_BITS   (1)
#define	TIM_CLKMSKEN   (0x00000004u)
#define	TIM_CLKMSKEN_MASK   (0x00000004u)
#define	TIM_CLKMSKEN_BIT   (2)
#define	TIM_CLKMSKEN_BITS   (1)
#define	TIM1_EXTRIGSEL   (0x00000003u)
#define	TIM1_EXTRIGSEL_MASK   (0x00000003u)
#define	TIM1_EXTRIGSEL_BIT   (0)
#define	TIM1_EXTRIGSEL_BITS   (2)
#define	BLOCK_TIM2_BASE   (0x4000F000u)
#define	BLOCK_TIM2_END   (0x4000F050u)
#define	BLOCK_TIM2_SIZE   (BLOCK_TIM2_END - BLOCK_TIM2_BASE + 1)
#define	TIM2_CR1   *((volatile int32u *)0x4000F000u)
#define	TIM2_CR1_REG   *((volatile int32u *)0x4000F000u)
#define	TIM2_CR1_ADDR   (0x4000F000u)
#define	TIM2_CR1_RESET   (0x00000000u)
#define	TIM_ARBE   (0x00000080u)
#define	TIM_ARBE_MASK   (0x00000080u)
#define	TIM_ARBE_BIT   (7)
#define	TIM_ARBE_BITS   (1)
#define	TIM_CMS   (0x00000060u)
#define	TIM_CMS_MASK   (0x00000060u)
#define	TIM_CMS_BIT   (5)
#define	TIM_CMS_BITS   (2)
#define	TIM_DIR   (0x00000010u)
#define	TIM_DIR_MASK   (0x00000010u)
#define	TIM_DIR_BIT   (4)
#define	TIM_DIR_BITS   (1)
#define	TIM_OPM   (0x00000008u)
#define	TIM_OPM_MASK   (0x00000008u)
#define	TIM_OPM_BIT   (3)
#define	TIM_OPM_BITS   (1)
#define	TIM_URS   (0x00000004u)
#define	TIM_URS_MASK   (0x00000004u)
#define	TIM_URS_BIT   (2)
#define	TIM_URS_BITS   (1)
#define	TIM_UDIS   (0x00000002u)
#define	TIM_UDIS_MASK   (0x00000002u)
#define	TIM_UDIS_BIT   (1)
#define	TIM_UDIS_BITS   (1)
#define	TIM_CEN   (0x00000001u)
#define	TIM_CEN_MASK   (0x00000001u)
#define	TIM_CEN_BIT   (0)
#define	TIM_CEN_BITS   (1)
#define	TIM2_CR2   *((volatile int32u *)0x4000F004u)
#define	TIM2_CR2_REG   *((volatile int32u *)0x4000F004u)
#define	TIM2_CR2_ADDR   (0x4000F004u)
#define	TIM2_CR2_RESET   (0x00000000u)
#define	TIM_TI1S   (0x00000080u)
#define	TIM_TI1S_MASK   (0x00000080u)
#define	TIM_TI1S_BIT   (7)
#define	TIM_TI1S_BITS   (1)
#define	TIM_MMS   (0x00000070u)
#define	TIM_MMS_MASK   (0x00000070u)
#define	TIM_MMS_BIT   (4)
#define	TIM_MMS_BITS   (3)
#define	TIM2_SMCR   *((volatile int32u *)0x4000F008u)
#define	TIM2_SMCR_REG   *((volatile int32u *)0x4000F008u)
#define	TIM2_SMCR_ADDR   (0x4000F008u)
#define	TIM2_SMCR_RESET   (0x00000000u)
#define	TIM_ETP   (0x00008000u)
#define	TIM_ETP_MASK   (0x00008000u)
#define	TIM_ETP_BIT   (15)
#define	TIM_ETP_BITS   (1)
#define	TIM_ECE   (0x00004000u)
#define	TIM_ECE_MASK   (0x00004000u)
#define	TIM_ECE_BIT   (14)
#define	TIM_ECE_BITS   (1)
#define	TIM_ETPS   (0x00003000u)
#define	TIM_ETPS_MASK   (0x00003000u)
#define	TIM_ETPS_BIT   (12)
#define	TIM_ETPS_BITS   (2)
#define	TIM_ETF   (0x00000F00u)
#define	TIM_ETF_MASK   (0x00000F00u)
#define	TIM_ETF_BIT   (8)
#define	TIM_ETF_BITS   (4)
#define	TIM_MSM   (0x00000080u)
#define	TIM_MSM_MASK   (0x00000080u)
#define	TIM_MSM_BIT   (7)
#define	TIM_MSM_BITS   (1)
#define	TIM_TS   (0x00000070u)
#define	TIM_TS_MASK   (0x00000070u)
#define	TIM_TS_BIT   (4)
#define	TIM_TS_BITS   (3)
#define	TIM_SMS   (0x00000007u)
#define	TIM_SMS_MASK   (0x00000007u)
#define	TIM_SMS_BIT   (0)
#define	TIM_SMS_BITS   (3)
#define	TMR2_DIER   *((volatile int32u *)0x4000F00Cu)
#define	TMR2_DIER_REG   *((volatile int32u *)0x4000F00Cu)
#define	TMR2_DIER_ADDR   (0x4000F00Cu)
#define	TMR2_DIER_RESET   (0x00000000u)
#define	TMR2_DIER_TIE   (0x00000040u)
#define	TMR2_DIER_TIE_MASK   (0x00000040u)
#define	TMR2_DIER_TIE_BIT   (6)
#define	TMR2_DIER_TIE_BITS   (1)
#define	TMR2_DIER_CC4IE   (0x00000010u)
#define	TMR2_DIER_CC4IE_MASK   (0x00000010u)
#define	TMR2_DIER_CC4IE_BIT   (4)
#define	TMR2_DIER_CC4IE_BITS   (1)
#define	TMR2_DIER_CC3IE   (0x00000008u)
#define	TMR2_DIER_CC3IE_MASK   (0x00000008u)
#define	TMR2_DIER_CC3IE_BIT   (3)
#define	TMR2_DIER_CC3IE_BITS   (1)
#define	TMR2_DIER_CC2IE   (0x00000004u)
#define	TMR2_DIER_CC2IE_MASK   (0x00000004u)
#define	TMR2_DIER_CC2IE_BIT   (2)
#define	TMR2_DIER_CC2IE_BITS   (1)
#define	TMR2_DIER_CC1IE   (0x00000002u)
#define	TMR2_DIER_CC1IE_MASK   (0x00000002u)
#define	TMR2_DIER_CC1IE_BIT   (1)
#define	TMR2_DIER_CC1IE_BITS   (1)
#define	TMR2_DIER_UIE   (0x00000001u)
#define	TMR2_DIER_UIE_MASK   (0x00000001u)
#define	TMR2_DIER_UIE_BIT   (0)
#define	TMR2_DIER_UIE_BITS   (1)
#define	TMR2_SR   *((volatile int32u *)0x4000F010u)
#define	TMR2_SR_REG   *((volatile int32u *)0x4000F010u)
#define	TMR2_SR_ADDR   (0x4000F010u)
#define	TMR2_SR_RESET   (0x00000000u)
#define	TMR2_SR_CC4OF   (0x00001000u)
#define	TMR2_SR_CC4OF_MASK   (0x00001000u)
#define	TMR2_SR_CC4OF_BIT   (12)
#define	TMR2_SR_CC4OF_BITS   (1)
#define	TMR2_SR_CC3OF   (0x00000800u)
#define	TMR2_SR_CC3OF_MASK   (0x00000800u)
#define	TMR2_SR_CC3OF_BIT   (11)
#define	TMR2_SR_CC3OF_BITS   (1)
#define	TMR2_SR_CC2OF   (0x00000400u)
#define	TMR2_SR_CC2OF_MASK   (0x00000400u)
#define	TMR2_SR_CC2OF_BIT   (10)
#define	TMR2_SR_CC2OF_BITS   (1)
#define	TMR2_SR_CC1OF   (0x00000200u)
#define	TMR2_SR_CC1OF_MASK   (0x00000200u)
#define	TMR2_SR_CC1OF_BIT   (9)
#define	TMR2_SR_CC1OF_BITS   (1)
#define	TMR2_SR_TIF   (0x00000040u)
#define	TMR2_SR_TIF_MASK   (0x00000040u)
#define	TMR2_SR_TIF_BIT   (6)
#define	TMR2_SR_TIF_BITS   (1)
#define	TMR2_SR_CC4IF   (0x00000010u)
#define	TMR2_SR_CC4IF_MASK   (0x00000010u)
#define	TMR2_SR_CC4IF_BIT   (4)
#define	TMR2_SR_CC4IF_BITS   (1)
#define	TMR2_SR_CC3IF   (0x00000008u)
#define	TMR2_SR_CC3IF_MASK   (0x00000008u)
#define	TMR2_SR_CC3IF_BIT   (3)
#define	TMR2_SR_CC3IF_BITS   (1)
#define	TMR2_SR_CC2IF   (0x00000004u)
#define	TMR2_SR_CC2IF_MASK   (0x00000004u)
#define	TMR2_SR_CC2IF_BIT   (2)
#define	TMR2_SR_CC2IF_BITS   (1)
#define	TMR2_SR_CC1IF   (0x00000002u)
#define	TMR2_SR_CC1IF_MASK   (0x00000002u)
#define	TMR2_SR_CC1IF_BIT   (1)
#define	TMR2_SR_CC1IF_BITS   (1)
#define	TMR2_SR_UIF   (0x00000001u)
#define	TMR2_SR_UIF_MASK   (0x00000001u)
#define	TMR2_SR_UIF_BIT   (0)
#define	TMR2_SR_UIF_BITS   (1)
#define	TIM2_EGR   *((volatile int32u *)0x4000F014u)
#define	TIM2_EGR_REG   *((volatile int32u *)0x4000F014u)
#define	TIM2_EGR_ADDR   (0x4000F014u)
#define	TIM2_EGR_RESET   (0x00000000u)
#define	TIM_TG   (0x00000040u)
#define	TIM_TG_MASK   (0x00000040u)
#define	TIM_TG_BIT   (6)
#define	TIM_TG_BITS   (1)
#define	TIM_CC4G   (0x00000010u)
#define	TIM_CC4G_MASK   (0x00000010u)
#define	TIM_CC4G_BIT   (4)
#define	TIM_CC4G_BITS   (1)
#define	TIM_CC3G   (0x00000008u)
#define	TIM_CC3G_MASK   (0x00000008u)
#define	TIM_CC3G_BIT   (3)
#define	TIM_CC3G_BITS   (1)
#define	TIM_CC2G   (0x00000004u)
#define	TIM_CC2G_MASK   (0x00000004u)
#define	TIM_CC2G_BIT   (2)
#define	TIM_CC2G_BITS   (1)
#define	TIM_CC1G   (0x00000002u)
#define	TIM_CC1G_MASK   (0x00000002u)
#define	TIM_CC1G_BIT   (1)
#define	TIM_CC1G_BITS   (1)
#define	TIM_UG   (0x00000001u)
#define	TIM_UG_MASK   (0x00000001u)
#define	TIM_UG_BIT   (0)
#define	TIM_UG_BITS   (1)
#define	TIM2_CCMR1   *((volatile int32u *)0x4000F018u)
#define	TIM2_CCMR1_REG   *((volatile int32u *)0x4000F018u)
#define	TIM2_CCMR1_ADDR   (0x4000F018u)
#define	TIM2_CCMR1_RESET   (0x00000000u)
#define	TIM_IC2F   (0x0000F000u)
#define	TIM_IC2F_MASK   (0x0000F000u)
#define	TIM_IC2F_BIT   (12)
#define	TIM_IC2F_BITS   (4)
#define	TIM_IC2PSC   (0x00000C00u)
#define	TIM_IC2PSC_MASK   (0x00000C00u)
#define	TIM_IC2PSC_BIT   (10)
#define	TIM_IC2PSC_BITS   (2)
#define	TIM_IC1F   (0x000000F0u)
#define	TIM_IC1F_MASK   (0x000000F0u)
#define	TIM_IC1F_BIT   (4)
#define	TIM_IC1F_BITS   (4)
#define	TIM_IC1PSC   (0x0000000Cu)
#define	TIM_IC1PSC_MASK   (0x0000000Cu)
#define	TIM_IC1PSC_BIT   (2)
#define	TIM_IC1PSC_BITS   (2)
#define	TIM_OC2CE   (0x00008000u)
#define	TIM_OC2CE_MASK   (0x00008000u)
#define	TIM_OC2CE_BIT   (15)
#define	TIM_OC2CE_BITS   (1)
#define	TIM_OC2M   (0x00007000u)
#define	TIM_OC2M_MASK   (0x00007000u)
#define	TIM_OC2M_BIT   (12)
#define	TIM_OC2M_BITS   (3)
#define	TIM_OC2BE   (0x00000800u)
#define	TIM_OC2BE_MASK   (0x00000800u)
#define	TIM_OC2BE_BIT   (11)
#define	TIM_OC2BE_BITS   (1)
#define	TIM_OC2FE   (0x00000400u)
#define	TIM_OC2FE_MASK   (0x00000400u)
#define	TIM_OC2FE_BIT   (10)
#define	TIM_OC2FE_BITS   (1)
#define	TIM_CC2S   (0x00000300u)
#define	TIM_CC2S_MASK   (0x00000300u)
#define	TIM_CC2S_BIT   (8)
#define	TIM_CC2S_BITS   (2)
#define	TIM_OC1CE   (0x00000080u)
#define	TIM_OC1CE_MASK   (0x00000080u)
#define	TIM_OC1CE_BIT   (7)
#define	TIM_OC1CE_BITS   (1)
#define	TIM_OC1M   (0x00000070u)
#define	TIM_OC1M_MASK   (0x00000070u)
#define	TIM_OC1M_BIT   (4)
#define	TIM_OC1M_BITS   (3)
#define	TIM_OC1PE   (0x00000008u)
#define	TIM_OC1PE_MASK   (0x00000008u)
#define	TIM_OC1PE_BIT   (3)
#define	TIM_OC1PE_BITS   (1)
#define	TIM_OC1FE   (0x00000004u)
#define	TIM_OC1FE_MASK   (0x00000004u)
#define	TIM_OC1FE_BIT   (2)
#define	TIM_OC1FE_BITS   (1)
#define	TIM_CC1S   (0x00000003u)
#define	TIM_CC1S_MASK   (0x00000003u)
#define	TIM_CC1S_BIT   (0)
#define	TIM_CC1S_BITS   (2)
#define	TIM2_CCMR2   *((volatile int32u *)0x4000F01Cu)
#define	TIM2_CCMR2_REG   *((volatile int32u *)0x4000F01Cu)
#define	TIM2_CCMR2_ADDR   (0x4000F01Cu)
#define	TIM2_CCMR2_RESET   (0x00000000u)
#define	TIM_IC4F   (0x0000F000u)
#define	TIM_IC4F_MASK   (0x0000F000u)
#define	TIM_IC4F_BIT   (12)
#define	TIM_IC4F_BITS   (4)
#define	TIM_IC4PSC   (0x00000C00u)
#define	TIM_IC4PSC_MASK   (0x00000C00u)
#define	TIM_IC4PSC_BIT   (10)
#define	TIM_IC4PSC_BITS   (2)
#define	TIM_IC3F   (0x000000F0u)
#define	TIM_IC3F_MASK   (0x000000F0u)
#define	TIM_IC3F_BIT   (4)
#define	TIM_IC3F_BITS   (4)
#define	TIM_IC3PSC   (0x0000000Cu)
#define	TIM_IC3PSC_MASK   (0x0000000Cu)
#define	TIM_IC3PSC_BIT   (2)
#define	TIM_IC3PSC_BITS   (2)
#define	TIM_OC4CE   (0x00008000u)
#define	TIM_OC4CE_MASK   (0x00008000u)
#define	TIM_OC4CE_BIT   (15)
#define	TIM_OC4CE_BITS   (1)
#define	TIM_OC4M   (0x00007000u)
#define	TIM_OC4M_MASK   (0x00007000u)
#define	TIM_OC4M_BIT   (12)
#define	TIM_OC4M_BITS   (3)
#define	TIM_OC4BE   (0x00000800u)
#define	TIM_OC4BE_MASK   (0x00000800u)
#define	TIM_OC4BE_BIT   (11)
#define	TIM_OC4BE_BITS   (1)
#define	TIM_OC4FE   (0x00000400u)
#define	TIM_OC4FE_MASK   (0x00000400u)
#define	TIM_OC4FE_BIT   (10)
#define	TIM_OC4FE_BITS   (1)
#define	TIM_CC4S   (0x00000300u)
#define	TIM_CC4S_MASK   (0x00000300u)
#define	TIM_CC4S_BIT   (8)
#define	TIM_CC4S_BITS   (2)
#define	TIM_OC3CE   (0x00000080u)
#define	TIM_OC3CE_MASK   (0x00000080u)
#define	TIM_OC3CE_BIT   (7)
#define	TIM_OC3CE_BITS   (1)
#define	TIM_OC3M   (0x00000070u)
#define	TIM_OC3M_MASK   (0x00000070u)
#define	TIM_OC3M_BIT   (4)
#define	TIM_OC3M_BITS   (3)
#define	TIM_OC3BE   (0x00000008u)
#define	TIM_OC3BE_MASK   (0x00000008u)
#define	TIM_OC3BE_BIT   (3)
#define	TIM_OC3BE_BITS   (1)
#define	TIM_OC3FE   (0x00000004u)
#define	TIM_OC3FE_MASK   (0x00000004u)
#define	TIM_OC3FE_BIT   (2)
#define	TIM_OC3FE_BITS   (1)
#define	TIM_CC3S   (0x00000003u)
#define	TIM_CC3S_MASK   (0x00000003u)
#define	TIM_CC3S_BIT   (0)
#define	TIM_CC3S_BITS   (2)
#define	TIM2_CCER   *((volatile int32u *)0x4000F020u)
#define	TIM2_CCER_REG   *((volatile int32u *)0x4000F020u)
#define	TIM2_CCER_ADDR   (0x4000F020u)
#define	TIM2_CCER_RESET   (0x00000000u)
#define	TIM_CC4P   (0x00002000u)
#define	TIM_CC4P_MASK   (0x00002000u)
#define	TIM_CC4P_BIT   (13)
#define	TIM_CC4P_BITS   (1)
#define	TIM_CC4E   (0x00001000u)
#define	TIM_CC4E_MASK   (0x00001000u)
#define	TIM_CC4E_BIT   (12)
#define	TIM_CC4E_BITS   (1)
#define	TIM_CC3P   (0x00000200u)
#define	TIM_CC3P_MASK   (0x00000200u)
#define	TIM_CC3P_BIT   (9)
#define	TIM_CC3P_BITS   (1)
#define	TIM_CC3E   (0x00000100u)
#define	TIM_CC3E_MASK   (0x00000100u)
#define	TIM_CC3E_BIT   (8)
#define	TIM_CC3E_BITS   (1)
#define	TIM_CC2P   (0x00000020u)
#define	TIM_CC2P_MASK   (0x00000020u)
#define	TIM_CC2P_BIT   (5)
#define	TIM_CC2P_BITS   (1)
#define	TIM_CC2E   (0x00000010u)
#define	TIM_CC2E_MASK   (0x00000010u)
#define	TIM_CC2E_BIT   (4)
#define	TIM_CC2E_BITS   (1)
#define	TIM_CC1P   (0x00000002u)
#define	TIM_CC1P_MASK   (0x00000002u)
#define	TIM_CC1P_BIT   (1)
#define	TIM_CC1P_BITS   (1)
#define	TIM_CC1E   (0x00000001u)
#define	TIM_CC1E_MASK   (0x00000001u)
#define	TIM_CC1E_BIT   (0)
#define	TIM_CC1E_BITS   (1)
#define	TIM2_CNT   *((volatile int32u *)0x4000F024u)
#define	TIM2_CNT_REG   *((volatile int32u *)0x4000F024u)
#define	TIM2_CNT_ADDR   (0x4000F024u)
#define	TIM2_CNT_RESET   (0x00000000u)
#define	TIM_CNT   (0x0000FFFFu)
#define	TIM_CNT_MASK   (0x0000FFFFu)
#define	TIM_CNT_BIT   (0)
#define	TIM_CNT_BITS   (16)
#define	TIM2_PSC   *((volatile int32u *)0x4000F028u)
#define	TIM2_PSC_REG   *((volatile int32u *)0x4000F028u)
#define	TIM2_PSC_ADDR   (0x4000F028u)
#define	TIM2_PSC_RESET   (0x00000000u)
#define	TIM_PSC   (0x0000000Fu)
#define	TIM_PSC_MASK   (0x0000000Fu)
#define	TIM_PSC_BIT   (0)
#define	TIM_PSC_BITS   (4)
#define	TIM2_ARR   *((volatile int32u *)0x4000F02Cu)
#define	TIM2_ARR_REG   *((volatile int32u *)0x4000F02Cu)
#define	TIM2_ARR_ADDR   (0x4000F02Cu)
#define	TIM2_ARR_RESET   (0x0000FFFFu)
#define	TIM_ARR   (0x0000FFFFu)
#define	TIM_ARR_MASK   (0x0000FFFFu)
#define	TIM_ARR_BIT   (0)
#define	TIM_ARR_BITS   (16)
#define	TIM2_CCR1   *((volatile int32u *)0x4000F034u)
#define	TIM2_CCR1_REG   *((volatile int32u *)0x4000F034u)
#define	TIM2_CCR1_ADDR   (0x4000F034u)
#define	TIM2_CCR1_RESET   (0x00000000u)
#define	TIM_CCR   (0x0000FFFFu)
#define	TIM_CCR_MASK   (0x0000FFFFu)
#define	TIM_CCR_BIT   (0)
#define	TIM_CCR_BITS   (16)
#define	TIM2_CCR2   *((volatile int32u *)0x4000F038u)
#define	TIM2_CCR2_REG   *((volatile int32u *)0x4000F038u)
#define	TIM2_CCR2_ADDR   (0x4000F038u)
#define	TIM2_CCR2_RESET   (0x00000000u)
#define	TIM_CCR   (0x0000FFFFu)
#define	TIM_CCR_MASK   (0x0000FFFFu)
#define	TIM_CCR_BIT   (0)
#define	TIM_CCR_BITS   (16)
#define	TIM2_CCR3   *((volatile int32u *)0x4000F03Cu)
#define	TIM2_CCR3_REG   *((volatile int32u *)0x4000F03Cu)
#define	TIM2_CCR3_ADDR   (0x4000F03Cu)
#define	TIM2_CCR3_RESET   (0x00000000u)
#define	TIM_CCR   (0x0000FFFFu)
#define	TIM_CCR_MASK   (0x0000FFFFu)
#define	TIM_CCR_BIT   (0)
#define	TIM_CCR_BITS   (16)
#define	TIM2_CCR4   *((volatile int32u *)0x4000F040u)
#define	TIM2_CCR4_REG   *((volatile int32u *)0x4000F040u)
#define	TIM2_CCR4_ADDR   (0x4000F040u)
#define	TIM2_CCR4_RESET   (0x00000000u)
#define	TIM_CCR   (0x0000FFFFu)
#define	TIM_CCR_MASK   (0x0000FFFFu)
#define	TIM_CCR_BIT   (0)
#define	TIM_CCR_BITS   (16)
#define	TIM2_OR   *((volatile int32u *)0x4000F050u)
#define	TIM2_OR_REG   *((volatile int32u *)0x4000F050u)
#define	TIM2_OR_ADDR   (0x4000F050u)
#define	TIM2_OR_RESET   (0x00000000u)
#define	TIM_REMAPC4   (0x00000080u)
#define	TIM_REMAPC4_MASK   (0x00000080u)
#define	TIM_REMAPC4_BIT   (7)
#define	TIM_REMAPC4_BITS   (1)
#define	TIM_REMAPC3   (0x00000040u)
#define	TIM_REMAPC3_MASK   (0x00000040u)
#define	TIM_REMAPC3_BIT   (6)
#define	TIM_REMAPC3_BITS   (1)
#define	TIM_REMAPC2   (0x00000020u)
#define	TIM_REMAPC2_MASK   (0x00000020u)
#define	TIM_REMAPC2_BIT   (5)
#define	TIM_REMAPC2_BITS   (1)
#define	TIM_REMAPC1   (0x00000010u)
#define	TIM_REMAPC1_MASK   (0x00000010u)
#define	TIM_REMAPC1_BIT   (4)
#define	TIM_REMAPC1_BITS   (1)
#define	TIM_ORRSVD   (0x00000008u)
#define	TIM_ORRSVD_MASK   (0x00000008u)
#define	TIM_ORRSVD_BIT   (3)
#define	TIM_ORRSVD_BITS   (1)
#define	TIM_CLKMSKEN   (0x00000004u)
#define	TIM_CLKMSKEN_MASK   (0x00000004u)
#define	TIM_CLKMSKEN_BIT   (2)
#define	TIM_CLKMSKEN_BITS   (1)
#define	TIM1_EXTRIGSEL   (0x00000003u)
#define	TIM1_EXTRIGSEL_MASK   (0x00000003u)
#define	TIM1_EXTRIGSEL_BIT   (0)
#define	TIM1_EXTRIGSEL_BITS   (2)
#define	DATA_EXT_RAM_BASE   (0x60000000u)
#define	DATA_EXT_RAM_END   (0x9FFFFFFFu)
#define	DATA_EXT_RAM_SIZE   (DATA_EXT_RAM_END - DATA_EXT_RAM_BASE + 1)
#define	DATA_EXT_DEVICE_BASE   (0xA0000000u)
#define	DATA_EXT_DEVICE_END   (0xDFFFFFFFu)
#define	DATA_EXT_DEVICE_SIZE   (DATA_EXT_DEVICE_END - DATA_EXT_DEVICE_BASE + 1)
#define	DATA_ITM_BASE   (0xE0000000u)
#define	DATA_ITM_END   (0xE0000FFFu)
#define	DATA_ITM_SIZE   (DATA_ITM_END - DATA_ITM_BASE + 1)
#define	ITM_SP0   *((volatile int32u *)0xE0000000u)
#define	ITM_SP0_REG   *((volatile int32u *)0xE0000000u)
#define	ITM_SP0_ADDR   (0xE0000000u)
#define	ITM_SP0_RESET   (0x00000000u)
#define	ITM_SP0_FIFOREADY   (0x00000001u)
#define	ITM_SP0_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP0_FIFOREADY_BIT   (0)
#define	ITM_SP0_FIFOREADY_BITS   (1)
#define	ITM_SP0_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP0_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP0_STIMULUS_BIT   (0)
#define	ITM_SP0_STIMULUS_BITS   (32)
#define	ITM_SP1   *((volatile int32u *)0xE0000004u)
#define	ITM_SP1_REG   *((volatile int32u *)0xE0000004u)
#define	ITM_SP1_ADDR   (0xE0000004u)
#define	ITM_SP1_RESET   (0x00000000u)
#define	ITM_SP1_FIFOREADY   (0x00000001u)
#define	ITM_SP1_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP1_FIFOREADY_BIT   (0)
#define	ITM_SP1_FIFOREADY_BITS   (1)
#define	ITM_SP1_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP1_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP1_STIMULUS_BIT   (0)
#define	ITM_SP1_STIMULUS_BITS   (32)
#define	ITM_SP2   *((volatile int32u *)0xE0000008u)
#define	ITM_SP2_REG   *((volatile int32u *)0xE0000008u)
#define	ITM_SP2_ADDR   (0xE0000008u)
#define	ITM_SP2_RESET   (0x00000000u)
#define	ITM_SP2_FIFOREADY   (0x00000001u)
#define	ITM_SP2_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP2_FIFOREADY_BIT   (0)
#define	ITM_SP2_FIFOREADY_BITS   (1)
#define	ITM_SP2_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP2_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP2_STIMULUS_BIT   (0)
#define	ITM_SP2_STIMULUS_BITS   (32)
#define	ITM_SP3   *((volatile int32u *)0xE000000Cu)
#define	ITM_SP3_REG   *((volatile int32u *)0xE000000Cu)
#define	ITM_SP3_ADDR   (0xE000000Cu)
#define	ITM_SP3_RESET   (0x00000000u)
#define	ITM_SP3_FIFOREADY   (0x00000001u)
#define	ITM_SP3_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP3_FIFOREADY_BIT   (0)
#define	ITM_SP3_FIFOREADY_BITS   (1)
#define	ITM_SP3_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP3_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP3_STIMULUS_BIT   (0)
#define	ITM_SP3_STIMULUS_BITS   (32)
#define	ITM_SP4   *((volatile int32u *)0xE0000010u)
#define	ITM_SP4_REG   *((volatile int32u *)0xE0000010u)
#define	ITM_SP4_ADDR   (0xE0000010u)
#define	ITM_SP4_RESET   (0x00000000u)
#define	ITM_SP4_FIFOREADY   (0x00000001u)
#define	ITM_SP4_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP4_FIFOREADY_BIT   (0)
#define	ITM_SP4_FIFOREADY_BITS   (1)
#define	ITM_SP4_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP4_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP4_STIMULUS_BIT   (0)
#define	ITM_SP4_STIMULUS_BITS   (32)
#define	ITM_SP5   *((volatile int32u *)0xE0000014u)
#define	ITM_SP5_REG   *((volatile int32u *)0xE0000014u)
#define	ITM_SP5_ADDR   (0xE0000014u)
#define	ITM_SP5_RESET   (0x00000000u)
#define	ITM_SP5_FIFOREADY   (0x00000001u)
#define	ITM_SP5_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP5_FIFOREADY_BIT   (0)
#define	ITM_SP5_FIFOREADY_BITS   (1)
#define	ITM_SP5_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP5_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP5_STIMULUS_BIT   (0)
#define	ITM_SP5_STIMULUS_BITS   (32)
#define	ITM_SP6   *((volatile int32u *)0xE0000018u)
#define	ITM_SP6_REG   *((volatile int32u *)0xE0000018u)
#define	ITM_SP6_ADDR   (0xE0000018u)
#define	ITM_SP6_RESET   (0x00000000u)
#define	ITM_SP6_FIFOREADY   (0x00000001u)
#define	ITM_SP6_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP6_FIFOREADY_BIT   (0)
#define	ITM_SP6_FIFOREADY_BITS   (1)
#define	ITM_SP6_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP6_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP6_STIMULUS_BIT   (0)
#define	ITM_SP6_STIMULUS_BITS   (32)
#define	ITM_SP7   *((volatile int32u *)0xE000001Cu)
#define	ITM_SP7_REG   *((volatile int32u *)0xE000001Cu)
#define	ITM_SP7_ADDR   (0xE000001Cu)
#define	ITM_SP7_RESET   (0x00000000u)
#define	ITM_SP7_FIFOREADY   (0x00000001u)
#define	ITM_SP7_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP7_FIFOREADY_BIT   (0)
#define	ITM_SP7_FIFOREADY_BITS   (1)
#define	ITM_SP7_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP7_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP7_STIMULUS_BIT   (0)
#define	ITM_SP7_STIMULUS_BITS   (32)
#define	ITM_SP8   *((volatile int32u *)0xE0000020u)
#define	ITM_SP8_REG   *((volatile int32u *)0xE0000020u)
#define	ITM_SP8_ADDR   (0xE0000020u)
#define	ITM_SP8_RESET   (0x00000000u)
#define	ITM_SP8_FIFOREADY   (0x00000001u)
#define	ITM_SP8_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP8_FIFOREADY_BIT   (0)
#define	ITM_SP8_FIFOREADY_BITS   (1)
#define	ITM_SP8_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP8_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP8_STIMULUS_BIT   (0)
#define	ITM_SP8_STIMULUS_BITS   (32)
#define	ITM_SP9   *((volatile int32u *)0xE0000024u)
#define	ITM_SP9_REG   *((volatile int32u *)0xE0000024u)
#define	ITM_SP9_ADDR   (0xE0000024u)
#define	ITM_SP9_RESET   (0x00000000u)
#define	ITM_SP9_FIFOREADY   (0x00000001u)
#define	ITM_SP9_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP9_FIFOREADY_BIT   (0)
#define	ITM_SP9_FIFOREADY_BITS   (1)
#define	ITM_SP9_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP9_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP9_STIMULUS_BIT   (0)
#define	ITM_SP9_STIMULUS_BITS   (32)
#define	ITM_SP10   *((volatile int32u *)0xE0000028u)
#define	ITM_SP10_REG   *((volatile int32u *)0xE0000028u)
#define	ITM_SP10_ADDR   (0xE0000028u)
#define	ITM_SP10_RESET   (0x00000000u)
#define	ITM_SP10_FIFOREADY   (0x00000001u)
#define	ITM_SP10_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP10_FIFOREADY_BIT   (0)
#define	ITM_SP10_FIFOREADY_BITS   (1)
#define	ITM_SP10_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP10_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP10_STIMULUS_BIT   (0)
#define	ITM_SP10_STIMULUS_BITS   (32)
#define	ITM_SP11   *((volatile int32u *)0xE000002Cu)
#define	ITM_SP11_REG   *((volatile int32u *)0xE000002Cu)
#define	ITM_SP11_ADDR   (0xE000002Cu)
#define	ITM_SP11_RESET   (0x00000000u)
#define	ITM_SP11_FIFOREADY   (0x00000001u)
#define	ITM_SP11_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP11_FIFOREADY_BIT   (0)
#define	ITM_SP11_FIFOREADY_BITS   (1)
#define	ITM_SP11_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP11_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP11_STIMULUS_BIT   (0)
#define	ITM_SP11_STIMULUS_BITS   (32)
#define	ITM_SP12   *((volatile int32u *)0xE0000030u)
#define	ITM_SP12_REG   *((volatile int32u *)0xE0000030u)
#define	ITM_SP12_ADDR   (0xE0000030u)
#define	ITM_SP12_RESET   (0x00000000u)
#define	ITM_SP12_FIFOREADY   (0x00000001u)
#define	ITM_SP12_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP12_FIFOREADY_BIT   (0)
#define	ITM_SP12_FIFOREADY_BITS   (1)
#define	ITM_SP12_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP12_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP12_STIMULUS_BIT   (0)
#define	ITM_SP12_STIMULUS_BITS   (32)
#define	ITM_SP13   *((volatile int32u *)0xE0000034u)
#define	ITM_SP13_REG   *((volatile int32u *)0xE0000034u)
#define	ITM_SP13_ADDR   (0xE0000034u)
#define	ITM_SP13_RESET   (0x00000000u)
#define	ITM_SP13_FIFOREADY   (0x00000001u)
#define	ITM_SP13_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP13_FIFOREADY_BIT   (0)
#define	ITM_SP13_FIFOREADY_BITS   (1)
#define	ITM_SP13_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP13_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP13_STIMULUS_BIT   (0)
#define	ITM_SP13_STIMULUS_BITS   (32)
#define	ITM_SP14   *((volatile int32u *)0xE0000038u)
#define	ITM_SP14_REG   *((volatile int32u *)0xE0000038u)
#define	ITM_SP14_ADDR   (0xE0000038u)
#define	ITM_SP14_RESET   (0x00000000u)
#define	ITM_SP14_FIFOREADY   (0x00000001u)
#define	ITM_SP14_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP14_FIFOREADY_BIT   (0)
#define	ITM_SP14_FIFOREADY_BITS   (1)
#define	ITM_SP14_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP14_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP14_STIMULUS_BIT   (0)
#define	ITM_SP14_STIMULUS_BITS   (32)
#define	ITM_SP15   *((volatile int32u *)0xE000003Cu)
#define	ITM_SP15_REG   *((volatile int32u *)0xE000003Cu)
#define	ITM_SP15_ADDR   (0xE000003Cu)
#define	ITM_SP15_RESET   (0x00000000u)
#define	ITM_SP15_FIFOREADY   (0x00000001u)
#define	ITM_SP15_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP15_FIFOREADY_BIT   (0)
#define	ITM_SP15_FIFOREADY_BITS   (1)
#define	ITM_SP15_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP15_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP15_STIMULUS_BIT   (0)
#define	ITM_SP15_STIMULUS_BITS   (32)
#define	ITM_SP16   *((volatile int32u *)0xE0000040u)
#define	ITM_SP16_REG   *((volatile int32u *)0xE0000040u)
#define	ITM_SP16_ADDR   (0xE0000040u)
#define	ITM_SP16_RESET   (0x00000000u)
#define	ITM_SP16_FIFOREADY   (0x00000001u)
#define	ITM_SP16_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP16_FIFOREADY_BIT   (0)
#define	ITM_SP16_FIFOREADY_BITS   (1)
#define	ITM_SP16_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP16_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP16_STIMULUS_BIT   (0)
#define	ITM_SP16_STIMULUS_BITS   (32)
#define	ITM_SP17   *((volatile int32u *)0xE0000044u)
#define	ITM_SP17_REG   *((volatile int32u *)0xE0000044u)
#define	ITM_SP17_ADDR   (0xE0000044u)
#define	ITM_SP17_RESET   (0x00000000u)
#define	ITM_SP17_FIFOREADY   (0x00000001u)
#define	ITM_SP17_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP17_FIFOREADY_BIT   (0)
#define	ITM_SP17_FIFOREADY_BITS   (1)
#define	ITM_SP17_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP17_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP17_STIMULUS_BIT   (0)
#define	ITM_SP17_STIMULUS_BITS   (32)
#define	ITM_SP18   *((volatile int32u *)0xE0000048u)
#define	ITM_SP18_REG   *((volatile int32u *)0xE0000048u)
#define	ITM_SP18_ADDR   (0xE0000048u)
#define	ITM_SP18_RESET   (0x00000000u)
#define	ITM_SP18_FIFOREADY   (0x00000001u)
#define	ITM_SP18_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP18_FIFOREADY_BIT   (0)
#define	ITM_SP18_FIFOREADY_BITS   (1)
#define	ITM_SP18_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP18_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP18_STIMULUS_BIT   (0)
#define	ITM_SP18_STIMULUS_BITS   (32)
#define	ITM_SP19   *((volatile int32u *)0xE000004Cu)
#define	ITM_SP19_REG   *((volatile int32u *)0xE000004Cu)
#define	ITM_SP19_ADDR   (0xE000004Cu)
#define	ITM_SP19_RESET   (0x00000000u)
#define	ITM_SP19_FIFOREADY   (0x00000001u)
#define	ITM_SP19_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP19_FIFOREADY_BIT   (0)
#define	ITM_SP19_FIFOREADY_BITS   (1)
#define	ITM_SP19_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP19_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP19_STIMULUS_BIT   (0)
#define	ITM_SP19_STIMULUS_BITS   (32)
#define	ITM_SP20   *((volatile int32u *)0xE0000050u)
#define	ITM_SP20_REG   *((volatile int32u *)0xE0000050u)
#define	ITM_SP20_ADDR   (0xE0000050u)
#define	ITM_SP20_RESET   (0x00000000u)
#define	ITM_SP20_FIFOREADY   (0x00000001u)
#define	ITM_SP20_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP20_FIFOREADY_BIT   (0)
#define	ITM_SP20_FIFOREADY_BITS   (1)
#define	ITM_SP20_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP20_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP20_STIMULUS_BIT   (0)
#define	ITM_SP20_STIMULUS_BITS   (32)
#define	ITM_SP21   *((volatile int32u *)0xE0000054u)
#define	ITM_SP21_REG   *((volatile int32u *)0xE0000054u)
#define	ITM_SP21_ADDR   (0xE0000054u)
#define	ITM_SP21_RESET   (0x00000000u)
#define	ITM_SP21_FIFOREADY   (0x00000001u)
#define	ITM_SP21_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP21_FIFOREADY_BIT   (0)
#define	ITM_SP21_FIFOREADY_BITS   (1)
#define	ITM_SP21_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP21_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP21_STIMULUS_BIT   (0)
#define	ITM_SP21_STIMULUS_BITS   (32)
#define	ITM_SP22   *((volatile int32u *)0xE0000058u)
#define	ITM_SP22_REG   *((volatile int32u *)0xE0000058u)
#define	ITM_SP22_ADDR   (0xE0000058u)
#define	ITM_SP22_RESET   (0x00000000u)
#define	ITM_SP22_FIFOREADY   (0x00000001u)
#define	ITM_SP22_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP22_FIFOREADY_BIT   (0)
#define	ITM_SP22_FIFOREADY_BITS   (1)
#define	ITM_SP22_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP22_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP22_STIMULUS_BIT   (0)
#define	ITM_SP22_STIMULUS_BITS   (32)
#define	ITM_SP23   *((volatile int32u *)0xE000005Cu)
#define	ITM_SP23_REG   *((volatile int32u *)0xE000005Cu)
#define	ITM_SP23_ADDR   (0xE000005Cu)
#define	ITM_SP23_RESET   (0x00000000u)
#define	ITM_SP23_FIFOREADY   (0x00000001u)
#define	ITM_SP23_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP23_FIFOREADY_BIT   (0)
#define	ITM_SP23_FIFOREADY_BITS   (1)
#define	ITM_SP23_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP23_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP23_STIMULUS_BIT   (0)
#define	ITM_SP23_STIMULUS_BITS   (32)
#define	ITM_SP24   *((volatile int32u *)0xE0000060u)
#define	ITM_SP24_REG   *((volatile int32u *)0xE0000060u)
#define	ITM_SP24_ADDR   (0xE0000060u)
#define	ITM_SP24_RESET   (0x00000000u)
#define	ITM_SP24_FIFOREADY   (0x00000001u)
#define	ITM_SP24_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP24_FIFOREADY_BIT   (0)
#define	ITM_SP24_FIFOREADY_BITS   (1)
#define	ITM_SP24_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP24_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP24_STIMULUS_BIT   (0)
#define	ITM_SP24_STIMULUS_BITS   (32)
#define	ITM_SP25   *((volatile int32u *)0xE0000064u)
#define	ITM_SP25_REG   *((volatile int32u *)0xE0000064u)
#define	ITM_SP25_ADDR   (0xE0000064u)
#define	ITM_SP25_RESET   (0x00000000u)
#define	ITM_SP25_FIFOREADY   (0x00000001u)
#define	ITM_SP25_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP25_FIFOREADY_BIT   (0)
#define	ITM_SP25_FIFOREADY_BITS   (1)
#define	ITM_SP25_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP25_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP25_STIMULUS_BIT   (0)
#define	ITM_SP25_STIMULUS_BITS   (32)
#define	ITM_SP26   *((volatile int32u *)0xE0000068u)
#define	ITM_SP26_REG   *((volatile int32u *)0xE0000068u)
#define	ITM_SP26_ADDR   (0xE0000068u)
#define	ITM_SP26_RESET   (0x00000000u)
#define	ITM_SP26_FIFOREADY   (0x00000001u)
#define	ITM_SP26_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP26_FIFOREADY_BIT   (0)
#define	ITM_SP26_FIFOREADY_BITS   (1)
#define	ITM_SP26_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP26_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP26_STIMULUS_BIT   (0)
#define	ITM_SP26_STIMULUS_BITS   (32)
#define	ITM_SP27   *((volatile int32u *)0xE000006Cu)
#define	ITM_SP27_REG   *((volatile int32u *)0xE000006Cu)
#define	ITM_SP27_ADDR   (0xE000006Cu)
#define	ITM_SP27_RESET   (0x00000000u)
#define	ITM_SP27_FIFOREADY   (0x00000001u)
#define	ITM_SP27_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP27_FIFOREADY_BIT   (0)
#define	ITM_SP27_FIFOREADY_BITS   (1)
#define	ITM_SP27_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP27_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP27_STIMULUS_BIT   (0)
#define	ITM_SP27_STIMULUS_BITS   (32)
#define	ITM_SP28   *((volatile int32u *)0xE0000070u)
#define	ITM_SP28_REG   *((volatile int32u *)0xE0000070u)
#define	ITM_SP28_ADDR   (0xE0000070u)
#define	ITM_SP28_RESET   (0x00000000u)
#define	ITM_SP28_FIFOREADY   (0x00000001u)
#define	ITM_SP28_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP28_FIFOREADY_BIT   (0)
#define	ITM_SP28_FIFOREADY_BITS   (1)
#define	ITM_SP28_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP28_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP28_STIMULUS_BIT   (0)
#define	ITM_SP28_STIMULUS_BITS   (32)
#define	ITM_SP29   *((volatile int32u *)0xE0000074u)
#define	ITM_SP29_REG   *((volatile int32u *)0xE0000074u)
#define	ITM_SP29_ADDR   (0xE0000074u)
#define	ITM_SP29_RESET   (0x00000000u)
#define	ITM_SP29_FIFOREADY   (0x00000001u)
#define	ITM_SP29_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP29_FIFOREADY_BIT   (0)
#define	ITM_SP29_FIFOREADY_BITS   (1)
#define	ITM_SP29_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP29_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP29_STIMULUS_BIT   (0)
#define	ITM_SP29_STIMULUS_BITS   (32)
#define	ITM_SP30   *((volatile int32u *)0xE0000078u)
#define	ITM_SP30_REG   *((volatile int32u *)0xE0000078u)
#define	ITM_SP30_ADDR   (0xE0000078u)
#define	ITM_SP30_RESET   (0x00000000u)
#define	ITM_SP30_FIFOREADY   (0x00000001u)
#define	ITM_SP30_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP30_FIFOREADY_BIT   (0)
#define	ITM_SP30_FIFOREADY_BITS   (1)
#define	ITM_SP30_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP30_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP30_STIMULUS_BIT   (0)
#define	ITM_SP30_STIMULUS_BITS   (32)
#define	ITM_SP31   *((volatile int32u *)0xE000007Cu)
#define	ITM_SP31_REG   *((volatile int32u *)0xE000007Cu)
#define	ITM_SP31_ADDR   (0xE000007Cu)
#define	ITM_SP31_RESET   (0x00000000u)
#define	ITM_SP31_FIFOREADY   (0x00000001u)
#define	ITM_SP31_FIFOREADY_MASK   (0x00000001u)
#define	ITM_SP31_FIFOREADY_BIT   (0)
#define	ITM_SP31_FIFOREADY_BITS   (1)
#define	ITM_SP31_STIMULUS   (0xFFFFFFFFu)
#define	ITM_SP31_STIMULUS_MASK   (0xFFFFFFFFu)
#define	ITM_SP31_STIMULUS_BIT   (0)
#define	ITM_SP31_STIMULUS_BITS   (32)
#define	ITM_TER   *((volatile int32u *)0xE0000E00u)
#define	ITM_TER_REG   *((volatile int32u *)0xE0000E00u)
#define	ITM_TER_ADDR   (0xE0000E00u)
#define	ITM_TER_RESET   (0x00000000u)
#define	ITM_TER_STIMENA   (0xFFFFFFFFu)
#define	ITM_TER_STIMENA_MASK   (0xFFFFFFFFu)
#define	ITM_TER_STIMENA_BIT   (0)
#define	ITM_TER_STIMENA_BITS   (32)
#define	ITM_TPR   *((volatile int32u *)0xE0000E40u)
#define	ITM_TPR_REG   *((volatile int32u *)0xE0000E40u)
#define	ITM_TPR_ADDR   (0xE0000E40u)
#define	ITM_TPR_RESET   (0x00000000u)
#define	ITM_TPR_PRIVMASK   (0x0000000Fu)
#define	ITM_TPR_PRIVMASK_MASK   (0x0000000Fu)
#define	ITM_TPR_PRIVMASK_BIT   (0)
#define	ITM_TPR_PRIVMASK_BITS   (4)
#define	ITM_TCR   *((volatile int32u *)0xE0000E80u)
#define	ITM_TCR_REG   *((volatile int32u *)0xE0000E80u)
#define	ITM_TCR_ADDR   (0xE0000E80u)
#define	ITM_TCR_RESET   (0x00000000u)
#define	ITM_TCR_BUSY   (0x00800000u)
#define	ITM_TCR_BUSY_MASK   (0x00800000u)
#define	ITM_TCR_BUSY_BIT   (23)
#define	ITM_TCR_BUSY_BITS   (1)
#define	ITM_TCR_ATBID   (0x007F0000u)
#define	ITM_TCR_ATBID_MASK   (0x007F0000u)
#define	ITM_TCR_ATBID_BIT   (16)
#define	ITM_TCR_ATBID_BITS   (7)
#define	ITM_TCR_TSPRESCALE   (0x00000300u)
#define	ITM_TCR_TSPRESCALE_MASK   (0x00000300u)
#define	ITM_TCR_TSPRESCALE_BIT   (8)
#define	ITM_TCR_TSPRESCALE_BITS   (2)
#define	ITM_TCR_SWOENA   (0x00000010u)
#define	ITM_TCR_SWOENA_MASK   (0x00000010u)
#define	ITM_TCR_SWOENA_BIT   (4)
#define	ITM_TCR_SWOENA_BITS   (1)
#define	ITM_TCR_DWTENA   (0x00000008u)
#define	ITM_TCR_DWTENA_MASK   (0x00000008u)
#define	ITM_TCR_DWTENA_BIT   (3)
#define	ITM_TCR_DWTENA_BITS   (1)
#define	ITM_TCR_SYNCENA   (0x00000004u)
#define	ITM_TCR_SYNCENA_MASK   (0x00000004u)
#define	ITM_TCR_SYNCENA_BIT   (2)
#define	ITM_TCR_SYNCENA_BITS   (1)
#define	ITM_TCR_TSENA   (0x00000002u)
#define	ITM_TCR_TSENA_MASK   (0x00000002u)
#define	ITM_TCR_TSENA_BIT   (1)
#define	ITM_TCR_TSENA_BITS   (1)
#define	ITM_TCR_ITMEN   (0x00000001u)
#define	ITM_TCR_ITMEN_MASK   (0x00000001u)
#define	ITM_TCR_ITMEN_BIT   (0)
#define	ITM_TCR_ITMEN_BITS   (1)
#define	ITM_IW   *((volatile int32u *)0xE0000EF8u)
#define	ITM_IW_REG   *((volatile int32u *)0xE0000EF8u)
#define	ITM_IW_ADDR   (0xE0000EF8u)
#define	ITM_IW_RESET   (0x00000000u)
#define	ITM_IW_ATVALIDM   (0x00000001u)
#define	ITM_IW_ATVALIDM_MASK   (0x00000001u)
#define	ITM_IW_ATVALIDM_BIT   (0)
#define	ITM_IW_ATVALIDM_BITS   (1)
#define	ITM_IR   *((volatile int32u *)0xE0000EFCu)
#define	ITM_IR_REG   *((volatile int32u *)0xE0000EFCu)
#define	ITM_IR_ADDR   (0xE0000EFCu)
#define	ITM_IR_RESET   (0x00000000u)
#define	ITM_IR_ATREADYM   (0x00000001u)
#define	ITM_IR_ATREADYM_MASK   (0x00000001u)
#define	ITM_IR_ATREADYM_BIT   (0)
#define	ITM_IR_ATREADYM_BITS   (1)
#define	ITM_IMC   *((volatile int32u *)0xE0000F00u)
#define	ITM_IMC_REG   *((volatile int32u *)0xE0000F00u)
#define	ITM_IMC_ADDR   (0xE0000F00u)
#define	ITM_IMC_RESET   (0x00000000u)
#define	ITM_IMC_INTEGRATION   (0x00000001u)
#define	ITM_IMC_INTEGRATION_MASK   (0x00000001u)
#define	ITM_IMC_INTEGRATION_BIT   (0)
#define	ITM_IMC_INTEGRATION_BITS   (1)
#define	ITM_LA   *((volatile int32u *)0xE0000FB0u)
#define	ITM_LA_REG   *((volatile int32u *)0xE0000FB0u)
#define	ITM_LA_ADDR   (0xE0000FB0u)
#define	ITM_LA_RESET   (0x00000000u)
#define	ITM_LA_LOCKACC   (0xFFFFFFFFu)
#define	ITM_LA_LOCKACC_MASK   (0xFFFFFFFFu)
#define	ITM_LA_LOCKACC_BIT   (0)
#define	ITM_LA_LOCKACC_BITS   (32)
#define	ITM_LS   *((volatile int32u *)0xE0000FB4u)
#define	ITM_LS_REG   *((volatile int32u *)0xE0000FB4u)
#define	ITM_LS_ADDR   (0xE0000FB4u)
#define	ITM_LS_RESET   (0x00000000u)
#define	ITM_LS_BYTEACC   (0x00000004u)
#define	ITM_LS_BYTEACC_MASK   (0x00000004u)
#define	ITM_LS_BYTEACC_BIT   (2)
#define	ITM_LS_BYTEACC_BITS   (1)
#define	ITM_LS_ACCESS   (0x00000002u)
#define	ITM_LS_ACCESS_MASK   (0x00000002u)
#define	ITM_LS_ACCESS_BIT   (1)
#define	ITM_LS_ACCESS_BITS   (1)
#define	ITM_LS_PRESENT   (0x00000001u)
#define	ITM_LS_PRESENT_MASK   (0x00000001u)
#define	ITM_LS_PRESENT_BIT   (0)
#define	ITM_LS_PRESENT_BITS   (1)
#define	ITM_PERIPHID4   *((volatile int32u *)0xE0000FD0u)
#define	ITM_PERIPHID4_REG   *((volatile int32u *)0xE0000FD0u)
#define	ITM_PERIPHID4_ADDR   (0xE0000FD0u)
#define	ITM_PERIPHID4_RESET   (0x00000004u)
#define	ITM_PERIPHID4_PERIPHID   (0xFFFFFFFFu)
#define	ITM_PERIPHID4_PERIPHID_MASK   (0xFFFFFFFFu)
#define	ITM_PERIPHID4_PERIPHID_BIT   (0)
#define	ITM_PERIPHID4_PERIPHID_BITS   (32)
#define	ITM_PERIPHID5   *((volatile int32u *)0xE0000FD4u)
#define	ITM_PERIPHID5_REG   *((volatile int32u *)0xE0000FD4u)
#define	ITM_PERIPHID5_ADDR   (0xE0000FD4u)
#define	ITM_PERIPHID5_RESET   (0x00000000u)
#define	ITM_PERIPHID5_PERIPHID   (0xFFFFFFFFu)
#define	ITM_PERIPHID5_PERIPHID_MASK   (0xFFFFFFFFu)
#define	ITM_PERIPHID5_PERIPHID_BIT   (0)
#define	ITM_PERIPHID5_PERIPHID_BITS   (32)
#define	ITM_PERIPHID6   *((volatile int32u *)0xE0000FD8u)
#define	ITM_PERIPHID6_REG   *((volatile int32u *)0xE0000FD8u)
#define	ITM_PERIPHID6_ADDR   (0xE0000FD8u)
#define	ITM_PERIPHID6_RESET   (0x00000000u)
#define	ITM_PERIPHID6_PERIPHID   (0xFFFFFFFFu)
#define	ITM_PERIPHID6_PERIPHID_MASK   (0xFFFFFFFFu)
#define	ITM_PERIPHID6_PERIPHID_BIT   (0)
#define	ITM_PERIPHID6_PERIPHID_BITS   (32)
#define	ITM_PERIPHID7   *((volatile int32u *)0xE0000FDCu)
#define	ITM_PERIPHID7_REG   *((volatile int32u *)0xE0000FDCu)
#define	ITM_PERIPHID7_ADDR   (0xE0000FDCu)
#define	ITM_PERIPHID7_RESET   (0x00000000u)
#define	ITM_PERIPHID7_PERIPHID   (0xFFFFFFFFu)
#define	ITM_PERIPHID7_PERIPHID_MASK   (0xFFFFFFFFu)
#define	ITM_PERIPHID7_PERIPHID_BIT   (0)
#define	ITM_PERIPHID7_PERIPHID_BITS   (32)
#define	ITM_PERIPHID0   *((volatile int32u *)0xE0000FE0u)
#define	ITM_PERIPHID0_REG   *((volatile int32u *)0xE0000FE0u)
#define	ITM_PERIPHID0_ADDR   (0xE0000FE0u)
#define	ITM_PERIPHID0_RESET   (0x00000001u)
#define	ITM_PERIPHID0_PERIPHID   (0xFFFFFFFFu)
#define	ITM_PERIPHID0_PERIPHID_MASK   (0xFFFFFFFFu)
#define	ITM_PERIPHID0_PERIPHID_BIT   (0)
#define	ITM_PERIPHID0_PERIPHID_BITS   (32)
#define	ITM_PERIPHID1   *((volatile int32u *)0xE0000FE4u)
#define	ITM_PERIPHID1_REG   *((volatile int32u *)0xE0000FE4u)
#define	ITM_PERIPHID1_ADDR   (0xE0000FE4u)
#define	ITM_PERIPHID1_RESET   (0x000000B0u)
#define	ITM_PERIPHID1_PERIPHID   (0xFFFFFFFFu)
#define	ITM_PERIPHID1_PERIPHID_MASK   (0xFFFFFFFFu)
#define	ITM_PERIPHID1_PERIPHID_BIT   (0)
#define	ITM_PERIPHID1_PERIPHID_BITS   (32)
#define	ITM_PERIPHID2   *((volatile int32u *)0xE0000FE8u)
#define	ITM_PERIPHID2_REG   *((volatile int32u *)0xE0000FE8u)
#define	ITM_PERIPHID2_ADDR   (0xE0000FE8u)
#define	ITM_PERIPHID2_RESET   (0x0000001Bu)
#define	ITM_PERIPHID2_PERIPHID   (0xFFFFFFFFu)
#define	ITM_PERIPHID2_PERIPHID_MASK   (0xFFFFFFFFu)
#define	ITM_PERIPHID2_PERIPHID_BIT   (0)
#define	ITM_PERIPHID2_PERIPHID_BITS   (32)
#define	ITM_PERIPHID3   *((volatile int32u *)0xE0000FECu)
#define	ITM_PERIPHID3_REG   *((volatile int32u *)0xE0000FECu)
#define	ITM_PERIPHID3_ADDR   (0xE0000FECu)
#define	ITM_PERIPHID3_RESET   (0x00000000u)
#define	ITM_PERIPHID3_PERIPHID   (0xFFFFFFFFu)
#define	ITM_PERIPHID3_PERIPHID_MASK   (0xFFFFFFFFu)
#define	ITM_PERIPHID3_PERIPHID_BIT   (0)
#define	ITM_PERIPHID3_PERIPHID_BITS   (32)
#define	ITM_CELLID0   *((volatile int32u *)0xE0000FF0u)
#define	ITM_CELLID0_REG   *((volatile int32u *)0xE0000FF0u)
#define	ITM_CELLID0_ADDR   (0xE0000FF0u)
#define	ITM_CELLID0_RESET   (0x0000000Du)
#define	ITM_CELLID0_PERIPHID   (0xFFFFFFFFu)
#define	ITM_CELLID0_PERIPHID_MASK   (0xFFFFFFFFu)
#define	ITM_CELLID0_PERIPHID_BIT   (0)
#define	ITM_CELLID0_PERIPHID_BITS   (32)
#define	ITM_CELLID1   *((volatile int32u *)0xE0000FF4u)
#define	ITM_CELLID1_REG   *((volatile int32u *)0xE0000FF4u)
#define	ITM_CELLID1_ADDR   (0xE0000FF4u)
#define	ITM_CELLID1_RESET   (0x000000E0u)
#define	ITM_CELLID1_PERIPHID   (0xFFFFFFFFu)
#define	ITM_CELLID1_PERIPHID_MASK   (0xFFFFFFFFu)
#define	ITM_CELLID1_PERIPHID_BIT   (0)
#define	ITM_CELLID1_PERIPHID_BITS   (32)
#define	ITM_CELLID2   *((volatile int32u *)0xE0000FF8u)
#define	ITM_CELLID2_REG   *((volatile int32u *)0xE0000FF8u)
#define	ITM_CELLID2_ADDR   (0xE0000FF8u)
#define	ITM_CELLID2_RESET   (0x00000005u)
#define	ITM_CELLID2_PERIPHID   (0xFFFFFFFFu)
#define	ITM_CELLID2_PERIPHID_MASK   (0xFFFFFFFFu)
#define	ITM_CELLID2_PERIPHID_BIT   (0)
#define	ITM_CELLID2_PERIPHID_BITS   (32)
#define	ITM_CELLID3   *((volatile int32u *)0xE0000FFCu)
#define	ITM_CELLID3_REG   *((volatile int32u *)0xE0000FFCu)
#define	ITM_CELLID3_ADDR   (0xE0000FFCu)
#define	ITM_CELLID3_RESET   (0x000000B1u)
#define	ITM_CELLID3_PERIPHID   (0xFFFFFFFFu)
#define	ITM_CELLID3_PERIPHID_MASK   (0xFFFFFFFFu)
#define	ITM_CELLID3_PERIPHID_BIT   (0)
#define	ITM_CELLID3_PERIPHID_BITS   (32)
#define	DATA_DWT_BASE   (0xE0001000u)
#define	DATA_DWT_END   (0xE0001FFFu)
#define	DATA_DWT_SIZE   (DATA_DWT_END - DATA_DWT_BASE + 1)
#define	DWT_CTRL   *((volatile int32u *)0xE0001000u)
#define	DWT_CTRL_REG   *((volatile int32u *)0xE0001000u)
#define	DWT_CTRL_ADDR   (0xE0001000u)
#define	DWT_CTRL_RESET   (0x40000000u)
#define	DWT_CTRL_NUMCOMP   (0xF0000000u)
#define	DWT_CTRL_NUMCOMP_MASK   (0xF0000000u)
#define	DWT_CTRL_NUMCOMP_BIT   (28)
#define	DWT_CTRL_NUMCOMP_BITS   (4)
#define	DWT_CTRL_CYCEVTENA   (0x00400000u)
#define	DWT_CTRL_CYCEVTENA_MASK   (0x00400000u)
#define	DWT_CTRL_CYCEVTENA_BIT   (22)
#define	DWT_CTRL_CYCEVTENA_BITS   (1)
#define	DWT_CTRL_FOLDEVTENA   (0x00200000u)
#define	DWT_CTRL_FOLDEVTENA_MASK   (0x00200000u)
#define	DWT_CTRL_FOLDEVTENA_BIT   (21)
#define	DWT_CTRL_FOLDEVTENA_BITS   (1)
#define	DWT_CTRL_LSUEVTENA   (0x00100000u)
#define	DWT_CTRL_LSUEVTENA_MASK   (0x00100000u)
#define	DWT_CTRL_LSUEVTENA_BIT   (20)
#define	DWT_CTRL_LSUEVTENA_BITS   (1)
#define	DWT_CTRL_SLEEPEVTENA   (0x00080000u)
#define	DWT_CTRL_SLEEPEVTENA_MASK   (0x00080000u)
#define	DWT_CTRL_SLEEPEVTENA_BIT   (19)
#define	DWT_CTRL_SLEEPEVTENA_BITS   (1)
#define	DWT_CTRL_EXCEVTENA   (0x00040000u)
#define	DWT_CTRL_EXCEVTENA_MASK   (0x00040000u)
#define	DWT_CTRL_EXCEVTENA_BIT   (18)
#define	DWT_CTRL_EXCEVTENA_BITS   (1)
#define	DWT_CTRL_CPIEVTENA   (0x00020000u)
#define	DWT_CTRL_CPIEVTENA_MASK   (0x00020000u)
#define	DWT_CTRL_CPIEVTENA_BIT   (17)
#define	DWT_CTRL_CPIEVTENA_BITS   (1)
#define	DWT_CTRL_EXCTRCENA   (0x00010000u)
#define	DWT_CTRL_EXCTRCENA_MASK   (0x00010000u)
#define	DWT_CTRL_EXCTRCENA_BIT   (16)
#define	DWT_CTRL_EXCTRCENA_BITS   (1)
#define	DWT_CTRL_PCSAMPLEENA   (0x00001000u)
#define	DWT_CTRL_PCSAMPLEENA_MASK   (0x00001000u)
#define	DWT_CTRL_PCSAMPLEENA_BIT   (12)
#define	DWT_CTRL_PCSAMPLEENA_BITS   (1)
#define	DWT_CTRL_SYNCTAP   (0x00000C00u)
#define	DWT_CTRL_SYNCTAP_MASK   (0x00000C00u)
#define	DWT_CTRL_SYNCTAP_BIT   (10)
#define	DWT_CTRL_SYNCTAP_BITS   (2)
#define	DWT_CTRL_CYCTAP   (0x00000200u)
#define	DWT_CTRL_CYCTAP_MASK   (0x00000200u)
#define	DWT_CTRL_CYCTAP_BIT   (9)
#define	DWT_CTRL_CYCTAP_BITS   (1)
#define	DWT_CTRL_POSTCNT   (0x000001E0u)
#define	DWT_CTRL_POSTCNT_MASK   (0x000001E0u)
#define	DWT_CTRL_POSTCNT_BIT   (5)
#define	DWT_CTRL_POSTCNT_BITS   (4)
#define	DWT_CTRL_POSTPRESET   (0x0000001Eu)
#define	DWT_CTRL_POSTPRESET_MASK   (0x0000001Eu)
#define	DWT_CTRL_POSTPRESET_BIT   (1)
#define	DWT_CTRL_POSTPRESET_BITS   (4)
#define	DWT_CTRL_CYCCNTENA   (0x00000001u)
#define	DWT_CTRL_CYCCNTENA_MASK   (0x00000001u)
#define	DWT_CTRL_CYCCNTENA_BIT   (0)
#define	DWT_CTRL_CYCCNTENA_BITS   (1)
#define	DWT_CYCCNT   *((volatile int32u *)0xE0001004u)
#define	DWT_CYCCNT_REG   *((volatile int32u *)0xE0001004u)
#define	DWT_CYCCNT_ADDR   (0xE0001004u)
#define	DWT_CYCCNT_RESET   (0x00000000u)
#define	DWT_CYCCNT_CYCCNT   (0xFFFFFFFFu)
#define	DWT_CYCCNT_CYCCNT_MASK   (0xFFFFFFFFu)
#define	DWT_CYCCNT_CYCCNT_BIT   (0)
#define	DWT_CYCCNT_CYCCNT_BITS   (32)
#define	DWT_CPICNT   *((volatile int32u *)0xE0001008u)
#define	DWT_CPICNT_REG   *((volatile int32u *)0xE0001008u)
#define	DWT_CPICNT_ADDR   (0xE0001008u)
#define	DWT_CPICNT_RESET   (0x00000000u)
#define	DWT_CPICNT_CPICNT   (0x000000FFu)
#define	DWT_CPICNT_CPICNT_MASK   (0x000000FFu)
#define	DWT_CPICNT_CPICNT_BIT   (0)
#define	DWT_CPICNT_CPICNT_BITS   (8)
#define	DWT_EXCCNT   *((volatile int32u *)0xE000100Cu)
#define	DWT_EXCCNT_REG   *((volatile int32u *)0xE000100Cu)
#define	DWT_EXCCNT_ADDR   (0xE000100Cu)
#define	DWT_EXCCNT_RESET   (0x00000000u)
#define	DWT_EXCCNT_EXCCNT   (0x000000FFu)
#define	DWT_EXCCNT_EXCCNT_MASK   (0x000000FFu)
#define	DWT_EXCCNT_EXCCNT_BIT   (0)
#define	DWT_EXCCNT_EXCCNT_BITS   (8)
#define	DWT_SLEEPCNT   *((volatile int32u *)0xE0001010u)
#define	DWT_SLEEPCNT_REG   *((volatile int32u *)0xE0001010u)
#define	DWT_SLEEPCNT_ADDR   (0xE0001010u)
#define	DWT_SLEEPCNT_RESET   (0x00000000u)
#define	DWT_SLEEPCNT_SLEEPCNT   (0x000000FFu)
#define	DWT_SLEEPCNT_SLEEPCNT_MASK   (0x000000FFu)
#define	DWT_SLEEPCNT_SLEEPCNT_BIT   (0)
#define	DWT_SLEEPCNT_SLEEPCNT_BITS   (8)
#define	DWT_LSUCNT   *((volatile int32u *)0xE0001014u)
#define	DWT_LSUCNT_REG   *((volatile int32u *)0xE0001014u)
#define	DWT_LSUCNT_ADDR   (0xE0001014u)
#define	DWT_LSUCNT_RESET   (0x00000000u)
#define	DWT_LSUCNT_CPICNT   (0x000000FFu)
#define	DWT_LSUCNT_CPICNT_MASK   (0x000000FFu)
#define	DWT_LSUCNT_CPICNT_BIT   (0)
#define	DWT_LSUCNT_CPICNT_BITS   (8)
#define	DWT_FOLDCNT   *((volatile int32u *)0xE0001018u)
#define	DWT_FOLDCNT_REG   *((volatile int32u *)0xE0001018u)
#define	DWT_FOLDCNT_ADDR   (0xE0001018u)
#define	DWT_FOLDCNT_RESET   (0x00000000u)
#define	DWT_FOLDCNT_CPICNT   (0x000000FFu)
#define	DWT_FOLDCNT_CPICNT_MASK   (0x000000FFu)
#define	DWT_FOLDCNT_CPICNT_BIT   (0)
#define	DWT_FOLDCNT_CPICNT_BITS   (8)
#define	DWT_PCSR   *((volatile int32u *)0xE000101Cu)
#define	DWT_PCSR_REG   *((volatile int32u *)0xE000101Cu)
#define	DWT_PCSR_ADDR   (0xE000101Cu)
#define	DWT_PCSR_RESET   (0x00000000u)
#define	DWT_PCSR_EIASAMPLE   (0xFFFFFFFFu)
#define	DWT_PCSR_EIASAMPLE_MASK   (0xFFFFFFFFu)
#define	DWT_PCSR_EIASAMPLE_BIT   (0)
#define	DWT_PCSR_EIASAMPLE_BITS   (32)
#define	DWT_COMP0   *((volatile int32u *)0xE0001020u)
#define	DWT_COMP0_REG   *((volatile int32u *)0xE0001020u)
#define	DWT_COMP0_ADDR   (0xE0001020u)
#define	DWT_COMP0_RESET   (0x00000000u)
#define	DWT_COMP0_COMP0   (0xFFFFFFFFu)
#define	DWT_COMP0_COMP0_MASK   (0xFFFFFFFFu)
#define	DWT_COMP0_COMP0_BIT   (0)
#define	DWT_COMP0_COMP0_BITS   (32)
#define	DWT_MASK0   *((volatile int32u *)0xE0001024u)
#define	DWT_MASK0_REG   *((volatile int32u *)0xE0001024u)
#define	DWT_MASK0_ADDR   (0xE0001024u)
#define	DWT_MASK0_RESET   (0x00000000u)
#define	DWT_MASK0_MASK0   (0x0000001Fu)
#define	DWT_MASK0_MASK0_MASK   (0x0000001Fu)
#define	DWT_MASK0_MASK0_BIT   (0)
#define	DWT_MASK0_MASK0_BITS   (5)
#define	DWT_FUNCTION0   *((volatile int32u *)0xE0001028u)
#define	DWT_FUNCTION0_REG   *((volatile int32u *)0xE0001028u)
#define	DWT_FUNCTION0_ADDR   (0xE0001028u)
#define	DWT_FUNCTION0_RESET   (0x00000000u)
#define	DWT_FUNCTION0_MATCHED   (0x01000000u)
#define	DWT_FUNCTION0_MATCHED_MASK   (0x01000000u)
#define	DWT_FUNCTION0_MATCHED_BIT   (24)
#define	DWT_FUNCTION0_MATCHED_BITS   (1)
#define	DWT_FUNCTION0_CYCMATCH   (0x00000080u)
#define	DWT_FUNCTION0_CYCMATCH_MASK   (0x00000080u)
#define	DWT_FUNCTION0_CYCMATCH_BIT   (7)
#define	DWT_FUNCTION0_CYCMATCH_BITS   (1)
#define	DWT_FUNCTION0_EMITRANGE   (0x00000020u)
#define	DWT_FUNCTION0_EMITRANGE_MASK   (0x00000020u)
#define	DWT_FUNCTION0_EMITRANGE_BIT   (5)
#define	DWT_FUNCTION0_EMITRANGE_BITS   (1)
#define	DWT_FUNCTION0_FUNCTION   (0x0000000Fu)
#define	DWT_FUNCTION0_FUNCTION_MASK   (0x0000000Fu)
#define	DWT_FUNCTION0_FUNCTION_BIT   (0)
#define	DWT_FUNCTION0_FUNCTION_BITS   (4)
#define	DWT_COMP1   *((volatile int32u *)0xE0001030u)
#define	DWT_COMP1_REG   *((volatile int32u *)0xE0001030u)
#define	DWT_COMP1_ADDR   (0xE0001030u)
#define	DWT_COMP1_RESET   (0x00000000u)
#define	DWT_COMP1_COMP1   (0xFFFFFFFFu)
#define	DWT_COMP1_COMP1_MASK   (0xFFFFFFFFu)
#define	DWT_COMP1_COMP1_BIT   (0)
#define	DWT_COMP1_COMP1_BITS   (32)
#define	DWT_MASK1   *((volatile int32u *)0xE0001034u)
#define	DWT_MASK1_REG   *((volatile int32u *)0xE0001034u)
#define	DWT_MASK1_ADDR   (0xE0001034u)
#define	DWT_MASK1_RESET   (0x00000000u)
#define	DWT_MASK1_MASK1   (0x0000001Fu)
#define	DWT_MASK1_MASK1_MASK   (0x0000001Fu)
#define	DWT_MASK1_MASK1_BIT   (0)
#define	DWT_MASK1_MASK1_BITS   (5)
#define	DWT_FUNCTION1   *((volatile int32u *)0xE0001038u)
#define	DWT_FUNCTION1_REG   *((volatile int32u *)0xE0001038u)
#define	DWT_FUNCTION1_ADDR   (0xE0001038u)
#define	DWT_FUNCTION1_RESET   (0x00000200u)
#define	DWT_FUNCTION1_MATCHED   (0x01000000u)
#define	DWT_FUNCTION1_MATCHED_MASK   (0x01000000u)
#define	DWT_FUNCTION1_MATCHED_BIT   (24)
#define	DWT_FUNCTION1_MATCHED_BITS   (1)
#define	DWT_FUNCTION1_DATAVADDR1   (0x000F0000u)
#define	DWT_FUNCTION1_DATAVADDR1_MASK   (0x000F0000u)
#define	DWT_FUNCTION1_DATAVADDR1_BIT   (16)
#define	DWT_FUNCTION1_DATAVADDR1_BITS   (4)
#define	DWT_FUNCTION1_DATAVADDR0   (0x0000F000u)
#define	DWT_FUNCTION1_DATAVADDR0_MASK   (0x0000F000u)
#define	DWT_FUNCTION1_DATAVADDR0_BIT   (12)
#define	DWT_FUNCTION1_DATAVADDR0_BITS   (4)
#define	DWT_FUNCTION1_DATAVSIZE   (0x00000C00u)
#define	DWT_FUNCTION1_DATAVSIZE_MASK   (0x00000C00u)
#define	DWT_FUNCTION1_DATAVSIZE_BIT   (10)
#define	DWT_FUNCTION1_DATAVSIZE_BITS   (2)
#define	DWT_FUNCTION1_LNK1ENA   (0x00000200u)
#define	DWT_FUNCTION1_LNK1ENA_MASK   (0x00000200u)
#define	DWT_FUNCTION1_LNK1ENA_BIT   (9)
#define	DWT_FUNCTION1_LNK1ENA_BITS   (1)
#define	DWT_FUNCTION1_DATAVMATCH   (0x00000100u)
#define	DWT_FUNCTION1_DATAVMATCH_MASK   (0x00000100u)
#define	DWT_FUNCTION1_DATAVMATCH_BIT   (8)
#define	DWT_FUNCTION1_DATAVMATCH_BITS   (1)
#define	DWT_FUNCTION1_EMITRANGE   (0x00000020u)
#define	DWT_FUNCTION1_EMITRANGE_MASK   (0x00000020u)
#define	DWT_FUNCTION1_EMITRANGE_BIT   (5)
#define	DWT_FUNCTION1_EMITRANGE_BITS   (1)
#define	DWT_FUNCTION1_FUNCTION   (0x0000000Fu)
#define	DWT_FUNCTION1_FUNCTION_MASK   (0x0000000Fu)
#define	DWT_FUNCTION1_FUNCTION_BIT   (0)
#define	DWT_FUNCTION1_FUNCTION_BITS   (4)
#define	DWT_COMP2   *((volatile int32u *)0xE0001040u)
#define	DWT_COMP2_REG   *((volatile int32u *)0xE0001040u)
#define	DWT_COMP2_ADDR   (0xE0001040u)
#define	DWT_COMP2_RESET   (0x00000000u)
#define	DWT_COMP2_COMP2   (0xFFFFFFFFu)
#define	DWT_COMP2_COMP2_MASK   (0xFFFFFFFFu)
#define	DWT_COMP2_COMP2_BIT   (0)
#define	DWT_COMP2_COMP2_BITS   (32)
#define	DWT_MASK2   *((volatile int32u *)0xE0001044u)
#define	DWT_MASK2_REG   *((volatile int32u *)0xE0001044u)
#define	DWT_MASK2_ADDR   (0xE0001044u)
#define	DWT_MASK2_RESET   (0x00000000u)
#define	DWT_MASK2_MASK2   (0x0000001Fu)
#define	DWT_MASK2_MASK2_MASK   (0x0000001Fu)
#define	DWT_MASK2_MASK2_BIT   (0)
#define	DWT_MASK2_MASK2_BITS   (5)
#define	DWT_FUNCTION2   *((volatile int32u *)0xE0001048u)
#define	DWT_FUNCTION2_REG   *((volatile int32u *)0xE0001048u)
#define	DWT_FUNCTION2_ADDR   (0xE0001048u)
#define	DWT_FUNCTION2_RESET   (0x00000000u)
#define	DWT_FUNCTION2_MATCHED   (0x01000000u)
#define	DWT_FUNCTION2_MATCHED_MASK   (0x01000000u)
#define	DWT_FUNCTION2_MATCHED_BIT   (24)
#define	DWT_FUNCTION2_MATCHED_BITS   (1)
#define	DWT_FUNCTION2_EMITRANGE   (0x00000020u)
#define	DWT_FUNCTION2_EMITRANGE_MASK   (0x00000020u)
#define	DWT_FUNCTION2_EMITRANGE_BIT   (5)
#define	DWT_FUNCTION2_EMITRANGE_BITS   (1)
#define	DWT_FUNCTION2_FUNCTION   (0x0000000Fu)
#define	DWT_FUNCTION2_FUNCTION_MASK   (0x0000000Fu)
#define	DWT_FUNCTION2_FUNCTION_BIT   (0)
#define	DWT_FUNCTION2_FUNCTION_BITS   (4)
#define	DWT_COMP3   *((volatile int32u *)0xE0001050u)
#define	DWT_COMP3_REG   *((volatile int32u *)0xE0001050u)
#define	DWT_COMP3_ADDR   (0xE0001050u)
#define	DWT_COMP3_RESET   (0x00000000u)
#define	DWT_COMP3_COMP3   (0xFFFFFFFFu)
#define	DWT_COMP3_COMP3_MASK   (0xFFFFFFFFu)
#define	DWT_COMP3_COMP3_BIT   (0)
#define	DWT_COMP3_COMP3_BITS   (32)
#define	DWT_MASK3   *((volatile int32u *)0xE0001054u)
#define	DWT_MASK3_REG   *((volatile int32u *)0xE0001054u)
#define	DWT_MASK3_ADDR   (0xE0001054u)
#define	DWT_MASK3_RESET   (0x00000000u)
#define	DWT_MASK3_MASK3   (0x0000001Fu)
#define	DWT_MASK3_MASK3_MASK   (0x0000001Fu)
#define	DWT_MASK3_MASK3_BIT   (0)
#define	DWT_MASK3_MASK3_BITS   (5)
#define	DWT_FUNCTION3   *((volatile int32u *)0xE0001058u)
#define	DWT_FUNCTION3_REG   *((volatile int32u *)0xE0001058u)
#define	DWT_FUNCTION3_ADDR   (0xE0001058u)
#define	DWT_FUNCTION3_RESET   (0x00000000u)
#define	DWT_FUNCTION3_MATCHED   (0x01000000u)
#define	DWT_FUNCTION3_MATCHED_MASK   (0x01000000u)
#define	DWT_FUNCTION3_MATCHED_BIT   (24)
#define	DWT_FUNCTION3_MATCHED_BITS   (1)
#define	DWT_FUNCTION3_EMITRANGE   (0x00000020u)
#define	DWT_FUNCTION3_EMITRANGE_MASK   (0x00000020u)
#define	DWT_FUNCTION3_EMITRANGE_BIT   (5)
#define	DWT_FUNCTION3_EMITRANGE_BITS   (1)
#define	DWT_FUNCTION3_FUNCTION   (0x0000000Fu)
#define	DWT_FUNCTION3_FUNCTION_MASK   (0x0000000Fu)
#define	DWT_FUNCTION3_FUNCTION_BIT   (0)
#define	DWT_FUNCTION3_FUNCTION_BITS   (4)
#define	DWT_PERIPHID4   *((volatile int32u *)0xE0001FD0u)
#define	DWT_PERIPHID4_REG   *((volatile int32u *)0xE0001FD0u)
#define	DWT_PERIPHID4_ADDR   (0xE0001FD0u)
#define	DWT_PERIPHID4_RESET   (0x00000004u)
#define	DWT_PERIPHID4_PERIPHID   (0xFFFFFFFFu)
#define	DWT_PERIPHID4_PERIPHID_MASK   (0xFFFFFFFFu)
#define	DWT_PERIPHID4_PERIPHID_BIT   (0)
#define	DWT_PERIPHID4_PERIPHID_BITS   (32)
#define	DWT_PERIPHID5   *((volatile int32u *)0xE0001FD4u)
#define	DWT_PERIPHID5_REG   *((volatile int32u *)0xE0001FD4u)
#define	DWT_PERIPHID5_ADDR   (0xE0001FD4u)
#define	DWT_PERIPHID5_RESET   (0x00000000u)
#define	DWT_PERIPHID5_PERIPHID   (0xFFFFFFFFu)
#define	DWT_PERIPHID5_PERIPHID_MASK   (0xFFFFFFFFu)
#define	DWT_PERIPHID5_PERIPHID_BIT   (0)
#define	DWT_PERIPHID5_PERIPHID_BITS   (32)
#define	DWT_PERIPHID6   *((volatile int32u *)0xE0001FD8u)
#define	DWT_PERIPHID6_REG   *((volatile int32u *)0xE0001FD8u)
#define	DWT_PERIPHID6_ADDR   (0xE0001FD8u)
#define	DWT_PERIPHID6_RESET   (0x00000000u)
#define	DWT_PERIPHID6_PERIPHID   (0xFFFFFFFFu)
#define	DWT_PERIPHID6_PERIPHID_MASK   (0xFFFFFFFFu)
#define	DWT_PERIPHID6_PERIPHID_BIT   (0)
#define	DWT_PERIPHID6_PERIPHID_BITS   (32)
#define	DWT_PERIPHID7   *((volatile int32u *)0xE0001FDCu)
#define	DWT_PERIPHID7_REG   *((volatile int32u *)0xE0001FDCu)
#define	DWT_PERIPHID7_ADDR   (0xE0001FDCu)
#define	DWT_PERIPHID7_RESET   (0x00000000u)
#define	DWT_PERIPHID7_PERIPHID   (0xFFFFFFFFu)
#define	DWT_PERIPHID7_PERIPHID_MASK   (0xFFFFFFFFu)
#define	DWT_PERIPHID7_PERIPHID_BIT   (0)
#define	DWT_PERIPHID7_PERIPHID_BITS   (32)
#define	DWT_PERIPHID0   *((volatile int32u *)0xE0001FE0u)
#define	DWT_PERIPHID0_REG   *((volatile int32u *)0xE0001FE0u)
#define	DWT_PERIPHID0_ADDR   (0xE0001FE0u)
#define	DWT_PERIPHID0_RESET   (0x00000002u)
#define	DWT_PERIPHID0_PERIPHID   (0xFFFFFFFFu)
#define	DWT_PERIPHID0_PERIPHID_MASK   (0xFFFFFFFFu)
#define	DWT_PERIPHID0_PERIPHID_BIT   (0)
#define	DWT_PERIPHID0_PERIPHID_BITS   (32)
#define	DWT_PERIPHID1   *((volatile int32u *)0xE0001FE4u)
#define	DWT_PERIPHID1_REG   *((volatile int32u *)0xE0001FE4u)
#define	DWT_PERIPHID1_ADDR   (0xE0001FE4u)
#define	DWT_PERIPHID1_RESET   (0x00000000u)
#define	DWT_PERIPHID1_PERIPHID   (0xFFFFFFFFu)
#define	DWT_PERIPHID1_PERIPHID_MASK   (0xFFFFFFFFu)
#define	DWT_PERIPHID1_PERIPHID_BIT   (0)
#define	DWT_PERIPHID1_PERIPHID_BITS   (32)
#define	DWT_PERIPHID2   *((volatile int32u *)0xE0001FE8u)
#define	DWT_PERIPHID2_REG   *((volatile int32u *)0xE0001FE8u)
#define	DWT_PERIPHID2_ADDR   (0xE0001FE8u)
#define	DWT_PERIPHID2_RESET   (0x0000001Bu)
#define	DWT_PERIPHID2_PERIPHID   (0xFFFFFFFFu)
#define	DWT_PERIPHID2_PERIPHID_MASK   (0xFFFFFFFFu)
#define	DWT_PERIPHID2_PERIPHID_BIT   (0)
#define	DWT_PERIPHID2_PERIPHID_BITS   (32)
#define	DWT_PERIPHID3   *((volatile int32u *)0xE0001FECu)
#define	DWT_PERIPHID3_REG   *((volatile int32u *)0xE0001FECu)
#define	DWT_PERIPHID3_ADDR   (0xE0001FECu)
#define	DWT_PERIPHID3_RESET   (0x00000000u)
#define	DWT_PERIPHID3_PERIPHID   (0xFFFFFFFFu)
#define	DWT_PERIPHID3_PERIPHID_MASK   (0xFFFFFFFFu)
#define	DWT_PERIPHID3_PERIPHID_BIT   (0)
#define	DWT_PERIPHID3_PERIPHID_BITS   (32)
#define	DWT_CELLID0   *((volatile int32u *)0xE0001FF0u)
#define	DWT_CELLID0_REG   *((volatile int32u *)0xE0001FF0u)
#define	DWT_CELLID0_ADDR   (0xE0001FF0u)
#define	DWT_CELLID0_RESET   (0x0000000Du)
#define	DWT_CELLID0_CELLID   (0xFFFFFFFFu)
#define	DWT_CELLID0_CELLID_MASK   (0xFFFFFFFFu)
#define	DWT_CELLID0_CELLID_BIT   (0)
#define	DWT_CELLID0_CELLID_BITS   (32)
#define	DWT_CELLID1   *((volatile int32u *)0xE0001FF4u)
#define	DWT_CELLID1_REG   *((volatile int32u *)0xE0001FF4u)
#define	DWT_CELLID1_ADDR   (0xE0001FF4u)
#define	DWT_CELLID1_RESET   (0x000000E0u)
#define	DWT_CELLID1_CELLID   (0xFFFFFFFFu)
#define	DWT_CELLID1_CELLID_MASK   (0xFFFFFFFFu)
#define	DWT_CELLID1_CELLID_BIT   (0)
#define	DWT_CELLID1_CELLID_BITS   (32)
#define	DWT_CELLID2   *((volatile int32u *)0xE0001FF8u)
#define	DWT_CELLID2_REG   *((volatile int32u *)0xE0001FF8u)
#define	DWT_CELLID2_ADDR   (0xE0001FF8u)
#define	DWT_CELLID2_RESET   (0x00000005u)
#define	DWT_CELLID2_CELLID   (0xFFFFFFFFu)
#define	DWT_CELLID2_CELLID_MASK   (0xFFFFFFFFu)
#define	DWT_CELLID2_CELLID_BIT   (0)
#define	DWT_CELLID2_CELLID_BITS   (32)
#define	DWT_CELLID3   *((volatile int32u *)0xE0001FFCu)
#define	DWT_CELLID3_REG   *((volatile int32u *)0xE0001FFCu)
#define	DWT_CELLID3_ADDR   (0xE0001FFCu)
#define	DWT_CELLID3_RESET   (0x000000B1u)
#define	DWT_CELLID3_CELLID   (0xFFFFFFFFu)
#define	DWT_CELLID3_CELLID_MASK   (0xFFFFFFFFu)
#define	DWT_CELLID3_CELLID_BIT   (0)
#define	DWT_CELLID3_CELLID_BITS   (32)
#define	DATA_FPB_BASE   (0xE0002000u)
#define	DATA_FPB_END   (0xE0002FFFu)
#define	DATA_FPB_SIZE   (DATA_FPB_END - DATA_FPB_BASE + 1)
#define	FPB_CTRL   *((volatile int32u *)0xE0002000u)
#define	FPB_CTRL_REG   *((volatile int32u *)0xE0002000u)
#define	FPB_CTRL_ADDR   (0xE0002000u)
#define	FPB_CTRL_RESET   (0x00000000u)
#define	FPB_CTRL_NUM_LIT   (0x00000F00u)
#define	FPB_CTRL_NUM_LIT_MASK   (0x00000F00u)
#define	FPB_CTRL_NUM_LIT_BIT   (8)
#define	FPB_CTRL_NUM_LIT_BITS   (4)
#define	FPB_CTRL_NUM_CODE   (0x000000F0u)
#define	FPB_CTRL_NUM_CODE_MASK   (0x000000F0u)
#define	FPB_CTRL_NUM_CODE_BIT   (4)
#define	FPB_CTRL_NUM_CODE_BITS   (4)
#define	FPB_CTRL_KEY   (0x00000002u)
#define	FPB_CTRL_KEY_MASK   (0x00000002u)
#define	FPB_CTRL_KEY_BIT   (1)
#define	FPB_CTRL_KEY_BITS   (1)
#define	FPB_CTRL_enable   (0x00000001u)
#define	FPB_CTRL_enable_MASK   (0x00000001u)
#define	FPB_CTRL_enable_BIT   (0)
#define	FPB_CTRL_enable_BITS   (1)
#define	FPB_REMAP   *((volatile int32u *)0xE0002004u)
#define	FPB_REMAP_REG   *((volatile int32u *)0xE0002004u)
#define	FPB_REMAP_ADDR   (0xE0002004u)
#define	FPB_REMAP_RESET   (0x20000000u)
#define	FPB_REMAP_REMAP   (0x1FFFFFE0u)
#define	FPB_REMAP_REMAP_MASK   (0x1FFFFFE0u)
#define	FPB_REMAP_REMAP_BIT   (5)
#define	FPB_REMAP_REMAP_BITS   (24)
#define	FPB_COMP0   *((volatile int32u *)0xE0002008u)
#define	FPB_COMP0_REG   *((volatile int32u *)0xE0002008u)
#define	FPB_COMP0_ADDR   (0xE0002008u)
#define	FPB_COMP0_RESET   (0x00000000u)
#define	FPB_COMP0_REPLACE   (0xC0000000u)
#define	FPB_COMP0_REPLACE_MASK   (0xC0000000u)
#define	FPB_COMP0_REPLACE_BIT   (30)
#define	FPB_COMP0_REPLACE_BITS   (2)
#define	FPB_COMP0_COMP   (0x1FFFFFFCu)
#define	FPB_COMP0_COMP_MASK   (0x1FFFFFFCu)
#define	FPB_COMP0_COMP_BIT   (2)
#define	FPB_COMP0_COMP_BITS   (27)
#define	FPB_COMP0_enable   (0x00000001u)
#define	FPB_COMP0_enable_MASK   (0x00000001u)
#define	FPB_COMP0_enable_BIT   (0)
#define	FPB_COMP0_enable_BITS   (1)
#define	FPB_COMP1   *((volatile int32u *)0xE000200Cu)
#define	FPB_COMP1_REG   *((volatile int32u *)0xE000200Cu)
#define	FPB_COMP1_ADDR   (0xE000200Cu)
#define	FPB_COMP1_RESET   (0x00000000u)
#define	FPB_COMP1_REPLACE   (0xC0000000u)
#define	FPB_COMP1_REPLACE_MASK   (0xC0000000u)
#define	FPB_COMP1_REPLACE_BIT   (30)
#define	FPB_COMP1_REPLACE_BITS   (2)
#define	FPB_COMP1_COMP   (0x1FFFFFFCu)
#define	FPB_COMP1_COMP_MASK   (0x1FFFFFFCu)
#define	FPB_COMP1_COMP_BIT   (2)
#define	FPB_COMP1_COMP_BITS   (27)
#define	FPB_COMP1_enable   (0x00000001u)
#define	FPB_COMP1_enable_MASK   (0x00000001u)
#define	FPB_COMP1_enable_BIT   (0)
#define	FPB_COMP1_enable_BITS   (1)
#define	FPB_COMP2   *((volatile int32u *)0xE0002010u)
#define	FPB_COMP2_REG   *((volatile int32u *)0xE0002010u)
#define	FPB_COMP2_ADDR   (0xE0002010u)
#define	FPB_COMP2_RESET   (0x00000000u)
#define	FPB_COMP2_REPLACE   (0xC0000000u)
#define	FPB_COMP2_REPLACE_MASK   (0xC0000000u)
#define	FPB_COMP2_REPLACE_BIT   (30)
#define	FPB_COMP2_REPLACE_BITS   (2)
#define	FPB_COMP2_COMP   (0x1FFFFFFCu)
#define	FPB_COMP2_COMP_MASK   (0x1FFFFFFCu)
#define	FPB_COMP2_COMP_BIT   (2)
#define	FPB_COMP2_COMP_BITS   (27)
#define	FPB_COMP2_enable   (0x00000001u)
#define	FPB_COMP2_enable_MASK   (0x00000001u)
#define	FPB_COMP2_enable_BIT   (0)
#define	FPB_COMP2_enable_BITS   (1)
#define	FPB_COMP3   *((volatile int32u *)0xE0002014u)
#define	FPB_COMP3_REG   *((volatile int32u *)0xE0002014u)
#define	FPB_COMP3_ADDR   (0xE0002014u)
#define	FPB_COMP3_RESET   (0x00000000u)
#define	FPB_COMP3_REPLACE   (0xC0000000u)
#define	FPB_COMP3_REPLACE_MASK   (0xC0000000u)
#define	FPB_COMP3_REPLACE_BIT   (30)
#define	FPB_COMP3_REPLACE_BITS   (2)
#define	FPB_COMP3_COMP   (0x1FFFFFFCu)
#define	FPB_COMP3_COMP_MASK   (0x1FFFFFFCu)
#define	FPB_COMP3_COMP_BIT   (2)
#define	FPB_COMP3_COMP_BITS   (27)
#define	FPB_COMP3_enable   (0x00000001u)
#define	FPB_COMP3_enable_MASK   (0x00000001u)
#define	FPB_COMP3_enable_BIT   (0)
#define	FPB_COMP3_enable_BITS   (1)
#define	FPB_COMP4   *((volatile int32u *)0xE0002018u)
#define	FPB_COMP4_REG   *((volatile int32u *)0xE0002018u)
#define	FPB_COMP4_ADDR   (0xE0002018u)
#define	FPB_COMP4_RESET   (0x00000000u)
#define	FPB_COMP4_REPLACE   (0xC0000000u)
#define	FPB_COMP4_REPLACE_MASK   (0xC0000000u)
#define	FPB_COMP4_REPLACE_BIT   (30)
#define	FPB_COMP4_REPLACE_BITS   (2)
#define	FPB_COMP4_COMP   (0x1FFFFFFCu)
#define	FPB_COMP4_COMP_MASK   (0x1FFFFFFCu)
#define	FPB_COMP4_COMP_BIT   (2)
#define	FPB_COMP4_COMP_BITS   (27)
#define	FPB_COMP4_enable   (0x00000001u)
#define	FPB_COMP4_enable_MASK   (0x00000001u)
#define	FPB_COMP4_enable_BIT   (0)
#define	FPB_COMP4_enable_BITS   (1)
#define	FPB_COMP5   *((volatile int32u *)0xE000201Cu)
#define	FPB_COMP5_REG   *((volatile int32u *)0xE000201Cu)
#define	FPB_COMP5_ADDR   (0xE000201Cu)
#define	FPB_COMP5_RESET   (0x00000000u)
#define	FPB_COMP5_REPLACE   (0xC0000000u)
#define	FPB_COMP5_REPLACE_MASK   (0xC0000000u)
#define	FPB_COMP5_REPLACE_BIT   (30)
#define	FPB_COMP5_REPLACE_BITS   (2)
#define	FPB_COMP5_COMP   (0x1FFFFFFCu)
#define	FPB_COMP5_COMP_MASK   (0x1FFFFFFCu)
#define	FPB_COMP5_COMP_BIT   (2)
#define	FPB_COMP5_COMP_BITS   (27)
#define	FPB_COMP5_enable   (0x00000001u)
#define	FPB_COMP5_enable_MASK   (0x00000001u)
#define	FPB_COMP5_enable_BIT   (0)
#define	FPB_COMP5_enable_BITS   (1)
#define	FPB_COMP6   *((volatile int32u *)0xE0002020u)
#define	FPB_COMP6_REG   *((volatile int32u *)0xE0002020u)
#define	FPB_COMP6_ADDR   (0xE0002020u)
#define	FPB_COMP6_RESET   (0x00000000u)
#define	FPB_COMP6_REPLACE   (0xC0000000u)
#define	FPB_COMP6_REPLACE_MASK   (0xC0000000u)
#define	FPB_COMP6_REPLACE_BIT   (30)
#define	FPB_COMP6_REPLACE_BITS   (2)
#define	FPB_COMP6_COMP   (0x1FFFFFFCu)
#define	FPB_COMP6_COMP_MASK   (0x1FFFFFFCu)
#define	FPB_COMP6_COMP_BIT   (2)
#define	FPB_COMP6_COMP_BITS   (27)
#define	FPB_COMP6_enable   (0x00000001u)
#define	FPB_COMP6_enable_MASK   (0x00000001u)
#define	FPB_COMP6_enable_BIT   (0)
#define	FPB_COMP6_enable_BITS   (1)
#define	FPB_COMP7   *((volatile int32u *)0xE0002024u)
#define	FPB_COMP7_REG   *((volatile int32u *)0xE0002024u)
#define	FPB_COMP7_ADDR   (0xE0002024u)
#define	FPB_COMP7_RESET   (0x00000000u)
#define	FPB_COMP7_REPLACE   (0xC0000000u)
#define	FPB_COMP7_REPLACE_MASK   (0xC0000000u)
#define	FPB_COMP7_REPLACE_BIT   (30)
#define	FPB_COMP7_REPLACE_BITS   (2)
#define	FPB_COMP7_COMP   (0x1FFFFFFCu)
#define	FPB_COMP7_COMP_MASK   (0x1FFFFFFCu)
#define	FPB_COMP7_COMP_BIT   (2)
#define	FPB_COMP7_COMP_BITS   (27)
#define	FPB_COMP7_enable   (0x00000001u)
#define	FPB_COMP7_enable_MASK   (0x00000001u)
#define	FPB_COMP7_enable_BIT   (0)
#define	FPB_COMP7_enable_BITS   (1)
#define	FPB_PERIPHID4   *((volatile int32u *)0xE0002FD0u)
#define	FPB_PERIPHID4_REG   *((volatile int32u *)0xE0002FD0u)
#define	FPB_PERIPHID4_ADDR   (0xE0002FD0u)
#define	FPB_PERIPHID4_RESET   (0x00000004u)
#define	FPB_PERIPHID4_PERIPHID   (0xFFFFFFFFu)
#define	FPB_PERIPHID4_PERIPHID_MASK   (0xFFFFFFFFu)
#define	FPB_PERIPHID4_PERIPHID_BIT   (0)
#define	FPB_PERIPHID4_PERIPHID_BITS   (32)
#define	FPB_PERIPHID5   *((volatile int32u *)0xE0002FD4u)
#define	FPB_PERIPHID5_REG   *((volatile int32u *)0xE0002FD4u)
#define	FPB_PERIPHID5_ADDR   (0xE0002FD4u)
#define	FPB_PERIPHID5_RESET   (0x00000000u)
#define	FPB_PERIPHID5_PERIPHID   (0xFFFFFFFFu)
#define	FPB_PERIPHID5_PERIPHID_MASK   (0xFFFFFFFFu)
#define	FPB_PERIPHID5_PERIPHID_BIT   (0)
#define	FPB_PERIPHID5_PERIPHID_BITS   (32)
#define	FPB_PERIPHID6   *((volatile int32u *)0xE0002FD8u)
#define	FPB_PERIPHID6_REG   *((volatile int32u *)0xE0002FD8u)
#define	FPB_PERIPHID6_ADDR   (0xE0002FD8u)
#define	FPB_PERIPHID6_RESET   (0x00000000u)
#define	FPB_PERIPHID6_PERIPHID   (0xFFFFFFFFu)
#define	FPB_PERIPHID6_PERIPHID_MASK   (0xFFFFFFFFu)
#define	FPB_PERIPHID6_PERIPHID_BIT   (0)
#define	FPB_PERIPHID6_PERIPHID_BITS   (32)
#define	FPB_PERIPHID7   *((volatile int32u *)0xE0002FDCu)
#define	FPB_PERIPHID7_REG   *((volatile int32u *)0xE0002FDCu)
#define	FPB_PERIPHID7_ADDR   (0xE0002FDCu)
#define	FPB_PERIPHID7_RESET   (0x00000000u)
#define	FPB_PERIPHID7_PERIPHID   (0xFFFFFFFFu)
#define	FPB_PERIPHID7_PERIPHID_MASK   (0xFFFFFFFFu)
#define	FPB_PERIPHID7_PERIPHID_BIT   (0)
#define	FPB_PERIPHID7_PERIPHID_BITS   (32)
#define	FPB_PERIPHID0   *((volatile int32u *)0xE0002FE0u)
#define	FPB_PERIPHID0_REG   *((volatile int32u *)0xE0002FE0u)
#define	FPB_PERIPHID0_ADDR   (0xE0002FE0u)
#define	FPB_PERIPHID0_RESET   (0x00000003u)
#define	FPB_PERIPHID0_PERIPHID   (0xFFFFFFFFu)
#define	FPB_PERIPHID0_PERIPHID_MASK   (0xFFFFFFFFu)
#define	FPB_PERIPHID0_PERIPHID_BIT   (0)
#define	FPB_PERIPHID0_PERIPHID_BITS   (32)
#define	FPB_PERIPHID1   *((volatile int32u *)0xE0002FE4u)
#define	FPB_PERIPHID1_REG   *((volatile int32u *)0xE0002FE4u)
#define	FPB_PERIPHID1_ADDR   (0xE0002FE4u)
#define	FPB_PERIPHID1_RESET   (0x000000B0u)
#define	FPB_PERIPHID1_PERIPHID   (0xFFFFFFFFu)
#define	FPB_PERIPHID1_PERIPHID_MASK   (0xFFFFFFFFu)
#define	FPB_PERIPHID1_PERIPHID_BIT   (0)
#define	FPB_PERIPHID1_PERIPHID_BITS   (32)
#define	FPB_PERIPHID2   *((volatile int32u *)0xE0002FE8u)
#define	FPB_PERIPHID2_REG   *((volatile int32u *)0xE0002FE8u)
#define	FPB_PERIPHID2_ADDR   (0xE0002FE8u)
#define	FPB_PERIPHID2_RESET   (0x0000000Bu)
#define	FPB_PERIPHID2_PERIPHID   (0xFFFFFFFFu)
#define	FPB_PERIPHID2_PERIPHID_MASK   (0xFFFFFFFFu)
#define	FPB_PERIPHID2_PERIPHID_BIT   (0)
#define	FPB_PERIPHID2_PERIPHID_BITS   (32)
#define	FPB_PERIPHID3   *((volatile int32u *)0xE0002FECu)
#define	FPB_PERIPHID3_REG   *((volatile int32u *)0xE0002FECu)
#define	FPB_PERIPHID3_ADDR   (0xE0002FECu)
#define	FPB_PERIPHID3_RESET   (0x00000000u)
#define	FPB_PERIPHID3_PERIPHID   (0xFFFFFFFFu)
#define	FPB_PERIPHID3_PERIPHID_MASK   (0xFFFFFFFFu)
#define	FPB_PERIPHID3_PERIPHID_BIT   (0)
#define	FPB_PERIPHID3_PERIPHID_BITS   (32)
#define	FPB_CELLID0   *((volatile int32u *)0xE0002FF0u)
#define	FPB_CELLID0_REG   *((volatile int32u *)0xE0002FF0u)
#define	FPB_CELLID0_ADDR   (0xE0002FF0u)
#define	FPB_CELLID0_RESET   (0x0000000Du)
#define	FPB_CELLID0_CELLID   (0xFFFFFFFFu)
#define	FPB_CELLID0_CELLID_MASK   (0xFFFFFFFFu)
#define	FPB_CELLID0_CELLID_BIT   (0)
#define	FPB_CELLID0_CELLID_BITS   (32)
#define	FPB_CELLID1   *((volatile int32u *)0xE0002FF4u)
#define	FPB_CELLID1_REG   *((volatile int32u *)0xE0002FF4u)
#define	FPB_CELLID1_ADDR   (0xE0002FF4u)
#define	FPB_CELLID1_RESET   (0x000000E0u)
#define	FPB_CELLID1_CELLID   (0xFFFFFFFFu)
#define	FPB_CELLID1_CELLID_MASK   (0xFFFFFFFFu)
#define	FPB_CELLID1_CELLID_BIT   (0)
#define	FPB_CELLID1_CELLID_BITS   (32)
#define	FPB_CELLID2   *((volatile int32u *)0xE0002FF8u)
#define	FPB_CELLID2_REG   *((volatile int32u *)0xE0002FF8u)
#define	FPB_CELLID2_ADDR   (0xE0002FF8u)
#define	FPB_CELLID2_RESET   (0x00000005u)
#define	FPB_CELLID2_CELLID   (0xFFFFFFFFu)
#define	FPB_CELLID2_CELLID_MASK   (0xFFFFFFFFu)
#define	FPB_CELLID2_CELLID_BIT   (0)
#define	FPB_CELLID2_CELLID_BITS   (32)
#define	FPB_CELLID3   *((volatile int32u *)0xE0002FFCu)
#define	FPB_CELLID3_REG   *((volatile int32u *)0xE0002FFCu)
#define	FPB_CELLID3_ADDR   (0xE0002FFCu)
#define	FPB_CELLID3_RESET   (0x000000B1u)
#define	FPB_CELLID3_CELLID   (0xFFFFFFFFu)
#define	FPB_CELLID3_CELLID_MASK   (0xFFFFFFFFu)
#define	FPB_CELLID3_CELLID_BIT   (0)
#define	FPB_CELLID3_CELLID_BITS   (32)
#define	BLOCK_NVIC_BASE   (0xE000E000u)
#define	BLOCK_NVIC_END   (0xE000EFFFu)
#define	BLOCK_NVIC_SIZE   (BLOCK_NVIC_END - BLOCK_NVIC_BASE + 1)
#define	NVIC_MCR   *((volatile int32u *)0xE000E000u)
#define	NVIC_MCR_REG   *((volatile int32u *)0xE000E000u)
#define	NVIC_MCR_ADDR   (0xE000E000u)
#define	NVIC_MCR_RESET   (0x00000000u)
#define	NVIC_ICTR   *((volatile int32u *)0xE000E004u)
#define	NVIC_ICTR_REG   *((volatile int32u *)0xE000E004u)
#define	NVIC_ICTR_ADDR   (0xE000E004u)
#define	NVIC_ICTR_RESET   (0x00000000u)
#define	NVIC_ICTR_INTLINESNUM   (0x0000001Fu)
#define	NVIC_ICTR_INTLINESNUM_MASK   (0x0000001Fu)
#define	NVIC_ICTR_INTLINESNUM_BIT   (0)
#define	NVIC_ICTR_INTLINESNUM_BITS   (5)
#define	ST_CSR   *((volatile int32u *)0xE000E010u)
#define	ST_CSR_REG   *((volatile int32u *)0xE000E010u)
#define	ST_CSR_ADDR   (0xE000E010u)
#define	ST_CSR_RESET   (0x00000000u)
#define	ST_CSR_COUNTFLAG   (0x00010000u)
#define	ST_CSR_COUNTFLAG_MASK   (0x00010000u)
#define	ST_CSR_COUNTFLAG_BIT   (16)
#define	ST_CSR_COUNTFLAG_BITS   (1)
#define	ST_CSR_CLKSOURCE   (0x00000004u)
#define	ST_CSR_CLKSOURCE_MASK   (0x00000004u)
#define	ST_CSR_CLKSOURCE_BIT   (2)
#define	ST_CSR_CLKSOURCE_BITS   (1)
#define	ST_CSR_TICKINT   (0x00000002u)
#define	ST_CSR_TICKINT_MASK   (0x00000002u)
#define	ST_CSR_TICKINT_BIT   (1)
#define	ST_CSR_TICKINT_BITS   (1)
#define	ST_CSR_ENABLE   (0x00000001u)
#define	ST_CSR_ENABLE_MASK   (0x00000001u)
#define	ST_CSR_ENABLE_BIT   (0)
#define	ST_CSR_ENABLE_BITS   (1)
#define	ST_RVR   *((volatile int32u *)0xE000E014u)
#define	ST_RVR_REG   *((volatile int32u *)0xE000E014u)
#define	ST_RVR_ADDR   (0xE000E014u)
#define	ST_RVR_RESET   (0x00000000u)
#define	ST_RVR_RELOAD   (0x00FFFFFFu)
#define	ST_RVR_RELOAD_MASK   (0x00FFFFFFu)
#define	ST_RVR_RELOAD_BIT   (0)
#define	ST_RVR_RELOAD_BITS   (24)
#define	ST_CVR   *((volatile int32u *)0xE000E018u)
#define	ST_CVR_REG   *((volatile int32u *)0xE000E018u)
#define	ST_CVR_ADDR   (0xE000E018u)
#define	ST_CVR_RESET   (0x00000000u)
#define	ST_CVR_CURRENT   (0xFFFFFFFFu)
#define	ST_CVR_CURRENT_MASK   (0xFFFFFFFFu)
#define	ST_CVR_CURRENT_BIT   (0)
#define	ST_CVR_CURRENT_BITS   (32)
#define	ST_CALVR   *((volatile int32u *)0xE000E01Cu)
#define	ST_CALVR_REG   *((volatile int32u *)0xE000E01Cu)
#define	ST_CALVR_ADDR   (0xE000E01Cu)
#define	ST_CALVR_RESET   (0x00000000u)
#define	ST_CALVR_NOREF   (0x80000000u)
#define	ST_CALVR_NOREF_MASK   (0x80000000u)
#define	ST_CALVR_NOREF_BIT   (31)
#define	ST_CALVR_NOREF_BITS   (1)
#define	ST_CALVR_SKEW   (0x40000000u)
#define	ST_CALVR_SKEW_MASK   (0x40000000u)
#define	ST_CALVR_SKEW_BIT   (30)
#define	ST_CALVR_SKEW_BITS   (1)
#define	ST_CALVR_TENMS   (0x00FFFFFFu)
#define	ST_CALVR_TENMS_MASK   (0x00FFFFFFu)
#define	ST_CALVR_TENMS_BIT   (0)
#define	ST_CALVR_TENMS_BITS   (24)
#define	INT_CFGSET   *((volatile int32u *)0xE000E100u)
#define	INT_CFGSET_REG   *((volatile int32u *)0xE000E100u)
#define	INT_CFGSET_ADDR   (0xE000E100u)
#define	INT_CFGSET_RESET   (0x00000000u)
#define	INT_DEBUG   (0x00010000u)
#define	INT_DEBUG_MASK   (0x00010000u)
#define	INT_DEBUG_BIT   (16)
#define	INT_DEBUG_BITS   (1)
#define	INT_IRQD   (0x00008000u)
#define	INT_IRQD_MASK   (0x00008000u)
#define	INT_IRQD_BIT   (15)
#define	INT_IRQD_BITS   (1)
#define	INT_IRQC   (0x00004000u)
#define	INT_IRQC_MASK   (0x00004000u)
#define	INT_IRQC_BIT   (14)
#define	INT_IRQC_BITS   (1)
#define	INT_IRQB   (0x00002000u)
#define	INT_IRQB_MASK   (0x00002000u)
#define	INT_IRQB_BIT   (13)
#define	INT_IRQB_BITS   (1)
#define	INT_IRQA   (0x00001000u)
#define	INT_IRQA_MASK   (0x00001000u)
#define	INT_IRQA_BIT   (12)
#define	INT_IRQA_BITS   (1)
#define	INT_ADC   (0x00000800u)
#define	INT_ADC_MASK   (0x00000800u)
#define	INT_ADC_BIT   (11)
#define	INT_ADC_BITS   (1)
#define	INT_MACRX   (0x00000400u)
#define	INT_MACRX_MASK   (0x00000400u)
#define	INT_MACRX_BIT   (10)
#define	INT_MACRX_BITS   (1)
#define	INT_MACTX   (0x00000200u)
#define	INT_MACTX_MASK   (0x00000200u)
#define	INT_MACTX_BIT   (9)
#define	INT_MACTX_BITS   (1)
#define	INT_MACTMR   (0x00000100u)
#define	INT_MACTMR_MASK   (0x00000100u)
#define	INT_MACTMR_BIT   (8)
#define	INT_MACTMR_BITS   (1)
#define	INT_SEC   (0x00000080u)
#define	INT_SEC_MASK   (0x00000080u)
#define	INT_SEC_BIT   (7)
#define	INT_SEC_BITS   (1)
#define	INT_SC2   (0x00000040u)
#define	INT_SC2_MASK   (0x00000040u)
#define	INT_SC2_BIT   (6)
#define	INT_SC2_BITS   (1)
#define	INT_SC1   (0x00000020u)
#define	INT_SC1_MASK   (0x00000020u)
#define	INT_SC1_BIT   (5)
#define	INT_SC1_BITS   (1)
#define	INT_SLEEPTMR   (0x00000010u)
#define	INT_SLEEPTMR_MASK   (0x00000010u)
#define	INT_SLEEPTMR_BIT   (4)
#define	INT_SLEEPTMR_BITS   (1)
#define	INT_BB   (0x00000008u)
#define	INT_BB_MASK   (0x00000008u)
#define	INT_BB_BIT   (3)
#define	INT_BB_BITS   (1)
#define	INT_MGMT   (0x00000004u)
#define	INT_MGMT_MASK   (0x00000004u)
#define	INT_MGMT_BIT   (2)
#define	INT_MGMT_BITS   (1)
#define	INT_TIM2   (0x00000002u)
#define	INT_TIM2_MASK   (0x00000002u)
#define	INT_TIM2_BIT   (1)
#define	INT_TIM2_BITS   (1)
#define	INT_TIM1   (0x00000001u)
#define	INT_TIM1_MASK   (0x00000001u)
#define	INT_TIM1_BIT   (0)
#define	INT_TIM1_BITS   (1)
#define	INT_CFGCLR   *((volatile int32u *)0xE000E180u)
#define	INT_CFGCLR_REG   *((volatile int32u *)0xE000E180u)
#define	INT_CFGCLR_ADDR   (0xE000E180u)
#define	INT_CFGCLR_RESET   (0x00000000u)
#define	INT_DEBUG   (0x00010000u)
#define	INT_DEBUG_MASK   (0x00010000u)
#define	INT_DEBUG_BIT   (16)
#define	INT_DEBUG_BITS   (1)
#define	INT_IRQD   (0x00008000u)
#define	INT_IRQD_MASK   (0x00008000u)
#define	INT_IRQD_BIT   (15)
#define	INT_IRQD_BITS   (1)
#define	INT_IRQC   (0x00004000u)
#define	INT_IRQC_MASK   (0x00004000u)
#define	INT_IRQC_BIT   (14)
#define	INT_IRQC_BITS   (1)
#define	INT_IRQB   (0x00002000u)
#define	INT_IRQB_MASK   (0x00002000u)
#define	INT_IRQB_BIT   (13)
#define	INT_IRQB_BITS   (1)
#define	INT_IRQA   (0x00001000u)
#define	INT_IRQA_MASK   (0x00001000u)
#define	INT_IRQA_BIT   (12)
#define	INT_IRQA_BITS   (1)
#define	INT_ADC   (0x00000800u)
#define	INT_ADC_MASK   (0x00000800u)
#define	INT_ADC_BIT   (11)
#define	INT_ADC_BITS   (1)
#define	INT_MACRX   (0x00000400u)
#define	INT_MACRX_MASK   (0x00000400u)
#define	INT_MACRX_BIT   (10)
#define	INT_MACRX_BITS   (1)
#define	INT_MACTX   (0x00000200u)
#define	INT_MACTX_MASK   (0x00000200u)
#define	INT_MACTX_BIT   (9)
#define	INT_MACTX_BITS   (1)
#define	INT_MACTMR   (0x00000100u)
#define	INT_MACTMR_MASK   (0x00000100u)
#define	INT_MACTMR_BIT   (8)
#define	INT_MACTMR_BITS   (1)
#define	INT_SEC   (0x00000080u)
#define	INT_SEC_MASK   (0x00000080u)
#define	INT_SEC_BIT   (7)
#define	INT_SEC_BITS   (1)
#define	INT_SC2   (0x00000040u)
#define	INT_SC2_MASK   (0x00000040u)
#define	INT_SC2_BIT   (6)
#define	INT_SC2_BITS   (1)
#define	INT_SC1   (0x00000020u)
#define	INT_SC1_MASK   (0x00000020u)
#define	INT_SC1_BIT   (5)
#define	INT_SC1_BITS   (1)
#define	INT_SLEEPTMR   (0x00000010u)
#define	INT_SLEEPTMR_MASK   (0x00000010u)
#define	INT_SLEEPTMR_BIT   (4)
#define	INT_SLEEPTMR_BITS   (1)
#define	INT_BB   (0x00000008u)
#define	INT_BB_MASK   (0x00000008u)
#define	INT_BB_BIT   (3)
#define	INT_BB_BITS   (1)
#define	INT_MGMT   (0x00000004u)
#define	INT_MGMT_MASK   (0x00000004u)
#define	INT_MGMT_BIT   (2)
#define	INT_MGMT_BITS   (1)
#define	INT_TIM2   (0x00000002u)
#define	INT_TIM2_MASK   (0x00000002u)
#define	INT_TIM2_BIT   (1)
#define	INT_TIM2_BITS   (1)
#define	INT_TIM1   (0x00000001u)
#define	INT_TIM1_MASK   (0x00000001u)
#define	INT_TIM1_BIT   (0)
#define	INT_TIM1_BITS   (1)
#define	INT_PENDSET   *((volatile int32u *)0xE000E200u)
#define	INT_PENDSET_REG   *((volatile int32u *)0xE000E200u)
#define	INT_PENDSET_ADDR   (0xE000E200u)
#define	INT_PENDSET_RESET   (0x00000000u)
#define	INT_DEBUG   (0x00010000u)
#define	INT_DEBUG_MASK   (0x00010000u)
#define	INT_DEBUG_BIT   (16)
#define	INT_DEBUG_BITS   (1)
#define	INT_IRQD   (0x00008000u)
#define	INT_IRQD_MASK   (0x00008000u)
#define	INT_IRQD_BIT   (15)
#define	INT_IRQD_BITS   (1)
#define	INT_IRQC   (0x00004000u)
#define	INT_IRQC_MASK   (0x00004000u)
#define	INT_IRQC_BIT   (14)
#define	INT_IRQC_BITS   (1)
#define	INT_IRQB   (0x00002000u)
#define	INT_IRQB_MASK   (0x00002000u)
#define	INT_IRQB_BIT   (13)
#define	INT_IRQB_BITS   (1)
#define	INT_IRQA   (0x00001000u)
#define	INT_IRQA_MASK   (0x00001000u)
#define	INT_IRQA_BIT   (12)
#define	INT_IRQA_BITS   (1)
#define	INT_ADC   (0x00000800u)
#define	INT_ADC_MASK   (0x00000800u)
#define	INT_ADC_BIT   (11)
#define	INT_ADC_BITS   (1)
#define	INT_MACRX   (0x00000400u)
#define	INT_MACRX_MASK   (0x00000400u)
#define	INT_MACRX_BIT   (10)
#define	INT_MACRX_BITS   (1)
#define	INT_MACTX   (0x00000200u)
#define	INT_MACTX_MASK   (0x00000200u)
#define	INT_MACTX_BIT   (9)
#define	INT_MACTX_BITS   (1)
#define	INT_MACTMR   (0x00000100u)
#define	INT_MACTMR_MASK   (0x00000100u)
#define	INT_MACTMR_BIT   (8)
#define	INT_MACTMR_BITS   (1)
#define	INT_SEC   (0x00000080u)
#define	INT_SEC_MASK   (0x00000080u)
#define	INT_SEC_BIT   (7)
#define	INT_SEC_BITS   (1)
#define	INT_SC2   (0x00000040u)
#define	INT_SC2_MASK   (0x00000040u)
#define	INT_SC2_BIT   (6)
#define	INT_SC2_BITS   (1)
#define	INT_SC1   (0x00000020u)
#define	INT_SC1_MASK   (0x00000020u)
#define	INT_SC1_BIT   (5)
#define	INT_SC1_BITS   (1)
#define	INT_SLEEPTMR   (0x00000010u)
#define	INT_SLEEPTMR_MASK   (0x00000010u)
#define	INT_SLEEPTMR_BIT   (4)
#define	INT_SLEEPTMR_BITS   (1)
#define	INT_BB   (0x00000008u)
#define	INT_BB_MASK   (0x00000008u)
#define	INT_BB_BIT   (3)
#define	INT_BB_BITS   (1)
#define	INT_MGMT   (0x00000004u)
#define	INT_MGMT_MASK   (0x00000004u)
#define	INT_MGMT_BIT   (2)
#define	INT_MGMT_BITS   (1)
#define	INT_TIM2   (0x00000002u)
#define	INT_TIM2_MASK   (0x00000002u)
#define	INT_TIM2_BIT   (1)
#define	INT_TIM2_BITS   (1)
#define	INT_TIM1   (0x00000001u)
#define	INT_TIM1_MASK   (0x00000001u)
#define	INT_TIM1_BIT   (0)
#define	INT_TIM1_BITS   (1)
#define	INT_PENDCLR   *((volatile int32u *)0xE000E280u)
#define	INT_PENDCLR_REG   *((volatile int32u *)0xE000E280u)
#define	INT_PENDCLR_ADDR   (0xE000E280u)
#define	INT_PENDCLR_RESET   (0x00000000u)
#define	INT_DEBUG   (0x00010000u)
#define	INT_DEBUG_MASK   (0x00010000u)
#define	INT_DEBUG_BIT   (16)
#define	INT_DEBUG_BITS   (1)
#define	INT_IRQD   (0x00008000u)
#define	INT_IRQD_MASK   (0x00008000u)
#define	INT_IRQD_BIT   (15)
#define	INT_IRQD_BITS   (1)
#define	INT_IRQC   (0x00004000u)
#define	INT_IRQC_MASK   (0x00004000u)
#define	INT_IRQC_BIT   (14)
#define	INT_IRQC_BITS   (1)
#define	INT_IRQB   (0x00002000u)
#define	INT_IRQB_MASK   (0x00002000u)
#define	INT_IRQB_BIT   (13)
#define	INT_IRQB_BITS   (1)
#define	INT_IRQA   (0x00001000u)
#define	INT_IRQA_MASK   (0x00001000u)
#define	INT_IRQA_BIT   (12)
#define	INT_IRQA_BITS   (1)
#define	INT_ADC   (0x00000800u)
#define	INT_ADC_MASK   (0x00000800u)
#define	INT_ADC_BIT   (11)
#define	INT_ADC_BITS   (1)
#define	INT_MACRX   (0x00000400u)
#define	INT_MACRX_MASK   (0x00000400u)
#define	INT_MACRX_BIT   (10)
#define	INT_MACRX_BITS   (1)
#define	INT_MACTX   (0x00000200u)
#define	INT_MACTX_MASK   (0x00000200u)
#define	INT_MACTX_BIT   (9)
#define	INT_MACTX_BITS   (1)
#define	INT_MACTMR   (0x00000100u)
#define	INT_MACTMR_MASK   (0x00000100u)
#define	INT_MACTMR_BIT   (8)
#define	INT_MACTMR_BITS   (1)
#define	INT_SEC   (0x00000080u)
#define	INT_SEC_MASK   (0x00000080u)
#define	INT_SEC_BIT   (7)
#define	INT_SEC_BITS   (1)
#define	INT_SC2   (0x00000040u)
#define	INT_SC2_MASK   (0x00000040u)
#define	INT_SC2_BIT   (6)
#define	INT_SC2_BITS   (1)
#define	INT_SC1   (0x00000020u)
#define	INT_SC1_MASK   (0x00000020u)
#define	INT_SC1_BIT   (5)
#define	INT_SC1_BITS   (1)
#define	INT_SLEEPTMR   (0x00000010u)
#define	INT_SLEEPTMR_MASK   (0x00000010u)
#define	INT_SLEEPTMR_BIT   (4)
#define	INT_SLEEPTMR_BITS   (1)
#define	INT_BB   (0x00000008u)
#define	INT_BB_MASK   (0x00000008u)
#define	INT_BB_BIT   (3)
#define	INT_BB_BITS   (1)
#define	INT_MGMT   (0x00000004u)
#define	INT_MGMT_MASK   (0x00000004u)
#define	INT_MGMT_BIT   (2)
#define	INT_MGMT_BITS   (1)
#define	INT_TIM2   (0x00000002u)
#define	INT_TIM2_MASK   (0x00000002u)
#define	INT_TIM2_BIT   (1)
#define	INT_TIM2_BITS   (1)
#define	INT_TIM1   (0x00000001u)
#define	INT_TIM1_MASK   (0x00000001u)
#define	INT_TIM1_BIT   (0)
#define	INT_TIM1_BITS   (1)
#define	INT_ACTIVE   *((volatile int32u *)0xE000E300u)
#define	INT_ACTIVE_REG   *((volatile int32u *)0xE000E300u)
#define	INT_ACTIVE_ADDR   (0xE000E300u)
#define	INT_ACTIVE_RESET   (0x00000000u)
#define	INT_DEBUG   (0x00010000u)
#define	INT_DEBUG_MASK   (0x00010000u)
#define	INT_DEBUG_BIT   (16)
#define	INT_DEBUG_BITS   (1)
#define	INT_IRQD   (0x00008000u)
#define	INT_IRQD_MASK   (0x00008000u)
#define	INT_IRQD_BIT   (15)
#define	INT_IRQD_BITS   (1)
#define	INT_IRQC   (0x00004000u)
#define	INT_IRQC_MASK   (0x00004000u)
#define	INT_IRQC_BIT   (14)
#define	INT_IRQC_BITS   (1)
#define	INT_IRQB   (0x00002000u)
#define	INT_IRQB_MASK   (0x00002000u)
#define	INT_IRQB_BIT   (13)
#define	INT_IRQB_BITS   (1)
#define	INT_IRQA   (0x00001000u)
#define	INT_IRQA_MASK   (0x00001000u)
#define	INT_IRQA_BIT   (12)
#define	INT_IRQA_BITS   (1)
#define	INT_ADC   (0x00000800u)
#define	INT_ADC_MASK   (0x00000800u)
#define	INT_ADC_BIT   (11)
#define	INT_ADC_BITS   (1)
#define	INT_MACRX   (0x00000400u)
#define	INT_MACRX_MASK   (0x00000400u)
#define	INT_MACRX_BIT   (10)
#define	INT_MACRX_BITS   (1)
#define	INT_MACTX   (0x00000200u)
#define	INT_MACTX_MASK   (0x00000200u)
#define	INT_MACTX_BIT   (9)
#define	INT_MACTX_BITS   (1)
#define	INT_MACTMR   (0x00000100u)
#define	INT_MACTMR_MASK   (0x00000100u)
#define	INT_MACTMR_BIT   (8)
#define	INT_MACTMR_BITS   (1)
#define	INT_SEC   (0x00000080u)
#define	INT_SEC_MASK   (0x00000080u)
#define	INT_SEC_BIT   (7)
#define	INT_SEC_BITS   (1)
#define	INT_SC2   (0x00000040u)
#define	INT_SC2_MASK   (0x00000040u)
#define	INT_SC2_BIT   (6)
#define	INT_SC2_BITS   (1)
#define	INT_SC1   (0x00000020u)
#define	INT_SC1_MASK   (0x00000020u)
#define	INT_SC1_BIT   (5)
#define	INT_SC1_BITS   (1)
#define	INT_SLEEPTMR   (0x00000010u)
#define	INT_SLEEPTMR_MASK   (0x00000010u)
#define	INT_SLEEPTMR_BIT   (4)
#define	INT_SLEEPTMR_BITS   (1)
#define	INT_BB   (0x00000008u)
#define	INT_BB_MASK   (0x00000008u)
#define	INT_BB_BIT   (3)
#define	INT_BB_BITS   (1)
#define	INT_MGMT   (0x00000004u)
#define	INT_MGMT_MASK   (0x00000004u)
#define	INT_MGMT_BIT   (2)
#define	INT_MGMT_BITS   (1)
#define	INT_TIM2   (0x00000002u)
#define	INT_TIM2_MASK   (0x00000002u)
#define	INT_TIM2_BIT   (1)
#define	INT_TIM2_BITS   (1)
#define	INT_TIM1   (0x00000001u)
#define	INT_TIM1_MASK   (0x00000001u)
#define	INT_TIM1_BIT   (0)
#define	INT_TIM1_BITS   (1)
#define	NVIC_IPR_3to0   *((volatile int32u *)0xE000E400u)
#define	NVIC_IPR_3to0_REG   *((volatile int32u *)0xE000E400u)
#define	NVIC_IPR_3to0_ADDR   (0xE000E400u)
#define	NVIC_IPR_3to0_RESET   (0x00000000u)
#define	NVIC_IPR_3to0_PRI_3   (0xFF000000u)
#define	NVIC_IPR_3to0_PRI_3_MASK   (0xFF000000u)
#define	NVIC_IPR_3to0_PRI_3_BIT   (24)
#define	NVIC_IPR_3to0_PRI_3_BITS   (8)
#define	NVIC_IPR_3to0_PRI_2   (0x00FF0000u)
#define	NVIC_IPR_3to0_PRI_2_MASK   (0x00FF0000u)
#define	NVIC_IPR_3to0_PRI_2_BIT   (16)
#define	NVIC_IPR_3to0_PRI_2_BITS   (8)
#define	NVIC_IPR_3to0_PRI_1   (0x0000FF00u)
#define	NVIC_IPR_3to0_PRI_1_MASK   (0x0000FF00u)
#define	NVIC_IPR_3to0_PRI_1_BIT   (8)
#define	NVIC_IPR_3to0_PRI_1_BITS   (8)
#define	NVIC_IPR_3to0_PRI_0   (0x000000FFu)
#define	NVIC_IPR_3to0_PRI_0_MASK   (0x000000FFu)
#define	NVIC_IPR_3to0_PRI_0_BIT   (0)
#define	NVIC_IPR_3to0_PRI_0_BITS   (8)
#define	NVIC_IPR_7to4   *((volatile int32u *)0xE000E404u)
#define	NVIC_IPR_7to4_REG   *((volatile int32u *)0xE000E404u)
#define	NVIC_IPR_7to4_ADDR   (0xE000E404u)
#define	NVIC_IPR_7to4_RESET   (0x00000000u)
#define	NVIC_IPR_7to4_PRI_7   (0xFF000000u)
#define	NVIC_IPR_7to4_PRI_7_MASK   (0xFF000000u)
#define	NVIC_IPR_7to4_PRI_7_BIT   (24)
#define	NVIC_IPR_7to4_PRI_7_BITS   (8)
#define	NVIC_IPR_7to4_PRI_6   (0x00FF0000u)
#define	NVIC_IPR_7to4_PRI_6_MASK   (0x00FF0000u)
#define	NVIC_IPR_7to4_PRI_6_BIT   (16)
#define	NVIC_IPR_7to4_PRI_6_BITS   (8)
#define	NVIC_IPR_7to4_PRI_5   (0x0000FF00u)
#define	NVIC_IPR_7to4_PRI_5_MASK   (0x0000FF00u)
#define	NVIC_IPR_7to4_PRI_5_BIT   (8)
#define	NVIC_IPR_7to4_PRI_5_BITS   (8)
#define	NVIC_IPR_7to4_PRI_4   (0x000000FFu)
#define	NVIC_IPR_7to4_PRI_4_MASK   (0x000000FFu)
#define	NVIC_IPR_7to4_PRI_4_BIT   (0)
#define	NVIC_IPR_7to4_PRI_4_BITS   (8)
#define	NVIC_IPR_11to8   *((volatile int32u *)0xE000E408u)
#define	NVIC_IPR_11to8_REG   *((volatile int32u *)0xE000E408u)
#define	NVIC_IPR_11to8_ADDR   (0xE000E408u)
#define	NVIC_IPR_11to8_RESET   (0x00000000u)
#define	NVIC_IPR_11to8_PRI_11   (0xFF000000u)
#define	NVIC_IPR_11to8_PRI_11_MASK   (0xFF000000u)
#define	NVIC_IPR_11to8_PRI_11_BIT   (24)
#define	NVIC_IPR_11to8_PRI_11_BITS   (8)
#define	NVIC_IPR_11to8_PRI_10   (0x00FF0000u)
#define	NVIC_IPR_11to8_PRI_10_MASK   (0x00FF0000u)
#define	NVIC_IPR_11to8_PRI_10_BIT   (16)
#define	NVIC_IPR_11to8_PRI_10_BITS   (8)
#define	NVIC_IPR_11to8_PRI_9   (0x0000FF00u)
#define	NVIC_IPR_11to8_PRI_9_MASK   (0x0000FF00u)
#define	NVIC_IPR_11to8_PRI_9_BIT   (8)
#define	NVIC_IPR_11to8_PRI_9_BITS   (8)
#define	NVIC_IPR_11to8_PRI_8   (0x000000FFu)
#define	NVIC_IPR_11to8_PRI_8_MASK   (0x000000FFu)
#define	NVIC_IPR_11to8_PRI_8_BIT   (0)
#define	NVIC_IPR_11to8_PRI_8_BITS   (8)
#define	NVIC_IPR_15to12   *((volatile int32u *)0xE000E40Cu)
#define	NVIC_IPR_15to12_REG   *((volatile int32u *)0xE000E40Cu)
#define	NVIC_IPR_15to12_ADDR   (0xE000E40Cu)
#define	NVIC_IPR_15to12_RESET   (0x00000000u)
#define	NVIC_IPR_15to12_PRI_15   (0xFF000000u)
#define	NVIC_IPR_15to12_PRI_15_MASK   (0xFF000000u)
#define	NVIC_IPR_15to12_PRI_15_BIT   (24)
#define	NVIC_IPR_15to12_PRI_15_BITS   (8)
#define	NVIC_IPR_15to12_PRI_14   (0x00FF0000u)
#define	NVIC_IPR_15to12_PRI_14_MASK   (0x00FF0000u)
#define	NVIC_IPR_15to12_PRI_14_BIT   (16)
#define	NVIC_IPR_15to12_PRI_14_BITS   (8)
#define	NVIC_IPR_15to12_PRI_13   (0x0000FF00u)
#define	NVIC_IPR_15to12_PRI_13_MASK   (0x0000FF00u)
#define	NVIC_IPR_15to12_PRI_13_BIT   (8)
#define	NVIC_IPR_15to12_PRI_13_BITS   (8)
#define	NVIC_IPR_15to12_PRI_12   (0x000000FFu)
#define	NVIC_IPR_15to12_PRI_12_MASK   (0x000000FFu)
#define	NVIC_IPR_15to12_PRI_12_BIT   (0)
#define	NVIC_IPR_15to12_PRI_12_BITS   (8)
#define	NVIC_IPR_19to16   *((volatile int32u *)0xE000E410u)
#define	NVIC_IPR_19to16_REG   *((volatile int32u *)0xE000E410u)
#define	NVIC_IPR_19to16_ADDR   (0xE000E410u)
#define	NVIC_IPR_19to16_RESET   (0x00000000u)
#define	NVIC_IPR_19to16_PRI_19   (0xFF000000u)
#define	NVIC_IPR_19to16_PRI_19_MASK   (0xFF000000u)
#define	NVIC_IPR_19to16_PRI_19_BIT   (24)
#define	NVIC_IPR_19to16_PRI_19_BITS   (8)
#define	NVIC_IPR_19to16_PRI_18   (0x00FF0000u)
#define	NVIC_IPR_19to16_PRI_18_MASK   (0x00FF0000u)
#define	NVIC_IPR_19to16_PRI_18_BIT   (16)
#define	NVIC_IPR_19to16_PRI_18_BITS   (8)
#define	NVIC_IPR_19to16_PRI_17   (0x0000FF00u)
#define	NVIC_IPR_19to16_PRI_17_MASK   (0x0000FF00u)
#define	NVIC_IPR_19to16_PRI_17_BIT   (8)
#define	NVIC_IPR_19to16_PRI_17_BITS   (8)
#define	NVIC_IPR_19to16_PRI_16   (0x000000FFu)
#define	NVIC_IPR_19to16_PRI_16_MASK   (0x000000FFu)
#define	NVIC_IPR_19to16_PRI_16_BIT   (0)
#define	NVIC_IPR_19to16_PRI_16_BITS   (8)
#define	SCS_CPUID   *((volatile int32u *)0xE000ED00u)
#define	SCS_CPUID_REG   *((volatile int32u *)0xE000ED00u)
#define	SCS_CPUID_ADDR   (0xE000ED00u)
#define	SCS_CPUID_RESET   (0x411FC231u)
#define	SCS_CPUID_IMPLEMENTER   (0xFF000000u)
#define	SCS_CPUID_IMPLEMENTER_MASK   (0xFF000000u)
#define	SCS_CPUID_IMPLEMENTER_BIT   (24)
#define	SCS_CPUID_IMPLEMENTER_BITS   (8)
#define	SCS_CPUID_VARIANT   (0x00F00000u)
#define	SCS_CPUID_VARIANT_MASK   (0x00F00000u)
#define	SCS_CPUID_VARIANT_BIT   (20)
#define	SCS_CPUID_VARIANT_BITS   (4)
#define	SCS_CPUID_CONSTANT   (0x000F0000u)
#define	SCS_CPUID_CONSTANT_MASK   (0x000F0000u)
#define	SCS_CPUID_CONSTANT_BIT   (16)
#define	SCS_CPUID_CONSTANT_BITS   (4)
#define	SCS_CPUID_PARTNO   (0x0000FFF0u)
#define	SCS_CPUID_PARTNO_MASK   (0x0000FFF0u)
#define	SCS_CPUID_PARTNO_BIT   (4)
#define	SCS_CPUID_PARTNO_BITS   (12)
#define	SCS_CPUID_REVISION   (0x0000000Fu)
#define	SCS_CPUID_REVISION_MASK   (0x0000000Fu)
#define	SCS_CPUID_REVISION_BIT   (0)
#define	SCS_CPUID_REVISION_BITS   (4)
#define	SCS_ICSR   *((volatile int32u *)0xE000ED04u)
#define	SCS_ICSR_REG   *((volatile int32u *)0xE000ED04u)
#define	SCS_ICSR_ADDR   (0xE000ED04u)
#define	SCS_ICSR_RESET   (0x00000000u)
#define	SCS_ICSR_NMIPENDSET   (0x80000000u)
#define	SCS_ICSR_NMIPENDSET_MASK   (0x80000000u)
#define	SCS_ICSR_NMIPENDSET_BIT   (31)
#define	SCS_ICSR_NMIPENDSET_BITS   (1)
#define	SCS_ICSR_PENDSVSET   (0x10000000u)
#define	SCS_ICSR_PENDSVSET_MASK   (0x10000000u)
#define	SCS_ICSR_PENDSVSET_BIT   (28)
#define	SCS_ICSR_PENDSVSET_BITS   (1)
#define	SCS_ICSR_PENDSVCLR   (0x08000000u)
#define	SCS_ICSR_PENDSVCLR_MASK   (0x08000000u)
#define	SCS_ICSR_PENDSVCLR_BIT   (27)
#define	SCS_ICSR_PENDSVCLR_BITS   (1)
#define	SCS_ICSR_PENDSTSET   (0x04000000u)
#define	SCS_ICSR_PENDSTSET_MASK   (0x04000000u)
#define	SCS_ICSR_PENDSTSET_BIT   (26)
#define	SCS_ICSR_PENDSTSET_BITS   (1)
#define	SCS_ICSR_PENDSTCLR   (0x02000000u)
#define	SCS_ICSR_PENDSTCLR_MASK   (0x02000000u)
#define	SCS_ICSR_PENDSTCLR_BIT   (25)
#define	SCS_ICSR_PENDSTCLR_BITS   (1)
#define	SCS_ICSR_ISRPREEMPT   (0x00800000u)
#define	SCS_ICSR_ISRPREEMPT_MASK   (0x00800000u)
#define	SCS_ICSR_ISRPREEMPT_BIT   (23)
#define	SCS_ICSR_ISRPREEMPT_BITS   (1)
#define	SCS_ICSR_ISRPENDING   (0x00400000u)
#define	SCS_ICSR_ISRPENDING_MASK   (0x00400000u)
#define	SCS_ICSR_ISRPENDING_BIT   (22)
#define	SCS_ICSR_ISRPENDING_BITS   (1)
#define	SCS_ICSR_VECTPENDING   (0x001FF000u)
#define	SCS_ICSR_VECTPENDING_MASK   (0x001FF000u)
#define	SCS_ICSR_VECTPENDING_BIT   (12)
#define	SCS_ICSR_VECTPENDING_BITS   (9)
#define	SCS_ICSR_RETTOBASE   (0x00000800u)
#define	SCS_ICSR_RETTOBASE_MASK   (0x00000800u)
#define	SCS_ICSR_RETTOBASE_BIT   (11)
#define	SCS_ICSR_RETTOBASE_BITS   (1)
#define	SCS_ICSR_VECACTIVE   (0x000001FFu)
#define	SCS_ICSR_VECACTIVE_MASK   (0x000001FFu)
#define	SCS_ICSR_VECACTIVE_BIT   (0)
#define	SCS_ICSR_VECACTIVE_BITS   (9)
#define	SCS_VTOR   *((volatile int32u *)0xE000ED08u)
#define	SCS_VTOR_REG   *((volatile int32u *)0xE000ED08u)
#define	SCS_VTOR_ADDR   (0xE000ED08u)
#define	SCS_VTOR_RESET   (0x00000000u)
#define	SCS_VTOR_TBLBASE   (0x20000000u)
#define	SCS_VTOR_TBLBASE_MASK   (0x20000000u)
#define	SCS_VTOR_TBLBASE_BIT   (29)
#define	SCS_VTOR_TBLBASE_BITS   (1)
#define	SCS_VTOR_TBLOFF   (0x1FFFFF00u)
#define	SCS_VTOR_TBLOFF_MASK   (0x1FFFFF00u)
#define	SCS_VTOR_TBLOFF_BIT   (8)
#define	SCS_VTOR_TBLOFF_BITS   (21)
#define	SCS_AIRCR   *((volatile int32u *)0xE000ED0Cu)
#define	SCS_AIRCR_REG   *((volatile int32u *)0xE000ED0Cu)
#define	SCS_AIRCR_ADDR   (0xE000ED0Cu)
#define	SCS_AIRCR_RESET   (0x00000000u)
#define	SCS_AIRCR_VECTKEYSTAT   (0xFFFF0000u)
#define	SCS_AIRCR_VECTKEYSTAT_MASK   (0xFFFF0000u)
#define	SCS_AIRCR_VECTKEYSTAT_BIT   (16)
#define	SCS_AIRCR_VECTKEYSTAT_BITS   (16)
#define	SCS_AIRCR_VECTKEY   (0xFFFF0000u)
#define	SCS_AIRCR_VECTKEY_MASK   (0xFFFF0000u)
#define	SCS_AIRCR_VECTKEY_BIT   (16)
#define	SCS_AIRCR_VECTKEY_BITS   (16)
#define	SCS_AIRCR_ENDIANESS   (0x00008000u)
#define	SCS_AIRCR_ENDIANESS_MASK   (0x00008000u)
#define	SCS_AIRCR_ENDIANESS_BIT   (15)
#define	SCS_AIRCR_ENDIANESS_BITS   (1)
#define	SCS_AIRCR_PRIGROUP   (0x00000700u)
#define	SCS_AIRCR_PRIGROUP_MASK   (0x00000700u)
#define	SCS_AIRCR_PRIGROUP_BIT   (8)
#define	SCS_AIRCR_PRIGROUP_BITS   (3)
#define	SCS_AIRCR_SYSRESETREQ   (0x00000004u)
#define	SCS_AIRCR_SYSRESETREQ_MASK   (0x00000004u)
#define	SCS_AIRCR_SYSRESETREQ_BIT   (2)
#define	SCS_AIRCR_SYSRESETREQ_BITS   (1)
#define	SCS_AIRCR_VECTCLRACTIVE   (0x00000002u)
#define	SCS_AIRCR_VECTCLRACTIVE_MASK   (0x00000002u)
#define	SCS_AIRCR_VECTCLRACTIVE_BIT   (1)
#define	SCS_AIRCR_VECTCLRACTIVE_BITS   (1)
#define	SCS_AIRCR_VECTRESET   (0x00000001u)
#define	SCS_AIRCR_VECTRESET_MASK   (0x00000001u)
#define	SCS_AIRCR_VECTRESET_BIT   (0)
#define	SCS_AIRCR_VECTRESET_BITS   (1)
#define	SCS_SCR   *((volatile int32u *)0xE000ED10u)
#define	SCS_SCR_REG   *((volatile int32u *)0xE000ED10u)
#define	SCS_SCR_ADDR   (0xE000ED10u)
#define	SCS_SCR_RESET   (0x00000000u)
#define	SCS_SCR_SEVONPEND   (0x00000010u)
#define	SCS_SCR_SEVONPEND_MASK   (0x00000010u)
#define	SCS_SCR_SEVONPEND_BIT   (4)
#define	SCS_SCR_SEVONPEND_BITS   (1)
#define	SCS_SCR_SLEEPDEEP   (0x00000004u)
#define	SCS_SCR_SLEEPDEEP_MASK   (0x00000004u)
#define	SCS_SCR_SLEEPDEEP_BIT   (2)
#define	SCS_SCR_SLEEPDEEP_BITS   (1)
#define	SCS_SCR_SLEEPONEXIT   (0x00000002u)
#define	SCS_SCR_SLEEPONEXIT_MASK   (0x00000002u)
#define	SCS_SCR_SLEEPONEXIT_BIT   (1)
#define	SCS_SCR_SLEEPONEXIT_BITS   (1)
#define	SCS_CCR   *((volatile int32u *)0xE000ED14u)
#define	SCS_CCR_REG   *((volatile int32u *)0xE000ED14u)
#define	SCS_CCR_ADDR   (0xE000ED14u)
#define	SCS_CCR_RESET   (0x00000000u)
#define	SCS_CCR_STKALIGN   (0x00000200u)
#define	SCS_CCR_STKALIGN_MASK   (0x00000200u)
#define	SCS_CCR_STKALIGN_BIT   (9)
#define	SCS_CCR_STKALIGN_BITS   (1)
#define	SCS_CCR_BFHFNMIGN   (0x00000100u)
#define	SCS_CCR_BFHFNMIGN_MASK   (0x00000100u)
#define	SCS_CCR_BFHFNMIGN_BIT   (8)
#define	SCS_CCR_BFHFNMIGN_BITS   (1)
#define	SCS_CCR_DIV_0_TRP   (0x00000010u)
#define	SCS_CCR_DIV_0_TRP_MASK   (0x00000010u)
#define	SCS_CCR_DIV_0_TRP_BIT   (4)
#define	SCS_CCR_DIV_0_TRP_BITS   (1)
#define	SCS_CCR_UNALIGN_TRP   (0x00000008u)
#define	SCS_CCR_UNALIGN_TRP_MASK   (0x00000008u)
#define	SCS_CCR_UNALIGN_TRP_BIT   (3)
#define	SCS_CCR_UNALIGN_TRP_BITS   (1)
#define	SCS_CCR_USERSETMPEND   (0x00000002u)
#define	SCS_CCR_USERSETMPEND_MASK   (0x00000002u)
#define	SCS_CCR_USERSETMPEND_BIT   (1)
#define	SCS_CCR_USERSETMPEND_BITS   (1)
#define	SCS_CCR_NONBASETHRDENA   (0x00000001u)
#define	SCS_CCR_NONBASETHRDENA_MASK   (0x00000001u)
#define	SCS_CCR_NONBASETHRDENA_BIT   (0)
#define	SCS_CCR_NONBASETHRDENA_BITS   (1)
#define	SCS_SHPR_7to4   *((volatile int32u *)0xE000ED18u)
#define	SCS_SHPR_7to4_REG   *((volatile int32u *)0xE000ED18u)
#define	SCS_SHPR_7to4_ADDR   (0xE000ED18u)
#define	SCS_SHPR_7to4_RESET   (0x00000000u)
#define	SCS_SHPR_7to4_PRI_7   (0xFF000000u)
#define	SCS_SHPR_7to4_PRI_7_MASK   (0xFF000000u)
#define	SCS_SHPR_7to4_PRI_7_BIT   (24)
#define	SCS_SHPR_7to4_PRI_7_BITS   (8)
#define	SCS_SHPR_7to4_PRI_6   (0x00FF0000u)
#define	SCS_SHPR_7to4_PRI_6_MASK   (0x00FF0000u)
#define	SCS_SHPR_7to4_PRI_6_BIT   (16)
#define	SCS_SHPR_7to4_PRI_6_BITS   (8)
#define	SCS_SHPR_7to4_PRI_5   (0x0000FF00u)
#define	SCS_SHPR_7to4_PRI_5_MASK   (0x0000FF00u)
#define	SCS_SHPR_7to4_PRI_5_BIT   (8)
#define	SCS_SHPR_7to4_PRI_5_BITS   (8)
#define	SCS_SHPR_7to4_PRI_4   (0x000000FFu)
#define	SCS_SHPR_7to4_PRI_4_MASK   (0x000000FFu)
#define	SCS_SHPR_7to4_PRI_4_BIT   (0)
#define	SCS_SHPR_7to4_PRI_4_BITS   (8)
#define	SCS_SHPR_11to8   *((volatile int32u *)0xE000ED1Cu)
#define	SCS_SHPR_11to8_REG   *((volatile int32u *)0xE000ED1Cu)
#define	SCS_SHPR_11to8_ADDR   (0xE000ED1Cu)
#define	SCS_SHPR_11to8_RESET   (0x00000000u)
#define	SCS_SHPR_11to8_PRI_11   (0xFF000000u)
#define	SCS_SHPR_11to8_PRI_11_MASK   (0xFF000000u)
#define	SCS_SHPR_11to8_PRI_11_BIT   (24)
#define	SCS_SHPR_11to8_PRI_11_BITS   (8)
#define	SCS_SHPR_11to8_PRI_10   (0x00FF0000u)
#define	SCS_SHPR_11to8_PRI_10_MASK   (0x00FF0000u)
#define	SCS_SHPR_11to8_PRI_10_BIT   (16)
#define	SCS_SHPR_11to8_PRI_10_BITS   (8)
#define	SCS_SHPR_11to8_PRI_9   (0x0000FF00u)
#define	SCS_SHPR_11to8_PRI_9_MASK   (0x0000FF00u)
#define	SCS_SHPR_11to8_PRI_9_BIT   (8)
#define	SCS_SHPR_11to8_PRI_9_BITS   (8)
#define	SCS_SHPR_11to8_PRI_8   (0x000000FFu)
#define	SCS_SHPR_11to8_PRI_8_MASK   (0x000000FFu)
#define	SCS_SHPR_11to8_PRI_8_BIT   (0)
#define	SCS_SHPR_11to8_PRI_8_BITS   (8)
#define	SCS_SHPR_15to12   *((volatile int32u *)0xE000ED20u)
#define	SCS_SHPR_15to12_REG   *((volatile int32u *)0xE000ED20u)
#define	SCS_SHPR_15to12_ADDR   (0xE000ED20u)
#define	SCS_SHPR_15to12_RESET   (0x00000000u)
#define	SCS_SHPR_15to12_PRI_15   (0xFF000000u)
#define	SCS_SHPR_15to12_PRI_15_MASK   (0xFF000000u)
#define	SCS_SHPR_15to12_PRI_15_BIT   (24)
#define	SCS_SHPR_15to12_PRI_15_BITS   (8)
#define	SCS_SHPR_15to12_PRI_14   (0x00FF0000u)
#define	SCS_SHPR_15to12_PRI_14_MASK   (0x00FF0000u)
#define	SCS_SHPR_15to12_PRI_14_BIT   (16)
#define	SCS_SHPR_15to12_PRI_14_BITS   (8)
#define	SCS_SHPR_15to12_PRI_13   (0x0000FF00u)
#define	SCS_SHPR_15to12_PRI_13_MASK   (0x0000FF00u)
#define	SCS_SHPR_15to12_PRI_13_BIT   (8)
#define	SCS_SHPR_15to12_PRI_13_BITS   (8)
#define	SCS_SHPR_15to12_PRI_12   (0x000000FFu)
#define	SCS_SHPR_15to12_PRI_12_MASK   (0x000000FFu)
#define	SCS_SHPR_15to12_PRI_12_BIT   (0)
#define	SCS_SHPR_15to12_PRI_12_BITS   (8)
#define	SCS_SHCSR   *((volatile int32u *)0xE000ED24u)
#define	SCS_SHCSR_REG   *((volatile int32u *)0xE000ED24u)
#define	SCS_SHCSR_ADDR   (0xE000ED24u)
#define	SCS_SHCSR_RESET   (0x00000000u)
#define	SCS_SHCSR_USGFAULTENA   (0x00040000u)
#define	SCS_SHCSR_USGFAULTENA_MASK   (0x00040000u)
#define	SCS_SHCSR_USGFAULTENA_BIT   (18)
#define	SCS_SHCSR_USGFAULTENA_BITS   (1)
#define	SCS_SHCSR_BUSFAULTENA   (0x00020000u)
#define	SCS_SHCSR_BUSFAULTENA_MASK   (0x00020000u)
#define	SCS_SHCSR_BUSFAULTENA_BIT   (17)
#define	SCS_SHCSR_BUSFAULTENA_BITS   (1)
#define	SCS_SHCSR_MEMFAULTENA   (0x00010000u)
#define	SCS_SHCSR_MEMFAULTENA_MASK   (0x00010000u)
#define	SCS_SHCSR_MEMFAULTENA_BIT   (16)
#define	SCS_SHCSR_MEMFAULTENA_BITS   (1)
#define	SCS_SHCSR_SVCALLPENDED   (0x00008000u)
#define	SCS_SHCSR_SVCALLPENDED_MASK   (0x00008000u)
#define	SCS_SHCSR_SVCALLPENDED_BIT   (15)
#define	SCS_SHCSR_SVCALLPENDED_BITS   (1)
#define	SCS_SHCSR_BUSFAULTPENDED   (0x00004000u)
#define	SCS_SHCSR_BUSFAULTPENDED_MASK   (0x00004000u)
#define	SCS_SHCSR_BUSFAULTPENDED_BIT   (14)
#define	SCS_SHCSR_BUSFAULTPENDED_BITS   (1)
#define	SCS_SHCSR_MEMFAULTPENDED   (0x00002000u)
#define	SCS_SHCSR_MEMFAULTPENDED_MASK   (0x00002000u)
#define	SCS_SHCSR_MEMFAULTPENDED_BIT   (13)
#define	SCS_SHCSR_MEMFAULTPENDED_BITS   (1)
#define	SCS_SHCSR_USGFAULTPENDED   (0x00001000u)
#define	SCS_SHCSR_USGFAULTPENDED_MASK   (0x00001000u)
#define	SCS_SHCSR_USGFAULTPENDED_BIT   (12)
#define	SCS_SHCSR_USGFAULTPENDED_BITS   (1)
#define	SCS_SHCSR_SYSTICKACT   (0x00000800u)
#define	SCS_SHCSR_SYSTICKACT_MASK   (0x00000800u)
#define	SCS_SHCSR_SYSTICKACT_BIT   (11)
#define	SCS_SHCSR_SYSTICKACT_BITS   (1)
#define	SCS_SHCSR_PENDSVACT   (0x00000400u)
#define	SCS_SHCSR_PENDSVACT_MASK   (0x00000400u)
#define	SCS_SHCSR_PENDSVACT_BIT   (10)
#define	SCS_SHCSR_PENDSVACT_BITS   (1)
#define	SCS_SHCSR_MONITORACT   (0x00000100u)
#define	SCS_SHCSR_MONITORACT_MASK   (0x00000100u)
#define	SCS_SHCSR_MONITORACT_BIT   (8)
#define	SCS_SHCSR_MONITORACT_BITS   (1)
#define	SCS_SHCSR_SVCALLACT   (0x00000080u)
#define	SCS_SHCSR_SVCALLACT_MASK   (0x00000080u)
#define	SCS_SHCSR_SVCALLACT_BIT   (7)
#define	SCS_SHCSR_SVCALLACT_BITS   (1)
#define	SCS_SHCSR_USGFAULTACT   (0x00000008u)
#define	SCS_SHCSR_USGFAULTACT_MASK   (0x00000008u)
#define	SCS_SHCSR_USGFAULTACT_BIT   (3)
#define	SCS_SHCSR_USGFAULTACT_BITS   (1)
#define	SCS_SHCSR_BUSFAULTACT   (0x00000002u)
#define	SCS_SHCSR_BUSFAULTACT_MASK   (0x00000002u)
#define	SCS_SHCSR_BUSFAULTACT_BIT   (1)
#define	SCS_SHCSR_BUSFAULTACT_BITS   (1)
#define	SCS_SHCSR_MEMFAULTACT   (0x00000001u)
#define	SCS_SHCSR_MEMFAULTACT_MASK   (0x00000001u)
#define	SCS_SHCSR_MEMFAULTACT_BIT   (0)
#define	SCS_SHCSR_MEMFAULTACT_BITS   (1)
#define	SCS_CFSR   *((volatile int32u *)0xE000ED28u)
#define	SCS_CFSR_REG   *((volatile int32u *)0xE000ED28u)
#define	SCS_CFSR_ADDR   (0xE000ED28u)
#define	SCS_CFSR_RESET   (0x00000000u)
#define	SCS_CFSR_DIVBYZERO   (0x02000000u)
#define	SCS_CFSR_DIVBYZERO_MASK   (0x02000000u)
#define	SCS_CFSR_DIVBYZERO_BIT   (25)
#define	SCS_CFSR_DIVBYZERO_BITS   (1)
#define	SCS_CFSR_UNALIGNED   (0x01000000u)
#define	SCS_CFSR_UNALIGNED_MASK   (0x01000000u)
#define	SCS_CFSR_UNALIGNED_BIT   (24)
#define	SCS_CFSR_UNALIGNED_BITS   (1)
#define	SCS_CFSR_NOCP   (0x00080000u)
#define	SCS_CFSR_NOCP_MASK   (0x00080000u)
#define	SCS_CFSR_NOCP_BIT   (19)
#define	SCS_CFSR_NOCP_BITS   (1)
#define	SCS_CFSR_INVPC   (0x00040000u)
#define	SCS_CFSR_INVPC_MASK   (0x00040000u)
#define	SCS_CFSR_INVPC_BIT   (18)
#define	SCS_CFSR_INVPC_BITS   (1)
#define	SCS_CFSR_INVSTATE   (0x00020000u)
#define	SCS_CFSR_INVSTATE_MASK   (0x00020000u)
#define	SCS_CFSR_INVSTATE_BIT   (17)
#define	SCS_CFSR_INVSTATE_BITS   (1)
#define	SCS_CFSR_UNDEFINSTR   (0x00010000u)
#define	SCS_CFSR_UNDEFINSTR_MASK   (0x00010000u)
#define	SCS_CFSR_UNDEFINSTR_BIT   (16)
#define	SCS_CFSR_UNDEFINSTR_BITS   (1)
#define	SCS_CFSR_BFARVALID   (0x00008000u)
#define	SCS_CFSR_BFARVALID_MASK   (0x00008000u)
#define	SCS_CFSR_BFARVALID_BIT   (15)
#define	SCS_CFSR_BFARVALID_BITS   (1)
#define	SCS_CFSR_STKERR   (0x00001000u)
#define	SCS_CFSR_STKERR_MASK   (0x00001000u)
#define	SCS_CFSR_STKERR_BIT   (12)
#define	SCS_CFSR_STKERR_BITS   (1)
#define	SCS_CFSR_UNSTKERR   (0x00000800u)
#define	SCS_CFSR_UNSTKERR_MASK   (0x00000800u)
#define	SCS_CFSR_UNSTKERR_BIT   (11)
#define	SCS_CFSR_UNSTKERR_BITS   (1)
#define	SCS_CFSR_IMPRECISERR   (0x00000400u)
#define	SCS_CFSR_IMPRECISERR_MASK   (0x00000400u)
#define	SCS_CFSR_IMPRECISERR_BIT   (10)
#define	SCS_CFSR_IMPRECISERR_BITS   (1)
#define	SCS_CFSR_PRECISERR   (0x00000200u)
#define	SCS_CFSR_PRECISERR_MASK   (0x00000200u)
#define	SCS_CFSR_PRECISERR_BIT   (9)
#define	SCS_CFSR_PRECISERR_BITS   (1)
#define	SCS_CFSR_IBUSERR   (0x00000100u)
#define	SCS_CFSR_IBUSERR_MASK   (0x00000100u)
#define	SCS_CFSR_IBUSERR_BIT   (8)
#define	SCS_CFSR_IBUSERR_BITS   (1)
#define	SCS_CFSR_MMARVALID   (0x00000080u)
#define	SCS_CFSR_MMARVALID_MASK   (0x00000080u)
#define	SCS_CFSR_MMARVALID_BIT   (7)
#define	SCS_CFSR_MMARVALID_BITS   (1)
#define	SCS_CFSR_MSTKERR   (0x00000010u)
#define	SCS_CFSR_MSTKERR_MASK   (0x00000010u)
#define	SCS_CFSR_MSTKERR_BIT   (4)
#define	SCS_CFSR_MSTKERR_BITS   (1)
#define	SCS_CFSR_MUNSTKERR   (0x00000008u)
#define	SCS_CFSR_MUNSTKERR_MASK   (0x00000008u)
#define	SCS_CFSR_MUNSTKERR_BIT   (3)
#define	SCS_CFSR_MUNSTKERR_BITS   (1)
#define	SCS_CFSR_DACCVIOL   (0x00000002u)
#define	SCS_CFSR_DACCVIOL_MASK   (0x00000002u)
#define	SCS_CFSR_DACCVIOL_BIT   (1)
#define	SCS_CFSR_DACCVIOL_BITS   (1)
#define	SCS_CFSR_IACCVIOL   (0x00000001u)
#define	SCS_CFSR_IACCVIOL_MASK   (0x00000001u)
#define	SCS_CFSR_IACCVIOL_BIT   (0)
#define	SCS_CFSR_IACCVIOL_BITS   (1)
#define	SCS_HFSR   *((volatile int32u *)0xE000ED2Cu)
#define	SCS_HFSR_REG   *((volatile int32u *)0xE000ED2Cu)
#define	SCS_HFSR_ADDR   (0xE000ED2Cu)
#define	SCS_HFSR_RESET   (0x00000000u)
#define	SCS_HFSR_DEBUGEVT   (0x80000000u)
#define	SCS_HFSR_DEBUGEVT_MASK   (0x80000000u)
#define	SCS_HFSR_DEBUGEVT_BIT   (31)
#define	SCS_HFSR_DEBUGEVT_BITS   (1)
#define	SCS_HFSR_FORCED   (0x40000000u)
#define	SCS_HFSR_FORCED_MASK   (0x40000000u)
#define	SCS_HFSR_FORCED_BIT   (30)
#define	SCS_HFSR_FORCED_BITS   (1)
#define	SCS_HFSR_VECTTBL   (0x00000002u)
#define	SCS_HFSR_VECTTBL_MASK   (0x00000002u)
#define	SCS_HFSR_VECTTBL_BIT   (1)
#define	SCS_HFSR_VECTTBL_BITS   (1)
#define	SCS_DFSR   *((volatile int32u *)0xE000ED30u)
#define	SCS_DFSR_REG   *((volatile int32u *)0xE000ED30u)
#define	SCS_DFSR_ADDR   (0xE000ED30u)
#define	SCS_DFSR_RESET   (0x00000000u)
#define	SCS_DFSR_EXTERNAL   (0x00000010u)
#define	SCS_DFSR_EXTERNAL_MASK   (0x00000010u)
#define	SCS_DFSR_EXTERNAL_BIT   (4)
#define	SCS_DFSR_EXTERNAL_BITS   (1)
#define	SCS_DFSR_VCATCH   (0x00000008u)
#define	SCS_DFSR_VCATCH_MASK   (0x00000008u)
#define	SCS_DFSR_VCATCH_BIT   (3)
#define	SCS_DFSR_VCATCH_BITS   (1)
#define	SCS_DFSR_DWTTRAP   (0x00000004u)
#define	SCS_DFSR_DWTTRAP_MASK   (0x00000004u)
#define	SCS_DFSR_DWTTRAP_BIT   (2)
#define	SCS_DFSR_DWTTRAP_BITS   (1)
#define	SCS_DFSR_BKPT   (0x00000002u)
#define	SCS_DFSR_BKPT_MASK   (0x00000002u)
#define	SCS_DFSR_BKPT_BIT   (1)
#define	SCS_DFSR_BKPT_BITS   (1)
#define	SCS_DFSR_HALTED   (0x00000001u)
#define	SCS_DFSR_HALTED_MASK   (0x00000001u)
#define	SCS_DFSR_HALTED_BIT   (0)
#define	SCS_DFSR_HALTED_BITS   (1)
#define	SCS_MMAR   *((volatile int32u *)0xE000ED34u)
#define	SCS_MMAR_REG   *((volatile int32u *)0xE000ED34u)
#define	SCS_MMAR_ADDR   (0xE000ED34u)
#define	SCS_MMAR_RESET   (0x00000000u)
#define	SCS_MMAR_ADDRESS   (0xFFFFFFFFu)
#define	SCS_MMAR_ADDRESS_MASK   (0xFFFFFFFFu)
#define	SCS_MMAR_ADDRESS_BIT   (0)
#define	SCS_MMAR_ADDRESS_BITS   (32)
#define	SCS_BFAR   *((volatile int32u *)0xE000ED38u)
#define	SCS_BFAR_REG   *((volatile int32u *)0xE000ED38u)
#define	SCS_BFAR_ADDR   (0xE000ED38u)
#define	SCS_BFAR_RESET   (0x00000000u)
#define	SCS_BFAR_ADDRESS   (0xFFFFFFFFu)
#define	SCS_BFAR_ADDRESS_MASK   (0xFFFFFFFFu)
#define	SCS_BFAR_ADDRESS_BIT   (0)
#define	SCS_BFAR_ADDRESS_BITS   (32)
#define	SCS_AFSR   *((volatile int32u *)0xE000ED3Cu)
#define	SCS_AFSR_REG   *((volatile int32u *)0xE000ED3Cu)
#define	SCS_AFSR_ADDR   (0xE000ED3Cu)
#define	SCS_AFSR_RESET   (0x00000000u)
#define	SCS_AFSR_WRONGSIZE   (0x00000008u)
#define	SCS_AFSR_WRONGSIZE_MASK   (0x00000008u)
#define	SCS_AFSR_WRONGSIZE_BIT   (3)
#define	SCS_AFSR_WRONGSIZE_BITS   (1)
#define	SCS_AFSR_PROTECTED   (0x00000004u)
#define	SCS_AFSR_PROTECTED_MASK   (0x00000004u)
#define	SCS_AFSR_PROTECTED_BIT   (2)
#define	SCS_AFSR_PROTECTED_BITS   (1)
#define	SCS_AFSR_RESERVED   (0x00000002u)
#define	SCS_AFSR_RESERVED_MASK   (0x00000002u)
#define	SCS_AFSR_RESERVED_BIT   (1)
#define	SCS_AFSR_RESERVED_BITS   (1)
#define	SCS_AFSR_MISSED   (0x00000001u)
#define	SCS_AFSR_MISSED_MASK   (0x00000001u)
#define	SCS_AFSR_MISSED_BIT   (0)
#define	SCS_AFSR_MISSED_BITS   (1)
#define	SCS_PFR0   *((volatile int32u *)0xE000ED40u)
#define	SCS_PFR0_REG   *((volatile int32u *)0xE000ED40u)
#define	SCS_PFR0_ADDR   (0xE000ED40u)
#define	SCS_PFR0_RESET   (0x00000030u)
#define	SCS_PFR0_FEATURE   (0xFFFFFFFFu)
#define	SCS_PFR0_FEATURE_MASK   (0xFFFFFFFFu)
#define	SCS_PFR0_FEATURE_BIT   (0)
#define	SCS_PFR0_FEATURE_BITS   (32)
#define	SCS_PFR1   *((volatile int32u *)0xE000ED44u)
#define	SCS_PFR1_REG   *((volatile int32u *)0xE000ED44u)
#define	SCS_PFR1_ADDR   (0xE000ED44u)
#define	SCS_PFR1_RESET   (0x00000200u)
#define	SCS_PFR1_FEATURE   (0xFFFFFFFFu)
#define	SCS_PFR1_FEATURE_MASK   (0xFFFFFFFFu)
#define	SCS_PFR1_FEATURE_BIT   (0)
#define	SCS_PFR1_FEATURE_BITS   (32)
#define	SCS_DFR0   *((volatile int32u *)0xE000ED48u)
#define	SCS_DFR0_REG   *((volatile int32u *)0xE000ED48u)
#define	SCS_DFR0_ADDR   (0xE000ED48u)
#define	SCS_DFR0_RESET   (0x00100000u)
#define	SCS_DFR0_FEATURE   (0xFFFFFFFFu)
#define	SCS_DFR0_FEATURE_MASK   (0xFFFFFFFFu)
#define	SCS_DFR0_FEATURE_BIT   (0)
#define	SCS_DFR0_FEATURE_BITS   (32)
#define	SCS_AFR0   *((volatile int32u *)0xE000ED4Cu)
#define	SCS_AFR0_REG   *((volatile int32u *)0xE000ED4Cu)
#define	SCS_AFR0_ADDR   (0xE000ED4Cu)
#define	SCS_AFR0_RESET   (0x00000000u)
#define	SCS_AFR0_FEATURE   (0xFFFFFFFFu)
#define	SCS_AFR0_FEATURE_MASK   (0xFFFFFFFFu)
#define	SCS_AFR0_FEATURE_BIT   (0)
#define	SCS_AFR0_FEATURE_BITS   (32)
#define	SCS_MMFR0   *((volatile int32u *)0xE000ED50u)
#define	SCS_MMFR0_REG   *((volatile int32u *)0xE000ED50u)
#define	SCS_MMFR0_ADDR   (0xE000ED50u)
#define	SCS_MMFR0_RESET   (0x00000030u)
#define	SCS_MMFR0_FEATURE   (0xFFFFFFFFu)
#define	SCS_MMFR0_FEATURE_MASK   (0xFFFFFFFFu)
#define	SCS_MMFR0_FEATURE_BIT   (0)
#define	SCS_MMFR0_FEATURE_BITS   (32)
#define	SCS_MMFR1   *((volatile int32u *)0xE000ED54u)
#define	SCS_MMFR1_REG   *((volatile int32u *)0xE000ED54u)
#define	SCS_MMFR1_ADDR   (0xE000ED54u)
#define	SCS_MMFR1_RESET   (0x00000000u)
#define	SCS_MMFR1_FEATURE   (0xFFFFFFFFu)
#define	SCS_MMFR1_FEATURE_MASK   (0xFFFFFFFFu)
#define	SCS_MMFR1_FEATURE_BIT   (0)
#define	SCS_MMFR1_FEATURE_BITS   (32)
#define	SCS_MMFR2   *((volatile int32u *)0xE000ED58u)
#define	SCS_MMFR2_REG   *((volatile int32u *)0xE000ED58u)
#define	SCS_MMFR2_ADDR   (0xE000ED58u)
#define	SCS_MMFR2_RESET   (0x00000000u)
#define	SCS_MMFR2_FEATURE   (0xFFFFFFFFu)
#define	SCS_MMFR2_FEATURE_MASK   (0xFFFFFFFFu)
#define	SCS_MMFR2_FEATURE_BIT   (0)
#define	SCS_MMFR2_FEATURE_BITS   (32)
#define	SCS_MMFR3   *((volatile int32u *)0xE000ED5Cu)
#define	SCS_MMFR3_REG   *((volatile int32u *)0xE000ED5Cu)
#define	SCS_MMFR3_ADDR   (0xE000ED5Cu)
#define	SCS_MMFR3_RESET   (0x00000000u)
#define	SCS_MMFR3_FEATURE   (0xFFFFFFFFu)
#define	SCS_MMFR3_FEATURE_MASK   (0xFFFFFFFFu)
#define	SCS_MMFR3_FEATURE_BIT   (0)
#define	SCS_MMFR3_FEATURE_BITS   (32)
#define	SCS_ISAFR0   *((volatile int32u *)0xE000ED60u)
#define	SCS_ISAFR0_REG   *((volatile int32u *)0xE000ED60u)
#define	SCS_ISAFR0_ADDR   (0xE000ED60u)
#define	SCS_ISAFR0_RESET   (0x01141110u)
#define	SCS_ISAFR0_FEATURE   (0xFFFFFFFFu)
#define	SCS_ISAFR0_FEATURE_MASK   (0xFFFFFFFFu)
#define	SCS_ISAFR0_FEATURE_BIT   (0)
#define	SCS_ISAFR0_FEATURE_BITS   (32)
#define	SCS_ISAFR1   *((volatile int32u *)0xE000ED64u)
#define	SCS_ISAFR1_REG   *((volatile int32u *)0xE000ED64u)
#define	SCS_ISAFR1_ADDR   (0xE000ED64u)
#define	SCS_ISAFR1_RESET   (0x02111000u)
#define	SCS_ISAFR1_FEATURE   (0xFFFFFFFFu)
#define	SCS_ISAFR1_FEATURE_MASK   (0xFFFFFFFFu)
#define	SCS_ISAFR1_FEATURE_BIT   (0)
#define	SCS_ISAFR1_FEATURE_BITS   (32)
#define	SCS_ISAFR2   *((volatile int32u *)0xE000ED68u)
#define	SCS_ISAFR2_REG   *((volatile int32u *)0xE000ED68u)
#define	SCS_ISAFR2_ADDR   (0xE000ED68u)
#define	SCS_ISAFR2_RESET   (0x21112231u)
#define	SCS_ISAFR2_FEATURE   (0xFFFFFFFFu)
#define	SCS_ISAFR2_FEATURE_MASK   (0xFFFFFFFFu)
#define	SCS_ISAFR2_FEATURE_BIT   (0)
#define	SCS_ISAFR2_FEATURE_BITS   (32)
#define	SCS_ISAFR3   *((volatile int32u *)0xE000ED6Cu)
#define	SCS_ISAFR3_REG   *((volatile int32u *)0xE000ED6Cu)
#define	SCS_ISAFR3_ADDR   (0xE000ED6Cu)
#define	SCS_ISAFR3_RESET   (0x11111110u)
#define	SCS_ISAFR3_FEATURE   (0xFFFFFFFFu)
#define	SCS_ISAFR3_FEATURE_MASK   (0xFFFFFFFFu)
#define	SCS_ISAFR3_FEATURE_BIT   (0)
#define	SCS_ISAFR3_FEATURE_BITS   (32)
#define	SCS_ISAFR4   *((volatile int32u *)0xE000ED70u)
#define	SCS_ISAFR4_REG   *((volatile int32u *)0xE000ED70u)
#define	SCS_ISAFR4_ADDR   (0xE000ED70u)
#define	SCS_ISAFR4_RESET   (0x01310102u)
#define	SCS_ISAFR4_FEATURE   (0xFFFFFFFFu)
#define	SCS_ISAFR4_FEATURE_MASK   (0xFFFFFFFFu)
#define	SCS_ISAFR4_FEATURE_BIT   (0)
#define	SCS_ISAFR4_FEATURE_BITS   (32)
#define	MPU_TYPE   *((volatile int32u *)0xE000ED90u)
#define	MPU_TYPE_REG   *((volatile int32u *)0xE000ED90u)
#define	MPU_TYPE_ADDR   (0xE000ED90u)
#define	MPU_TYPE_RESET   (0x00000800u)
#define	MPU_TYPE_IREGION   (0x00FF0000u)
#define	MPU_TYPE_IREGION_MASK   (0x00FF0000u)
#define	MPU_TYPE_IREGION_BIT   (16)
#define	MPU_TYPE_IREGION_BITS   (8)
#define	MPU_TYPE_DREGION   (0x0000FF00u)
#define	MPU_TYPE_DREGION_MASK   (0x0000FF00u)
#define	MPU_TYPE_DREGION_BIT   (8)
#define	MPU_TYPE_DREGION_BITS   (8)
#define	MPU_CTRL   *((volatile int32u *)0xE000ED94u)
#define	MPU_CTRL_REG   *((volatile int32u *)0xE000ED94u)
#define	MPU_CTRL_ADDR   (0xE000ED94u)
#define	MPU_CTRL_RESET   (0x00000000u)
#define	MPU_CTRL_PRIVDEFENA   (0x00000004u)
#define	MPU_CTRL_PRIVDEFENA_MASK   (0x00000004u)
#define	MPU_CTRL_PRIVDEFENA_BIT   (2)
#define	MPU_CTRL_PRIVDEFENA_BITS   (1)
#define	MPU_CTRL_HFNMIENA   (0x00000002u)
#define	MPU_CTRL_HFNMIENA_MASK   (0x00000002u)
#define	MPU_CTRL_HFNMIENA_BIT   (1)
#define	MPU_CTRL_HFNMIENA_BITS   (1)
#define	MPU_CTRL_ENABLE   (0x00000001u)
#define	MPU_CTRL_ENABLE_MASK   (0x00000001u)
#define	MPU_CTRL_ENABLE_BIT   (0)
#define	MPU_CTRL_ENABLE_BITS   (1)
#define	MPU_REGION   *((volatile int32u *)0xE000ED98u)
#define	MPU_REGION_REG   *((volatile int32u *)0xE000ED98u)
#define	MPU_REGION_ADDR   (0xE000ED98u)
#define	MPU_REGION_RESET   (0x00000000u)
#define	MPU_REGION_REGION   (0x000000FFu)
#define	MPU_REGION_REGION_MASK   (0x000000FFu)
#define	MPU_REGION_REGION_BIT   (0)
#define	MPU_REGION_REGION_BITS   (8)
#define	MPU_BASE   *((volatile int32u *)0xE000ED9Cu)
#define	MPU_BASE_REG   *((volatile int32u *)0xE000ED9Cu)
#define	MPU_BASE_ADDR   (0xE000ED9Cu)
#define	MPU_BASE_RESET   (0x00000000u)
#define	MPU_BASE_ADDRESS   (0xFFFFFFE0u)
#define	MPU_BASE_ADDRESS_MASK   (0xFFFFFFE0u)
#define	MPU_BASE_ADDRESS_BIT   (5)
#define	MPU_BASE_ADDRESS_BITS   (27)
#define	MPU_BASE_VALID   (0x00000010u)
#define	MPU_BASE_VALID_MASK   (0x00000010u)
#define	MPU_BASE_VALID_BIT   (4)
#define	MPU_BASE_VALID_BITS   (1)
#define	MPU_BASE_REGION   (0x0000000Fu)
#define	MPU_BASE_REGION_MASK   (0x0000000Fu)
#define	MPU_BASE_REGION_BIT   (0)
#define	MPU_BASE_REGION_BITS   (4)
#define	MPU_ATTR   *((volatile int32u *)0xE000EDA0u)
#define	MPU_ATTR_REG   *((volatile int32u *)0xE000EDA0u)
#define	MPU_ATTR_ADDR   (0xE000EDA0u)
#define	MPU_ATTR_RESET   (0x00000000u)
#define	MPU_ATTR_XN   (0x10000000u)
#define	MPU_ATTR_XN_MASK   (0x10000000u)
#define	MPU_ATTR_XN_BIT   (28)
#define	MPU_ATTR_XN_BITS   (1)
#define	MPU_ATTR_AP   (0x07000000u)
#define	MPU_ATTR_AP_MASK   (0x07000000u)
#define	MPU_ATTR_AP_BIT   (24)
#define	MPU_ATTR_AP_BITS   (3)
#define	MPU_ATTR_TEX   (0x00380000u)
#define	MPU_ATTR_TEX_MASK   (0x00380000u)
#define	MPU_ATTR_TEX_BIT   (19)
#define	MPU_ATTR_TEX_BITS   (3)
#define	MPU_ATTR_S   (0x00040000u)
#define	MPU_ATTR_S_MASK   (0x00040000u)
#define	MPU_ATTR_S_BIT   (18)
#define	MPU_ATTR_S_BITS   (1)
#define	MPU_ATTR_C   (0x00020000u)
#define	MPU_ATTR_C_MASK   (0x00020000u)
#define	MPU_ATTR_C_BIT   (17)
#define	MPU_ATTR_C_BITS   (1)
#define	MPU_ATTR_B   (0x00010000u)
#define	MPU_ATTR_B_MASK   (0x00010000u)
#define	MPU_ATTR_B_BIT   (16)
#define	MPU_ATTR_B_BITS   (1)
#define	MPU_ATTR_SRD   (0x0000FF00u)
#define	MPU_ATTR_SRD_MASK   (0x0000FF00u)
#define	MPU_ATTR_SRD_BIT   (8)
#define	MPU_ATTR_SRD_BITS   (8)
#define	MPU_ATTR_SIZE   (0x0000003Eu)
#define	MPU_ATTR_SIZE_MASK   (0x0000003Eu)
#define	MPU_ATTR_SIZE_BIT   (1)
#define	MPU_ATTR_SIZE_BITS   (5)
#define	MPU_ATTR_ENABLE   (0x00000001u)
#define	MPU_ATTR_ENABLE_MASK   (0x00000001u)
#define	MPU_ATTR_ENABLE_BIT   (0)
#define	MPU_ATTR_ENABLE_BITS   (1)
#define	MPU_BASE1   *((volatile int32u *)0xE000EDA4u)
#define	MPU_BASE1_REG   *((volatile int32u *)0xE000EDA4u)
#define	MPU_BASE1_ADDR   (0xE000EDA4u)
#define	MPU_BASE1_RESET   (0x00000000u)
#define	MPU_BASE1_ADDRESS   (0xFFFFFFE0u)
#define	MPU_BASE1_ADDRESS_MASK   (0xFFFFFFE0u)
#define	MPU_BASE1_ADDRESS_BIT   (5)
#define	MPU_BASE1_ADDRESS_BITS   (27)
#define	MPU_BASE1_VALID   (0x00000010u)
#define	MPU_BASE1_VALID_MASK   (0x00000010u)
#define	MPU_BASE1_VALID_BIT   (4)
#define	MPU_BASE1_VALID_BITS   (1)
#define	MPU_BASE1_REGION   (0x0000000Fu)
#define	MPU_BASE1_REGION_MASK   (0x0000000Fu)
#define	MPU_BASE1_REGION_BIT   (0)
#define	MPU_BASE1_REGION_BITS   (4)
#define	MPU_ATTR1   *((volatile int32u *)0xE000EDA8u)
#define	MPU_ATTR1_REG   *((volatile int32u *)0xE000EDA8u)
#define	MPU_ATTR1_ADDR   (0xE000EDA8u)
#define	MPU_ATTR1_RESET   (0x00000000u)
#define	MPU_ATTR1_XN   (0x10000000u)
#define	MPU_ATTR1_XN_MASK   (0x10000000u)
#define	MPU_ATTR1_XN_BIT   (28)
#define	MPU_ATTR1_XN_BITS   (1)
#define	MPU_ATTR1_AP   (0x07000000u)
#define	MPU_ATTR1_AP_MASK   (0x07000000u)
#define	MPU_ATTR1_AP_BIT   (24)
#define	MPU_ATTR1_AP_BITS   (3)
#define	MPU_ATTR1_TEX   (0x00380000u)
#define	MPU_ATTR1_TEX_MASK   (0x00380000u)
#define	MPU_ATTR1_TEX_BIT   (19)
#define	MPU_ATTR1_TEX_BITS   (3)
#define	MPU_ATTR1_S   (0x00040000u)
#define	MPU_ATTR1_S_MASK   (0x00040000u)
#define	MPU_ATTR1_S_BIT   (18)
#define	MPU_ATTR1_S_BITS   (1)
#define	MPU_ATTR1_C   (0x00020000u)
#define	MPU_ATTR1_C_MASK   (0x00020000u)
#define	MPU_ATTR1_C_BIT   (17)
#define	MPU_ATTR1_C_BITS   (1)
#define	MPU_ATTR1_B   (0x00010000u)
#define	MPU_ATTR1_B_MASK   (0x00010000u)
#define	MPU_ATTR1_B_BIT   (16)
#define	MPU_ATTR1_B_BITS   (1)
#define	MPU_ATTR1_SRD   (0x0000FF00u)
#define	MPU_ATTR1_SRD_MASK   (0x0000FF00u)
#define	MPU_ATTR1_SRD_BIT   (8)
#define	MPU_ATTR1_SRD_BITS   (8)
#define	MPU_ATTR1_SIZE   (0x0000003Eu)
#define	MPU_ATTR1_SIZE_MASK   (0x0000003Eu)
#define	MPU_ATTR1_SIZE_BIT   (1)
#define	MPU_ATTR1_SIZE_BITS   (5)
#define	MPU_ATTR1_ENABLE   (0x00000001u)
#define	MPU_ATTR1_ENABLE_MASK   (0x00000001u)
#define	MPU_ATTR1_ENABLE_BIT   (0)
#define	MPU_ATTR1_ENABLE_BITS   (1)
#define	MPU_BASE2   *((volatile int32u *)0xE000EDACu)
#define	MPU_BASE2_REG   *((volatile int32u *)0xE000EDACu)
#define	MPU_BASE2_ADDR   (0xE000EDACu)
#define	MPU_BASE2_RESET   (0x00000000u)
#define	MPU_BASE2_ADDRESS   (0xFFFFFFE0u)
#define	MPU_BASE2_ADDRESS_MASK   (0xFFFFFFE0u)
#define	MPU_BASE2_ADDRESS_BIT   (5)
#define	MPU_BASE2_ADDRESS_BITS   (27)
#define	MPU_BASE2_VALID   (0x00000010u)
#define	MPU_BASE2_VALID_MASK   (0x00000010u)
#define	MPU_BASE2_VALID_BIT   (4)
#define	MPU_BASE2_VALID_BITS   (1)
#define	MPU_BASE2_REGION   (0x0000000Fu)
#define	MPU_BASE2_REGION_MASK   (0x0000000Fu)
#define	MPU_BASE2_REGION_BIT   (0)
#define	MPU_BASE2_REGION_BITS   (4)
#define	MPU_ATTR2   *((volatile int32u *)0xE000EDB0u)
#define	MPU_ATTR2_REG   *((volatile int32u *)0xE000EDB0u)
#define	MPU_ATTR2_ADDR   (0xE000EDB0u)
#define	MPU_ATTR2_RESET   (0x00000000u)
#define	MPU_ATTR2_XN   (0x10000000u)
#define	MPU_ATTR2_XN_MASK   (0x10000000u)
#define	MPU_ATTR2_XN_BIT   (28)
#define	MPU_ATTR2_XN_BITS   (1)
#define	MPU_ATTR2_AP   (0x1F000000u)
#define	MPU_ATTR2_AP_MASK   (0x1F000000u)
#define	MPU_ATTR2_AP_BIT   (24)
#define	MPU_ATTR2_AP_BITS   (5)
#define	MPU_ATTR2_TEX   (0x00380000u)
#define	MPU_ATTR2_TEX_MASK   (0x00380000u)
#define	MPU_ATTR2_TEX_BIT   (19)
#define	MPU_ATTR2_TEX_BITS   (3)
#define	MPU_ATTR2_S   (0x00040000u)
#define	MPU_ATTR2_S_MASK   (0x00040000u)
#define	MPU_ATTR2_S_BIT   (18)
#define	MPU_ATTR2_S_BITS   (1)
#define	MPU_ATTR2_C   (0x00020000u)
#define	MPU_ATTR2_C_MASK   (0x00020000u)
#define	MPU_ATTR2_C_BIT   (17)
#define	MPU_ATTR2_C_BITS   (1)
#define	MPU_ATTR2_B   (0x00010000u)
#define	MPU_ATTR2_B_MASK   (0x00010000u)
#define	MPU_ATTR2_B_BIT   (16)
#define	MPU_ATTR2_B_BITS   (1)
#define	MPU_ATTR2_SRD   (0x0000FF00u)
#define	MPU_ATTR2_SRD_MASK   (0x0000FF00u)
#define	MPU_ATTR2_SRD_BIT   (8)
#define	MPU_ATTR2_SRD_BITS   (8)
#define	MPU_ATTR2_SIZE   (0x0000003Eu)
#define	MPU_ATTR2_SIZE_MASK   (0x0000003Eu)
#define	MPU_ATTR2_SIZE_BIT   (1)
#define	MPU_ATTR2_SIZE_BITS   (5)
#define	MPU_ATTR2_ENABLE   (0x00000003u)
#define	MPU_ATTR2_ENABLE_MASK   (0x00000003u)
#define	MPU_ATTR2_ENABLE_BIT   (0)
#define	MPU_ATTR2_ENABLE_BITS   (2)
#define	MPU_BASE3   *((volatile int32u *)0xE000EDB4u)
#define	MPU_BASE3_REG   *((volatile int32u *)0xE000EDB4u)
#define	MPU_BASE3_ADDR   (0xE000EDB4u)
#define	MPU_BASE3_RESET   (0x00000000u)
#define	MPU_BASE3_ADDRESS   (0xFFFFFFE0u)
#define	MPU_BASE3_ADDRESS_MASK   (0xFFFFFFE0u)
#define	MPU_BASE3_ADDRESS_BIT   (5)
#define	MPU_BASE3_ADDRESS_BITS   (27)
#define	MPU_BASE3_VALID   (0x00000010u)
#define	MPU_BASE3_VALID_MASK   (0x00000010u)
#define	MPU_BASE3_VALID_BIT   (4)
#define	MPU_BASE3_VALID_BITS   (1)
#define	MPU_BASE3_REGION   (0x0000000Fu)
#define	MPU_BASE3_REGION_MASK   (0x0000000Fu)
#define	MPU_BASE3_REGION_BIT   (0)
#define	MPU_BASE3_REGION_BITS   (4)
#define	MPU_ATTR3   *((volatile int32u *)0xE000EDBCu)
#define	MPU_ATTR3_REG   *((volatile int32u *)0xE000EDBCu)
#define	MPU_ATTR3_ADDR   (0xE000EDBCu)
#define	MPU_ATTR3_RESET   (0x00000000u)
#define	MPU_ATTR3_XN   (0x10000000u)
#define	MPU_ATTR3_XN_MASK   (0x10000000u)
#define	MPU_ATTR3_XN_BIT   (28)
#define	MPU_ATTR3_XN_BITS   (1)
#define	MPU_ATTR3_AP   (0x1F000000u)
#define	MPU_ATTR3_AP_MASK   (0x1F000000u)
#define	MPU_ATTR3_AP_BIT   (24)
#define	MPU_ATTR3_AP_BITS   (5)
#define	MPU_ATTR3_TEX   (0x00380000u)
#define	MPU_ATTR3_TEX_MASK   (0x00380000u)
#define	MPU_ATTR3_TEX_BIT   (19)
#define	MPU_ATTR3_TEX_BITS   (3)
#define	MPU_ATTR3_S   (0x00040000u)
#define	MPU_ATTR3_S_MASK   (0x00040000u)
#define	MPU_ATTR3_S_BIT   (18)
#define	MPU_ATTR3_S_BITS   (1)
#define	MPU_ATTR3_C   (0x00020000u)
#define	MPU_ATTR3_C_MASK   (0x00020000u)
#define	MPU_ATTR3_C_BIT   (17)
#define	MPU_ATTR3_C_BITS   (1)
#define	MPU_ATTR3_B   (0x00010000u)
#define	MPU_ATTR3_B_MASK   (0x00010000u)
#define	MPU_ATTR3_B_BIT   (16)
#define	MPU_ATTR3_B_BITS   (1)
#define	MPU_ATTR3_SRD   (0x0000FF00u)
#define	MPU_ATTR3_SRD_MASK   (0x0000FF00u)
#define	MPU_ATTR3_SRD_BIT   (8)
#define	MPU_ATTR3_SRD_BITS   (8)
#define	MPU_ATTR3_SIZE   (0x0000003Eu)
#define	MPU_ATTR3_SIZE_MASK   (0x0000003Eu)
#define	MPU_ATTR3_SIZE_BIT   (1)
#define	MPU_ATTR3_SIZE_BITS   (5)
#define	MPU_ATTR3_ENABLE   (0x00000003u)
#define	MPU_ATTR3_ENABLE_MASK   (0x00000003u)
#define	MPU_ATTR3_ENABLE_BIT   (0)
#define	MPU_ATTR3_ENABLE_BITS   (2)
#define	DEBUG_HCSR   *((volatile int32u *)0xE000EDF0u)
#define	DEBUG_HCSR_REG   *((volatile int32u *)0xE000EDF0u)
#define	DEBUG_HCSR_ADDR   (0xE000EDF0u)
#define	DEBUG_HCSR_RESET   (0x00000000u)
#define	DEBUG_HCSR_S_RESET_ST   (0x02000000u)
#define	DEBUG_HCSR_S_RESET_ST_MASK   (0x02000000u)
#define	DEBUG_HCSR_S_RESET_ST_BIT   (25)
#define	DEBUG_HCSR_S_RESET_ST_BITS   (1)
#define	DEBUG_HCSR_S_RETIRE_ST   (0x01000000u)
#define	DEBUG_HCSR_S_RETIRE_ST_MASK   (0x01000000u)
#define	DEBUG_HCSR_S_RETIRE_ST_BIT   (24)
#define	DEBUG_HCSR_S_RETIRE_ST_BITS   (1)
#define	DEBUG_HCSR_S_LOCKUP   (0x00080000u)
#define	DEBUG_HCSR_S_LOCKUP_MASK   (0x00080000u)
#define	DEBUG_HCSR_S_LOCKUP_BIT   (19)
#define	DEBUG_HCSR_S_LOCKUP_BITS   (1)
#define	DEBUG_HCSR_S_SLEEP   (0x00040000u)
#define	DEBUG_HCSR_S_SLEEP_MASK   (0x00040000u)
#define	DEBUG_HCSR_S_SLEEP_BIT   (18)
#define	DEBUG_HCSR_S_SLEEP_BITS   (1)
#define	DEBUG_HCSR_S_HALT   (0x00020000u)
#define	DEBUG_HCSR_S_HALT_MASK   (0x00020000u)
#define	DEBUG_HCSR_S_HALT_BIT   (17)
#define	DEBUG_HCSR_S_HALT_BITS   (1)
#define	DEBUG_HCSR_S_REGRDY   (0x00010000u)
#define	DEBUG_HCSR_S_REGRDY_MASK   (0x00010000u)
#define	DEBUG_HCSR_S_REGRDY_BIT   (16)
#define	DEBUG_HCSR_S_REGRDY_BITS   (1)
#define	DEBUG_HCSR_DBGKEY   (0xFFFF0000u)
#define	DEBUG_HCSR_DBGKEY_MASK   (0xFFFF0000u)
#define	DEBUG_HCSR_DBGKEY_BIT   (16)
#define	DEBUG_HCSR_DBGKEY_BITS   (16)
#define	DEBUG_HCSR_C_SNAPSTALL   (0x00000020u)
#define	DEBUG_HCSR_C_SNAPSTALL_MASK   (0x00000020u)
#define	DEBUG_HCSR_C_SNAPSTALL_BIT   (5)
#define	DEBUG_HCSR_C_SNAPSTALL_BITS   (1)
#define	DEBUG_HCSR_C_MASKINTS   (0x00000008u)
#define	DEBUG_HCSR_C_MASKINTS_MASK   (0x00000008u)
#define	DEBUG_HCSR_C_MASKINTS_BIT   (3)
#define	DEBUG_HCSR_C_MASKINTS_BITS   (1)
#define	DEBUG_HCSR_C_STEP   (0x00000004u)
#define	DEBUG_HCSR_C_STEP_MASK   (0x00000004u)
#define	DEBUG_HCSR_C_STEP_BIT   (2)
#define	DEBUG_HCSR_C_STEP_BITS   (1)
#define	DEBUG_HCSR_C_HALT   (0x00000002u)
#define	DEBUG_HCSR_C_HALT_MASK   (0x00000002u)
#define	DEBUG_HCSR_C_HALT_BIT   (1)
#define	DEBUG_HCSR_C_HALT_BITS   (1)
#define	DEBUG_HCSR_C_DEBUGEN   (0x00000001u)
#define	DEBUG_HCSR_C_DEBUGEN_MASK   (0x00000001u)
#define	DEBUG_HCSR_C_DEBUGEN_BIT   (0)
#define	DEBUG_HCSR_C_DEBUGEN_BITS   (1)
#define	DEBUG_CRSR   *((volatile int32u *)0xE000EDF4u)
#define	DEBUG_CRSR_REG   *((volatile int32u *)0xE000EDF4u)
#define	DEBUG_CRSR_ADDR   (0xE000EDF4u)
#define	DEBUG_CRSR_RESET   (0x00000000u)
#define	DEBUG_CRSR_REGWnR   (0x00010000u)
#define	DEBUG_CRSR_REGWnR_MASK   (0x00010000u)
#define	DEBUG_CRSR_REGWnR_BIT   (16)
#define	DEBUG_CRSR_REGWnR_BITS   (1)
#define	DEBUG_CRSR_REGSEL   (0x0000001Fu)
#define	DEBUG_CRSR_REGSEL_MASK   (0x0000001Fu)
#define	DEBUG_CRSR_REGSEL_BIT   (0)
#define	DEBUG_CRSR_REGSEL_BITS   (5)
#define	DEBUG_CRDR   *((volatile int32u *)0xE000EDF8u)
#define	DEBUG_CRDR_REG   *((volatile int32u *)0xE000EDF8u)
#define	DEBUG_CRDR_ADDR   (0xE000EDF8u)
#define	DEBUG_CRDR_RESET   (0x00000000u)
#define	DEBUG_CRDR_DBGTMP   (0xFFFFFFFFu)
#define	DEBUG_CRDR_DBGTMP_MASK   (0xFFFFFFFFu)
#define	DEBUG_CRDR_DBGTMP_BIT   (0)
#define	DEBUG_CRDR_DBGTMP_BITS   (32)
#define	DEBUG_EMCR   *((volatile int32u *)0xE000EDFCu)
#define	DEBUG_EMCR_REG   *((volatile int32u *)0xE000EDFCu)
#define	DEBUG_EMCR_ADDR   (0xE000EDFCu)
#define	DEBUG_EMCR_RESET   (0x00000000u)
#define	DEBUG_EMCR_TRCENA   (0x01000000u)
#define	DEBUG_EMCR_TRCENA_MASK   (0x01000000u)
#define	DEBUG_EMCR_TRCENA_BIT   (24)
#define	DEBUG_EMCR_TRCENA_BITS   (1)
#define	DEBUG_EMCR_MON_REQ   (0x00080000u)
#define	DEBUG_EMCR_MON_REQ_MASK   (0x00080000u)
#define	DEBUG_EMCR_MON_REQ_BIT   (19)
#define	DEBUG_EMCR_MON_REQ_BITS   (1)
#define	DEBUG_EMCR_MON_STEP   (0x00040000u)
#define	DEBUG_EMCR_MON_STEP_MASK   (0x00040000u)
#define	DEBUG_EMCR_MON_STEP_BIT   (18)
#define	DEBUG_EMCR_MON_STEP_BITS   (1)
#define	DEBUG_EMCR_MON_PEND   (0x00020000u)
#define	DEBUG_EMCR_MON_PEND_MASK   (0x00020000u)
#define	DEBUG_EMCR_MON_PEND_BIT   (17)
#define	DEBUG_EMCR_MON_PEND_BITS   (1)
#define	DEBUG_EMCR_MON_EN   (0x00010000u)
#define	DEBUG_EMCR_MON_EN_MASK   (0x00010000u)
#define	DEBUG_EMCR_MON_EN_BIT   (16)
#define	DEBUG_EMCR_MON_EN_BITS   (1)
#define	DEBUG_EMCR_VC_HARDERR   (0x00000400u)
#define	DEBUG_EMCR_VC_HARDERR_MASK   (0x00000400u)
#define	DEBUG_EMCR_VC_HARDERR_BIT   (10)
#define	DEBUG_EMCR_VC_HARDERR_BITS   (1)
#define	DEBUG_EMCR_VC_INTERR   (0x00000200u)
#define	DEBUG_EMCR_VC_INTERR_MASK   (0x00000200u)
#define	DEBUG_EMCR_VC_INTERR_BIT   (9)
#define	DEBUG_EMCR_VC_INTERR_BITS   (1)
#define	DEBUG_EMCR_VC_BUSERR   (0x00000100u)
#define	DEBUG_EMCR_VC_BUSERR_MASK   (0x00000100u)
#define	DEBUG_EMCR_VC_BUSERR_BIT   (8)
#define	DEBUG_EMCR_VC_BUSERR_BITS   (1)
#define	DEBUG_EMCR_VC_STATERR   (0x00000080u)
#define	DEBUG_EMCR_VC_STATERR_MASK   (0x00000080u)
#define	DEBUG_EMCR_VC_STATERR_BIT   (7)
#define	DEBUG_EMCR_VC_STATERR_BITS   (1)
#define	DEBUG_EMCR_VC_CHKERR   (0x00000040u)
#define	DEBUG_EMCR_VC_CHKERR_MASK   (0x00000040u)
#define	DEBUG_EMCR_VC_CHKERR_BIT   (6)
#define	DEBUG_EMCR_VC_CHKERR_BITS   (1)
#define	DEBUG_EMCR_VC_NOCPERR   (0x00000020u)
#define	DEBUG_EMCR_VC_NOCPERR_MASK   (0x00000020u)
#define	DEBUG_EMCR_VC_NOCPERR_BIT   (5)
#define	DEBUG_EMCR_VC_NOCPERR_BITS   (1)
#define	DEBUG_EMCR_VC_MMERR   (0x00000010u)
#define	DEBUG_EMCR_VC_MMERR_MASK   (0x00000010u)
#define	DEBUG_EMCR_VC_MMERR_BIT   (4)
#define	DEBUG_EMCR_VC_MMERR_BITS   (1)
#define	DEBUG_EMCR_VC_CORERESET   (0x00000001u)
#define	DEBUG_EMCR_VC_CORERESET_MASK   (0x00000001u)
#define	DEBUG_EMCR_VC_CORERESET_BIT   (0)
#define	DEBUG_EMCR_VC_CORERESET_BITS   (1)
#define	NVIC_STIR   *((volatile int32u *)0xE000EF00u)
#define	NVIC_STIR_REG   *((volatile int32u *)0xE000EF00u)
#define	NVIC_STIR_ADDR   (0xE000EF00u)
#define	NVIC_STIR_RESET   (0x00000000u)
#define	NVIC_STIR_INTID   (0x000003FFu)
#define	NVIC_STIR_INTID_MASK   (0x000003FFu)
#define	NVIC_STIR_INTID_BIT   (0)
#define	NVIC_STIR_INTID_BITS   (10)
#define	NVIC_PERIPHID4   *((volatile int32u *)0xE000EFD0u)
#define	NVIC_PERIPHID4_REG   *((volatile int32u *)0xE000EFD0u)
#define	NVIC_PERIPHID4_ADDR   (0xE000EFD0u)
#define	NVIC_PERIPHID4_RESET   (0x00000004u)
#define	NVIC_PERIPHID4_PERIPHID   (0xFFFFFFFFu)
#define	NVIC_PERIPHID4_PERIPHID_MASK   (0xFFFFFFFFu)
#define	NVIC_PERIPHID4_PERIPHID_BIT   (0)
#define	NVIC_PERIPHID4_PERIPHID_BITS   (32)
#define	NVIC_PERIPHID5   *((volatile int32u *)0xE000EFD4u)
#define	NVIC_PERIPHID5_REG   *((volatile int32u *)0xE000EFD4u)
#define	NVIC_PERIPHID5_ADDR   (0xE000EFD4u)
#define	NVIC_PERIPHID5_RESET   (0x00000000u)
#define	NVIC_PERIPHID5_PERIPHID   (0xFFFFFFFFu)
#define	NVIC_PERIPHID5_PERIPHID_MASK   (0xFFFFFFFFu)
#define	NVIC_PERIPHID5_PERIPHID_BIT   (0)
#define	NVIC_PERIPHID5_PERIPHID_BITS   (32)
#define	NVIC_PERIPHID6   *((volatile int32u *)0xE000EFD8u)
#define	NVIC_PERIPHID6_REG   *((volatile int32u *)0xE000EFD8u)
#define	NVIC_PERIPHID6_ADDR   (0xE000EFD8u)
#define	NVIC_PERIPHID6_RESET   (0x00000000u)
#define	NVIC_PERIPHID6_PERIPHID   (0xFFFFFFFFu)
#define	NVIC_PERIPHID6_PERIPHID_MASK   (0xFFFFFFFFu)
#define	NVIC_PERIPHID6_PERIPHID_BIT   (0)
#define	NVIC_PERIPHID6_PERIPHID_BITS   (32)
#define	NVIC_PERIPHID7   *((volatile int32u *)0xE000EFDCu)
#define	NVIC_PERIPHID7_REG   *((volatile int32u *)0xE000EFDCu)
#define	NVIC_PERIPHID7_ADDR   (0xE000EFDCu)
#define	NVIC_PERIPHID7_RESET   (0x00000000u)
#define	NVIC_PERIPHID7_PERIPHID   (0xFFFFFFFFu)
#define	NVIC_PERIPHID7_PERIPHID_MASK   (0xFFFFFFFFu)
#define	NVIC_PERIPHID7_PERIPHID_BIT   (0)
#define	NVIC_PERIPHID7_PERIPHID_BITS   (32)
#define	NVIC_PERIPHID0   *((volatile int32u *)0xE000EFE0u)
#define	NVIC_PERIPHID0_REG   *((volatile int32u *)0xE000EFE0u)
#define	NVIC_PERIPHID0_ADDR   (0xE000EFE0u)
#define	NVIC_PERIPHID0_RESET   (0x00000000u)
#define	NVIC_PERIPHID0_PERIPHID   (0xFFFFFFFFu)
#define	NVIC_PERIPHID0_PERIPHID_MASK   (0xFFFFFFFFu)
#define	NVIC_PERIPHID0_PERIPHID_BIT   (0)
#define	NVIC_PERIPHID0_PERIPHID_BITS   (32)
#define	NVIC_PERIPHID1   *((volatile int32u *)0xE000EFE4u)
#define	NVIC_PERIPHID1_REG   *((volatile int32u *)0xE000EFE4u)
#define	NVIC_PERIPHID1_ADDR   (0xE000EFE4u)
#define	NVIC_PERIPHID1_RESET   (0x000000B0u)
#define	NVIC_PERIPHID1_PERIPHID   (0xFFFFFFFFu)
#define	NVIC_PERIPHID1_PERIPHID_MASK   (0xFFFFFFFFu)
#define	NVIC_PERIPHID1_PERIPHID_BIT   (0)
#define	NVIC_PERIPHID1_PERIPHID_BITS   (32)
#define	NVIC_PERIPHID2   *((volatile int32u *)0xE000EFE8u)
#define	NVIC_PERIPHID2_REG   *((volatile int32u *)0xE000EFE8u)
#define	NVIC_PERIPHID2_ADDR   (0xE000EFE8u)
#define	NVIC_PERIPHID2_RESET   (0x0000001Bu)
#define	NVIC_PERIPHID2_PERIPHID   (0xFFFFFFFFu)
#define	NVIC_PERIPHID2_PERIPHID_MASK   (0xFFFFFFFFu)
#define	NVIC_PERIPHID2_PERIPHID_BIT   (0)
#define	NVIC_PERIPHID2_PERIPHID_BITS   (32)
#define	NVIC_PERIPHID3   *((volatile int32u *)0xE000EFECu)
#define	NVIC_PERIPHID3_REG   *((volatile int32u *)0xE000EFECu)
#define	NVIC_PERIPHID3_ADDR   (0xE000EFECu)
#define	NVIC_PERIPHID3_RESET   (0x00000000u)
#define	NVIC_PERIPHID3_PERIPHID   (0xFFFFFFFFu)
#define	NVIC_PERIPHID3_PERIPHID_MASK   (0xFFFFFFFFu)
#define	NVIC_PERIPHID3_PERIPHID_BIT   (0)
#define	NVIC_PERIPHID3_PERIPHID_BITS   (32)
#define	NVIC_PCELLID0   *((volatile int32u *)0xE000EFF0u)
#define	NVIC_PCELLID0_REG   *((volatile int32u *)0xE000EFF0u)
#define	NVIC_PCELLID0_ADDR   (0xE000EFF0u)
#define	NVIC_PCELLID0_RESET   (0x0000000Du)
#define	NVIC_PCELLID0_PCELLID   (0xFFFFFFFFu)
#define	NVIC_PCELLID0_PCELLID_MASK   (0xFFFFFFFFu)
#define	NVIC_PCELLID0_PCELLID_BIT   (0)
#define	NVIC_PCELLID0_PCELLID_BITS   (32)
#define	NVIC_PCELLID1   *((volatile int32u *)0xE000EFF4u)
#define	NVIC_PCELLID1_REG   *((volatile int32u *)0xE000EFF4u)
#define	NVIC_PCELLID1_ADDR   (0xE000EFF4u)
#define	NVIC_PCELLID1_RESET   (0x000000E0u)
#define	NVIC_PCELLID1_PCELLID   (0xFFFFFFFFu)
#define	NVIC_PCELLID1_PCELLID_MASK   (0xFFFFFFFFu)
#define	NVIC_PCELLID1_PCELLID_BIT   (0)
#define	NVIC_PCELLID1_PCELLID_BITS   (32)
#define	NVIC_PCELLID2   *((volatile int32u *)0xE000EFF8u)
#define	NVIC_PCELLID2_REG   *((volatile int32u *)0xE000EFF8u)
#define	NVIC_PCELLID2_ADDR   (0xE000EFF8u)
#define	NVIC_PCELLID2_RESET   (0x00000005u)
#define	NVIC_PCELLID2_PCELLID   (0xFFFFFFFFu)
#define	NVIC_PCELLID2_PCELLID_MASK   (0xFFFFFFFFu)
#define	NVIC_PCELLID2_PCELLID_BIT   (0)
#define	NVIC_PCELLID2_PCELLID_BITS   (32)
#define	NVIC_PCELLID3   *((volatile int32u *)0xE000EFFCu)
#define	NVIC_PCELLID3_REG   *((volatile int32u *)0xE000EFFCu)
#define	NVIC_PCELLID3_ADDR   (0xE000EFFCu)
#define	NVIC_PCELLID3_RESET   (0x000000B1u)
#define	NVIC_PCELLID3_PCELLID   (0xFFFFFFFFu)
#define	NVIC_PCELLID3_PCELLID_MASK   (0xFFFFFFFFu)
#define	NVIC_PCELLID3_PCELLID_BIT   (0)
#define	NVIC_PCELLID3_PCELLID_BITS   (32)
#define	DATA_TPIU_BASE   (0xE0040000u)
#define	DATA_TPIU_END   (0xE0040EF8u)
#define	DATA_TPIU_SIZE   (DATA_TPIU_END - DATA_TPIU_BASE + 1)
#define	TPIU_SPS   *((volatile int32u *)0xE0040000u)
#define	TPIU_SPS_REG   *((volatile int32u *)0xE0040000u)
#define	TPIU_SPS_ADDR   (0xE0040000u)
#define	TPIU_SPS_RESET   (0x00000000u)
#define	TPIU_SPS_SPS_04   (0x00000008u)
#define	TPIU_SPS_SPS_04_MASK   (0x00000008u)
#define	TPIU_SPS_SPS_04_BIT   (3)
#define	TPIU_SPS_SPS_04_BITS   (1)
#define	TPIU_SPS_SPS_03   (0x00000004u)
#define	TPIU_SPS_SPS_03_MASK   (0x00000004u)
#define	TPIU_SPS_SPS_03_BIT   (2)
#define	TPIU_SPS_SPS_03_BITS   (1)
#define	TPIU_SPS_SPS_02   (0x00000002u)
#define	TPIU_SPS_SPS_02_MASK   (0x00000002u)
#define	TPIU_SPS_SPS_02_BIT   (1)
#define	TPIU_SPS_SPS_02_BITS   (1)
#define	TPIU_SPS_SPS_01   (0x00000001u)
#define	TPIU_SPS_SPS_01_MASK   (0x00000001u)
#define	TPIU_SPS_SPS_01_BIT   (0)
#define	TPIU_SPS_SPS_01_BITS   (1)
#define	TPIU_CPS   *((volatile int32u *)0xE0040004u)
#define	TPIU_CPS_REG   *((volatile int32u *)0xE0040004u)
#define	TPIU_CPS_ADDR   (0xE0040004u)
#define	TPIU_CPS_RESET   (0x00000001u)
#define	TPIU_CPS_CPS_04   (0x00000008u)
#define	TPIU_CPS_CPS_04_MASK   (0x00000008u)
#define	TPIU_CPS_CPS_04_BIT   (3)
#define	TPIU_CPS_CPS_04_BITS   (1)
#define	TPIU_CPS_CPS_03   (0x00000004u)
#define	TPIU_CPS_CPS_03_MASK   (0x00000004u)
#define	TPIU_CPS_CPS_03_BIT   (2)
#define	TPIU_CPS_CPS_03_BITS   (1)
#define	TPIU_CPS_CPS_02   (0x00000002u)
#define	TPIU_CPS_CPS_02_MASK   (0x00000002u)
#define	TPIU_CPS_CPS_02_BIT   (1)
#define	TPIU_CPS_CPS_02_BITS   (1)
#define	TPIU_CPS_CPS_01   (0x00000001u)
#define	TPIU_CPS_CPS_01_MASK   (0x00000001u)
#define	TPIU_CPS_CPS_01_BIT   (0)
#define	TPIU_CPS_CPS_01_BITS   (1)
#define	TPIU_COSD   *((volatile int32u *)0xE0040010u)
#define	TPIU_COSD_REG   *((volatile int32u *)0xE0040010u)
#define	TPIU_COSD_ADDR   (0xE0040010u)
#define	TPIU_COSD_RESET   (0x00000000u)
#define	TPIU_COSD_PRESCALER   (0x00001FFFu)
#define	TPIU_COSD_PRESCALER_MASK   (0x00001FFFu)
#define	TPIU_COSD_PRESCALER_BIT   (0)
#define	TPIU_COSD_PRESCALER_BITS   (13)
#define	TPIU_SPP   *((volatile int32u *)0xE00400F0u)
#define	TPIU_SPP_REG   *((volatile int32u *)0xE00400F0u)
#define	TPIU_SPP_ADDR   (0xE00400F0u)
#define	TPIU_SPP_RESET   (0x00000001u)
#define	TPIU_SPP_PROTOCOL   (0x00000003u)
#define	TPIU_SPP_PROTOCOL_MASK   (0x00000003u)
#define	TPIU_SPP_PROTOCOL_BIT   (0)
#define	TPIU_SPP_PROTOCOL_BITS   (2)
#define	TPIU_FFS   *((volatile int32u *)0xE0040300u)
#define	TPIU_FFS_REG   *((volatile int32u *)0xE0040300u)
#define	TPIU_FFS_ADDR   (0xE0040300u)
#define	TPIU_FFS_RESET   (0x00000008u)
#define	TPIU_FFS_FTNONSTOP   (0x00000008u)
#define	TPIU_FFS_FTNONSTOP_MASK   (0x00000008u)
#define	TPIU_FFS_FTNONSTOP_BIT   (3)
#define	TPIU_FFS_FTNONSTOP_BITS   (1)
#define	TPIU_FFS_TCPRESENT   (0x00000004u)
#define	TPIU_FFS_TCPRESENT_MASK   (0x00000004u)
#define	TPIU_FFS_TCPRESENT_BIT   (2)
#define	TPIU_FFS_TCPRESENT_BITS   (1)
#define	TPIU_FFS_FTSTOPPED   (0x00000002u)
#define	TPIU_FFS_FTSTOPPED_MASK   (0x00000002u)
#define	TPIU_FFS_FTSTOPPED_BIT   (1)
#define	TPIU_FFS_FTSTOPPED_BITS   (1)
#define	TPIU_FFS_FLINPROG   (0x00000001u)
#define	TPIU_FFS_FLINPROG_MASK   (0x00000001u)
#define	TPIU_FFS_FLINPROG_BIT   (0)
#define	TPIU_FFS_FLINPROG_BITS   (1)
#define	TPIU_FFC   *((volatile int32u *)0xE0040304u)
#define	TPIU_FFC_REG   *((volatile int32u *)0xE0040304u)
#define	TPIU_FFC_ADDR   (0xE0040304u)
#define	TPIU_FFC_RESET   (0x00000102u)
#define	TPIU_FFC_TRIGIN   (0x00000100u)
#define	TPIU_FFC_TRIGIN_MASK   (0x00000100u)
#define	TPIU_FFC_TRIGIN_BIT   (8)
#define	TPIU_FFC_TRIGIN_BITS   (1)
#define	TPIU_FFC_ENFCONT   (0x00000002u)
#define	TPIU_FFC_ENFCONT_MASK   (0x00000002u)
#define	TPIU_FFC_ENFCONT_BIT   (1)
#define	TPIU_FFC_ENFCONT_BITS   (1)
#define	TPIU_FSC   *((volatile int32u *)0xE0040308u)
#define	TPIU_FSC_REG   *((volatile int32u *)0xE0040308u)
#define	TPIU_FSC_ADDR   (0xE0040308u)
#define	TPIU_FSC_RESET   (0x00000000u)
#define	TPIU_FSC_FSC   (0xFFFFFFFFu)
#define	TPIU_FSC_FSC_MASK   (0xFFFFFFFFu)
#define	TPIU_FSC_FSC_BIT   (0)
#define	TPIU_FSC_FSC_BITS   (32)
#define	TPIU_ITATBCTR2   *((volatile int32u *)0xE0040EF0u)
#define	TPIU_ITATBCTR2_REG   *((volatile int32u *)0xE0040EF0u)
#define	TPIU_ITATBCTR2_ADDR   (0xE0040EF0u)
#define	TPIU_ITATBCTR2_RESET   (0x00000000u)
#define	TPIU_ITATBCTR2_ATREADY1   (0x00000001u)
#define	TPIU_ITATBCTR2_ATREADY1_MASK   (0x00000001u)
#define	TPIU_ITATBCTR2_ATREADY1_BIT   (0)
#define	TPIU_ITATBCTR2_ATREADY1_BITS   (1)
#define	TPIU_ITATBCTR0   *((volatile int32u *)0xE0040EF8u)
#define	TPIU_ITATBCTR0_REG   *((volatile int32u *)0xE0040EF8u)
#define	TPIU_ITATBCTR0_ADDR   (0xE0040EF8u)
#define	TPIU_ITATBCTR0_RESET   (0x00000000u)
#define	TPIU_ITATBCTR0_ATREADY1   (0x00000001u)
#define	TPIU_ITATBCTR0_ATREADY1_MASK   (0x00000001u)
#define	TPIU_ITATBCTR0_ATREADY1_BIT   (0)
#define	TPIU_ITATBCTR0_ATREADY1_BITS   (1)
#define	DATA_ETM_BASE   (0xE0041000u)
#define	DATA_ETM_END   (0xE0041FFFu)
#define	DATA_ETM_SIZE   (DATA_ETM_END - DATA_ETM_BASE + 1)
#define	DATA_ROM_TAB_BASE   (0xE00FF000u)
#define	DATA_ROM_TAB_END   (0xE00FFFFFu)
#define	DATA_ROM_TAB_SIZE   (DATA_ROM_TAB_END - DATA_ROM_TAB_BASE + 1)
#define	ROM_SCS   *((volatile int32u *)0xE00FF000u)
#define	ROM_SCS_REG   *((volatile int32u *)0xE00FF000u)
#define	ROM_SCS_ADDR   (0xE00FF000u)
#define	ROM_SCS_RESET   (0xFFF0F003u)
#define	ROM_SCS_ADDR_OFF   (0xFFFFF000u)
#define	ROM_SCS_ADDR_OFF_MASK   (0xFFFFF000u)
#define	ROM_SCS_ADDR_OFF_BIT   (12)
#define	ROM_SCS_ADDR_OFF_BITS   (20)
#define	ROM_SCS_FORMAT   (0x00000002u)
#define	ROM_SCS_FORMAT_MASK   (0x00000002u)
#define	ROM_SCS_FORMAT_BIT   (1)
#define	ROM_SCS_FORMAT_BITS   (1)
#define	ROM_SCS_ENTRY_PRES   (0x00000001u)
#define	ROM_SCS_ENTRY_PRES_MASK   (0x00000001u)
#define	ROM_SCS_ENTRY_PRES_BIT   (0)
#define	ROM_SCS_ENTRY_PRES_BITS   (1)
#define	ROM_DWT   *((volatile int32u *)0xE00FF004u)
#define	ROM_DWT_REG   *((volatile int32u *)0xE00FF004u)
#define	ROM_DWT_ADDR   (0xE00FF004u)
#define	ROM_DWT_RESET   (0xFFF02003u)
#define	ROM_DWT_ADDR_OFF   (0xFFFFF000u)
#define	ROM_DWT_ADDR_OFF_MASK   (0xFFFFF000u)
#define	ROM_DWT_ADDR_OFF_BIT   (12)
#define	ROM_DWT_ADDR_OFF_BITS   (20)
#define	ROM_DWT_FORMAT   (0x00000002u)
#define	ROM_DWT_FORMAT_MASK   (0x00000002u)
#define	ROM_DWT_FORMAT_BIT   (1)
#define	ROM_DWT_FORMAT_BITS   (1)
#define	ROM_DWT_ENTRY_PRES   (0x00000001u)
#define	ROM_DWT_ENTRY_PRES_MASK   (0x00000001u)
#define	ROM_DWT_ENTRY_PRES_BIT   (0)
#define	ROM_DWT_ENTRY_PRES_BITS   (1)
#define	ROM_FPB   *((volatile int32u *)0xE00FF008u)
#define	ROM_FPB_REG   *((volatile int32u *)0xE00FF008u)
#define	ROM_FPB_ADDR   (0xE00FF008u)
#define	ROM_FPB_RESET   (0xFFF03003u)
#define	ROM_FPB_ADDR_OFF   (0xFFFFF000u)
#define	ROM_FPB_ADDR_OFF_MASK   (0xFFFFF000u)
#define	ROM_FPB_ADDR_OFF_BIT   (12)
#define	ROM_FPB_ADDR_OFF_BITS   (20)
#define	ROM_FPB_FORMAT   (0x00000002u)
#define	ROM_FPB_FORMAT_MASK   (0x00000002u)
#define	ROM_FPB_FORMAT_BIT   (1)
#define	ROM_FPB_FORMAT_BITS   (1)
#define	ROM_FPB_ENTRY_PRES   (0x00000001u)
#define	ROM_FPB_ENTRY_PRES_MASK   (0x00000001u)
#define	ROM_FPB_ENTRY_PRES_BIT   (0)
#define	ROM_FPB_ENTRY_PRES_BITS   (1)
#define	ROM_ITM   *((volatile int32u *)0xE00FF00Cu)
#define	ROM_ITM_REG   *((volatile int32u *)0xE00FF00Cu)
#define	ROM_ITM_ADDR   (0xE00FF00Cu)
#define	ROM_ITM_RESET   (0xFFF01003u)
#define	ROM_ITM_ADDR_OFF   (0xFFFFF000u)
#define	ROM_ITM_ADDR_OFF_MASK   (0xFFFFF000u)
#define	ROM_ITM_ADDR_OFF_BIT   (12)
#define	ROM_ITM_ADDR_OFF_BITS   (20)
#define	ROM_ITM_FORMAT   (0x00000002u)
#define	ROM_ITM_FORMAT_MASK   (0x00000002u)
#define	ROM_ITM_FORMAT_BIT   (1)
#define	ROM_ITM_FORMAT_BITS   (1)
#define	ROM_ITM_ENTRY_PRES   (0x00000001u)
#define	ROM_ITM_ENTRY_PRES_MASK   (0x00000001u)
#define	ROM_ITM_ENTRY_PRES_BIT   (0)
#define	ROM_ITM_ENTRY_PRES_BITS   (1)
#define	ROM_TPIU   *((volatile int32u *)0xE00FF010u)
#define	ROM_TPIU_REG   *((volatile int32u *)0xE00FF010u)
#define	ROM_TPIU_ADDR   (0xE00FF010u)
#define	ROM_TPIU_RESET   (0xFFF0F003u)
#define	ROM_TPIU_ADDR_OFF   (0xFFFFF000u)
#define	ROM_TPIU_ADDR_OFF_MASK   (0xFFFFF000u)
#define	ROM_TPIU_ADDR_OFF_BIT   (12)
#define	ROM_TPIU_ADDR_OFF_BITS   (20)
#define	ROM_TPIU_FORMAT   (0x00000002u)
#define	ROM_TPIU_FORMAT_MASK   (0x00000002u)
#define	ROM_TPIU_FORMAT_BIT   (1)
#define	ROM_TPIU_FORMAT_BITS   (1)
#define	ROM_TPIU_ENTRY_PRES   (0x00000001u)
#define	ROM_TPIU_ENTRY_PRES_MASK   (0x00000001u)
#define	ROM_TPIU_ENTRY_PRES_BIT   (0)
#define	ROM_TPIU_ENTRY_PRES_BITS   (1)
#define	ROM_ETM   *((volatile int32u *)0xE00FF014u)
#define	ROM_ETM_REG   *((volatile int32u *)0xE00FF014u)
#define	ROM_ETM_ADDR   (0xE00FF014u)
#define	ROM_ETM_RESET   (0xFFF0F002u)
#define	ROM_ETM_ADDR_OFF   (0xFFFFF000u)
#define	ROM_ETM_ADDR_OFF_MASK   (0xFFFFF000u)
#define	ROM_ETM_ADDR_OFF_BIT   (12)
#define	ROM_ETM_ADDR_OFF_BITS   (20)
#define	ROM_ETM_FORMAT   (0x00000002u)
#define	ROM_ETM_FORMAT_MASK   (0x00000002u)
#define	ROM_ETM_FORMAT_BIT   (1)
#define	ROM_ETM_FORMAT_BITS   (1)
#define	ROM_ETM_ENTRY_PRES   (0x00000001u)
#define	ROM_ETM_ENTRY_PRES_MASK   (0x00000001u)
#define	ROM_ETM_ENTRY_PRES_BIT   (0)
#define	ROM_ETM_ENTRY_PRES_BITS   (1)
#define	ROM_END   *((volatile int32u *)0xE00FF018u)
#define	ROM_END_REG   *((volatile int32u *)0xE00FF018u)
#define	ROM_END_ADDR   (0xE00FF018u)
#define	ROM_END_RESET   (0x00000000u)
#define	ROM_END_END   (0xFFFFFFFFu)
#define	ROM_END_END_MASK   (0xFFFFFFFFu)
#define	ROM_END_END_BIT   (0)
#define	ROM_END_END_BITS   (32)
#define	ROM_MEMTYPE   *((volatile int32u *)0xE00FFFCCu)
#define	ROM_MEMTYPE_REG   *((volatile int32u *)0xE00FFFCCu)
#define	ROM_MEMTYPE_ADDR   (0xE00FFFCCu)
#define	ROM_MEMTYPE_RESET   (0x00000001u)
#define	ROM_MEMTYPE_MEMTYPE   (0x00000001u)
#define	ROM_MEMTYPE_MEMTYPE_MASK   (0x00000001u)
#define	ROM_MEMTYPE_MEMTYPE_BIT   (0)
#define	ROM_MEMTYPE_MEMTYPE_BITS   (1)
#define	ROM_PID4   *((volatile int32u *)0xE00FFFD0u)
#define	ROM_PID4_REG   *((volatile int32u *)0xE00FFFD0u)
#define	ROM_PID4_ADDR   (0xE00FFFD0u)
#define	ROM_PID4_RESET   (0x00000000u)
#define	ROM_PID4_PID   (0x0000000Fu)
#define	ROM_PID4_PID_MASK   (0x0000000Fu)
#define	ROM_PID4_PID_BIT   (0)
#define	ROM_PID4_PID_BITS   (4)
#define	ROM_PID5   *((volatile int32u *)0xE00FFFD4u)
#define	ROM_PID5_REG   *((volatile int32u *)0xE00FFFD4u)
#define	ROM_PID5_ADDR   (0xE00FFFD4u)
#define	ROM_PID5_RESET   (0x00000000u)
#define	ROM_PID5_PID   (0x0000000Fu)
#define	ROM_PID5_PID_MASK   (0x0000000Fu)
#define	ROM_PID5_PID_BIT   (0)
#define	ROM_PID5_PID_BITS   (4)
#define	ROM_PID6   *((volatile int32u *)0xE00FFFD8u)
#define	ROM_PID6_REG   *((volatile int32u *)0xE00FFFD8u)
#define	ROM_PID6_ADDR   (0xE00FFFD8u)
#define	ROM_PID6_RESET   (0x00000000u)
#define	ROM_PID6_PID   (0x0000000Fu)
#define	ROM_PID6_PID_MASK   (0x0000000Fu)
#define	ROM_PID6_PID_BIT   (0)
#define	ROM_PID6_PID_BITS   (4)
#define	ROM_PID7   *((volatile int32u *)0xE00FFFDCu)
#define	ROM_PID7_REG   *((volatile int32u *)0xE00FFFDCu)
#define	ROM_PID7_ADDR   (0xE00FFFDCu)
#define	ROM_PID7_RESET   (0x00000000u)
#define	ROM_PID7_PID   (0x0000000Fu)
#define	ROM_PID7_PID_MASK   (0x0000000Fu)
#define	ROM_PID7_PID_BIT   (0)
#define	ROM_PID7_PID_BITS   (4)
#define	ROM_PID0   *((volatile int32u *)0xE00FFFE0u)
#define	ROM_PID0_REG   *((volatile int32u *)0xE00FFFE0u)
#define	ROM_PID0_ADDR   (0xE00FFFE0u)
#define	ROM_PID0_RESET   (0x00000000u)
#define	ROM_PID0_PID   (0x0000000Fu)
#define	ROM_PID0_PID_MASK   (0x0000000Fu)
#define	ROM_PID0_PID_BIT   (0)
#define	ROM_PID0_PID_BITS   (4)
#define	ROM_PID1   *((volatile int32u *)0xE00FFFE4u)
#define	ROM_PID1_REG   *((volatile int32u *)0xE00FFFE4u)
#define	ROM_PID1_ADDR   (0xE00FFFE4u)
#define	ROM_PID1_RESET   (0x00000000u)
#define	ROM_PID1_PID   (0x0000000Fu)
#define	ROM_PID1_PID_MASK   (0x0000000Fu)
#define	ROM_PID1_PID_BIT   (0)
#define	ROM_PID1_PID_BITS   (4)
#define	ROM_PID2   *((volatile int32u *)0xE00FFFE8u)
#define	ROM_PID2_REG   *((volatile int32u *)0xE00FFFE8u)
#define	ROM_PID2_ADDR   (0xE00FFFE8u)
#define	ROM_PID2_RESET   (0x00000000u)
#define	ROM_PID2_PID   (0x0000000Fu)
#define	ROM_PID2_PID_MASK   (0x0000000Fu)
#define	ROM_PID2_PID_BIT   (0)
#define	ROM_PID2_PID_BITS   (4)
#define	ROM_PID3   *((volatile int32u *)0xE00FFFECu)
#define	ROM_PID3_REG   *((volatile int32u *)0xE00FFFECu)
#define	ROM_PID3_ADDR   (0xE00FFFECu)
#define	ROM_PID3_RESET   (0x00000000u)
#define	ROM_PID3_PID   (0x0000000Fu)
#define	ROM_PID3_PID_MASK   (0x0000000Fu)
#define	ROM_PID3_PID_BIT   (0)
#define	ROM_PID3_PID_BITS   (4)
#define	ROM_CID0   *((volatile int32u *)0xE00FFFF0u)
#define	ROM_CID0_REG   *((volatile int32u *)0xE00FFFF0u)
#define	ROM_CID0_ADDR   (0xE00FFFF0u)
#define	ROM_CID0_RESET   (0x0000000Du)
#define	ROM_CID0_CID   (0x000000FFu)
#define	ROM_CID0_CID_MASK   (0x000000FFu)
#define	ROM_CID0_CID_BIT   (0)
#define	ROM_CID0_CID_BITS   (8)
#define	ROM_CID1   *((volatile int32u *)0xE00FFFF4u)
#define	ROM_CID1_REG   *((volatile int32u *)0xE00FFFF4u)
#define	ROM_CID1_ADDR   (0xE00FFFF4u)
#define	ROM_CID1_RESET   (0x00000010u)
#define	ROM_CID1_CID   (0x000000FFu)
#define	ROM_CID1_CID_MASK   (0x000000FFu)
#define	ROM_CID1_CID_BIT   (0)
#define	ROM_CID1_CID_BITS   (8)
#define	ROM_CID2   *((volatile int32u *)0xE00FFFF8u)
#define	ROM_CID2_REG   *((volatile int32u *)0xE00FFFF8u)
#define	ROM_CID2_ADDR   (0xE00FFFF8u)
#define	ROM_CID2_RESET   (0x00000005u)
#define	ROM_CID2_CID   (0x000000FFu)
#define	ROM_CID2_CID_MASK   (0x000000FFu)
#define	ROM_CID2_CID_BIT   (0)
#define	ROM_CID2_CID_BITS   (8)
#define	ROM_CID3   *((volatile int32u *)0xE00FFFFCu)
#define	ROM_CID3_REG   *((volatile int32u *)0xE00FFFFCu)
#define	ROM_CID3_ADDR   (0xE00FFFFCu)
#define	ROM_CID3_RESET   (0x000000B1u)
#define	ROM_CID3_CID   (0x000000FFu)
#define	ROM_CID3_CID_MASK   (0x000000FFu)
#define	ROM_CID3_CID_BIT   (0)
#define	ROM_CID3_CID_BITS   (8)
#define	DATA_VENDOR_BASE   (0xE0100000u)
#define	DATA_VENDOR_END   (0xFFFFFFFFu)
#define	DATA_VENDOR_SIZE   (DATA_VENDOR_END - DATA_VENDOR_BASE + 1)

---

Define Documentation

#define __REGS_H__   1

Definition at line 2 of file regs.h.

#define ADC_1MHZCLK   (0x00000004u)

Definition at line 6505 of file regs.h.

#define ADC_1MHZCLK_BIT   (2)

Definition at line 6507 of file regs.h.

#define ADC_1MHZCLK_BITS   (1)

Definition at line 6508 of file regs.h.

#define ADC_1MHZCLK_MASK   (0x00000004u)

Definition at line 6506 of file regs.h.

#define ADC_BYPASS_EN   *((volatile int32u *)0x40001030u)

Definition at line 540 of file regs.h.

#define ADC_BYPASS_EN_ADC_BYPASS_EN   (0x00000001u)

Definition at line 545 of file regs.h.

#define ADC_BYPASS_EN_ADC_BYPASS_EN_BIT   (0)

Definition at line 547 of file regs.h.

#define ADC_BYPASS_EN_ADC_BYPASS_EN_BITS   (1)

Definition at line 548 of file regs.h.

#define ADC_BYPASS_EN_ADC_BYPASS_EN_MASK   (0x00000001u)

Definition at line 546 of file regs.h.

#define ADC_BYPASS_EN_ADDR   (0x40001030u)

Definition at line 542 of file regs.h.

#define ADC_BYPASS_EN_REG   *((volatile int32u *)0x40001030u)

Definition at line 541 of file regs.h.

#define ADC_BYPASS_EN_RESET   (0x00000000u)

Definition at line 543 of file regs.h.

#define ADC_CFG   *((volatile int32u *)0x4000D004u)

Definition at line 6475 of file regs.h.

#define ADC_CFG_ADDR   (0x4000D004u)

Definition at line 6477 of file regs.h.

#define ADC_CFG_REG   *((volatile int32u *)0x4000D004u)

Definition at line 6476 of file regs.h.

#define ADC_CFG_RESET   (0x00001800u)

Definition at line 6478 of file regs.h.

#define ADC_CFGRSVD   (0x00000002u)

Definition at line 6510 of file regs.h.

#define ADC_CFGRSVD_BIT   (1)

Definition at line 6512 of file regs.h.

#define ADC_CFGRSVD_BITS   (1)

Definition at line 6513 of file regs.h.

#define ADC_CFGRSVD_MASK   (0x00000002u)

Definition at line 6511 of file regs.h.

#define ADC_DATA   *((volatile int32u *)0x4000D000u)

Definition at line 6465 of file regs.h.

#define ADC_DATA_ADDR   (0x4000D000u)

Definition at line 6467 of file regs.h.

#define ADC_DATA_FIELD   (0x0000FFFFu)

Definition at line 6470 of file regs.h.

#define ADC_DATA_FIELD_BIT   (0)

Definition at line 6472 of file regs.h.

#define ADC_DATA_FIELD_BITS   (16)

Definition at line 6473 of file regs.h.

#define ADC_DATA_FIELD_MASK   (0x0000FFFFu)

Definition at line 6471 of file regs.h.

#define ADC_DATA_REG   *((volatile int32u *)0x4000D000u)

Definition at line 6466 of file regs.h.

#define ADC_DATA_RESET   (0x00000000u)

Definition at line 6468 of file regs.h.

#define ADC_DMAACT   (0x00000001u)

Definition at line 6570 of file regs.h.

#define ADC_DMAACT_BIT   (0)

Definition at line 6572 of file regs.h.

#define ADC_DMAACT_BITS   (1)

Definition at line 6573 of file regs.h.

#define ADC_DMAACT_MASK   (0x00000001u)

Definition at line 6571 of file regs.h.

#define ADC_DMAAUTOWRAP   (0x00000002u)

Definition at line 6550 of file regs.h.

#define ADC_DMAAUTOWRAP_BIT   (1)

Definition at line 6552 of file regs.h.

#define ADC_DMAAUTOWRAP_BITS   (1)

Definition at line 6553 of file regs.h.

#define ADC_DMAAUTOWRAP_MASK   (0x00000002u)

Definition at line 6551 of file regs.h.

#define ADC_DMABEG   *((volatile int32u *)0x4000D018u)

Definition at line 6575 of file regs.h.

#define ADC_DMABEG_ADDR   (0x4000D018u)

Definition at line 6577 of file regs.h.

#define ADC_DMABEG_FIELD   (0x00001FFFu)

Definition at line 6585 of file regs.h.

#define ADC_DMABEG_FIELD_BIT   (0)

Definition at line 6587 of file regs.h.

#define ADC_DMABEG_FIELD_BITS   (13)

Definition at line 6588 of file regs.h.

#define ADC_DMABEG_FIELD_MASK   (0x00001FFFu)

Definition at line 6586 of file regs.h.

#define ADC_DMABEG_FIXED   (0xFFFFE000u)

Definition at line 6580 of file regs.h.

#define ADC_DMABEG_FIXED_BIT   (13)

Definition at line 6582 of file regs.h.

#define ADC_DMABEG_FIXED_BITS   (19)

Definition at line 6583 of file regs.h.

#define ADC_DMABEG_FIXED_MASK   (0xFFFFE000u)

Definition at line 6581 of file regs.h.

#define ADC_DMABEG_REG   *((volatile int32u *)0x4000D018u)

Definition at line 6576 of file regs.h.

#define ADC_DMABEG_RESET   (0x20000000u)

Definition at line 6578 of file regs.h.

#define ADC_DMACFG   *((volatile int32u *)0x4000D010u)

Definition at line 6540 of file regs.h.

#define ADC_DMACFG_ADDR   (0x4000D010u)

Definition at line 6542 of file regs.h.

#define ADC_DMACFG_REG   *((volatile int32u *)0x4000D010u)

Definition at line 6541 of file regs.h.

#define ADC_DMACFG_RESET   (0x00000000u)

Definition at line 6543 of file regs.h.

#define ADC_DMACNT   *((volatile int32u *)0x4000D024u)

Definition at line 6615 of file regs.h.

#define ADC_DMACNT_ADDR   (0x4000D024u)

Definition at line 6617 of file regs.h.

#define ADC_DMACNT_FIELD   (0x00000FFFu)

Definition at line 6620 of file regs.h.

#define ADC_DMACNT_FIELD_BIT   (0)

Definition at line 6622 of file regs.h.

#define ADC_DMACNT_FIELD_BITS   (12)

Definition at line 6623 of file regs.h.

#define ADC_DMACNT_FIELD_MASK   (0x00000FFFu)

Definition at line 6621 of file regs.h.

#define ADC_DMACNT_REG   *((volatile int32u *)0x4000D024u)

Definition at line 6616 of file regs.h.

#define ADC_DMACNT_RESET   (0x00000000u)

Definition at line 6618 of file regs.h.

#define ADC_DMACUR   *((volatile int32u *)0x4000D020u)

Definition at line 6600 of file regs.h.

#define ADC_DMACUR_ADDR   (0x4000D020u)

Definition at line 6602 of file regs.h.

#define ADC_DMACUR_FIELD   (0x00001FFFu)

Definition at line 6610 of file regs.h.

#define ADC_DMACUR_FIELD_BIT   (0)

Definition at line 6612 of file regs.h.

#define ADC_DMACUR_FIELD_BITS   (13)

Definition at line 6613 of file regs.h.

#define ADC_DMACUR_FIELD_MASK   (0x00001FFFu)

Definition at line 6611 of file regs.h.

#define ADC_DMACUR_FIXED   (0xFFFFE000u)

Definition at line 6605 of file regs.h.

#define ADC_DMACUR_FIXED_BIT   (13)

Definition at line 6607 of file regs.h.

#define ADC_DMACUR_FIXED_BITS   (19)

Definition at line 6608 of file regs.h.

#define ADC_DMACUR_FIXED_MASK   (0xFFFFE000u)

Definition at line 6606 of file regs.h.

#define ADC_DMACUR_REG   *((volatile int32u *)0x4000D020u)

Definition at line 6601 of file regs.h.

#define ADC_DMACUR_RESET   (0x20000000u)

Definition at line 6603 of file regs.h.

#define ADC_DMALOAD   (0x00000001u)

Definition at line 6555 of file regs.h.

#define ADC_DMALOAD_BIT   (0)

Definition at line 6557 of file regs.h.

#define ADC_DMALOAD_BITS   (1)

Definition at line 6558 of file regs.h.

#define ADC_DMALOAD_MASK   (0x00000001u)

Definition at line 6556 of file regs.h.

#define ADC_DMAOVF   (0x00000002u)

Definition at line 6565 of file regs.h.

#define ADC_DMAOVF_BIT   (1)

Definition at line 6567 of file regs.h.

#define ADC_DMAOVF_BITS   (1)

Definition at line 6568 of file regs.h.

#define ADC_DMAOVF_MASK   (0x00000002u)

Definition at line 6566 of file regs.h.

#define ADC_DMARST   (0x00000010u)

Definition at line 6545 of file regs.h.

#define ADC_DMARST_BIT   (4)

Definition at line 6547 of file regs.h.

#define ADC_DMARST_BITS   (1)

Definition at line 6548 of file regs.h.

#define ADC_DMARST_MASK   (0x00000010u)

Definition at line 6546 of file regs.h.

#define ADC_DMASIZE   *((volatile int32u *)0x4000D01Cu)

Definition at line 6590 of file regs.h.

#define ADC_DMASIZE_ADDR   (0x4000D01Cu)

Definition at line 6592 of file regs.h.

#define ADC_DMASIZE_FIELD   (0x00000FFFu)

Definition at line 6595 of file regs.h.

#define ADC_DMASIZE_FIELD_BIT   (0)

Definition at line 6597 of file regs.h.

#define ADC_DMASIZE_FIELD_BITS   (12)

Definition at line 6598 of file regs.h.

#define ADC_DMASIZE_FIELD_MASK   (0x00000FFFu)

Definition at line 6596 of file regs.h.

#define ADC_DMASIZE_REG   *((volatile int32u *)0x4000D01Cu)

Definition at line 6591 of file regs.h.

#define ADC_DMASIZE_RESET   (0x00000000u)

Definition at line 6593 of file regs.h.

#define ADC_DMASTAT   *((volatile int32u *)0x4000D014u)

Definition at line 6560 of file regs.h.

#define ADC_DMASTAT_ADDR   (0x4000D014u)

Definition at line 6562 of file regs.h.

#define ADC_DMASTAT_REG   *((volatile int32u *)0x4000D014u)

Definition at line 6561 of file regs.h.

#define ADC_DMASTAT_RESET   (0x00000000u)

Definition at line 6563 of file regs.h.

#define ADC_ENABLE   (0x00000001u)

Definition at line 6515 of file regs.h.

#define ADC_ENABLE_BIT   (0)

Definition at line 6517 of file regs.h.

#define ADC_ENABLE_BITS   (1)

Definition at line 6518 of file regs.h.

#define ADC_ENABLE_MASK   (0x00000001u)

Definition at line 6516 of file regs.h.

#define ADC_GAIN   *((volatile int32u *)0x4000D00Cu)

Definition at line 6530 of file regs.h.

#define ADC_GAIN_ADDR   (0x4000D00Cu)

Definition at line 6532 of file regs.h.

#define ADC_GAIN_FIELD   (0x0000FFFFu)

Definition at line 6535 of file regs.h.

#define ADC_GAIN_FIELD_BIT   (0)

Definition at line 6537 of file regs.h.

#define ADC_GAIN_FIELD_BITS   (16)

Definition at line 6538 of file regs.h.

#define ADC_GAIN_FIELD_MASK   (0x0000FFFFu)

Definition at line 6536 of file regs.h.

#define ADC_GAIN_REG   *((volatile int32u *)0x4000D00Cu)

Definition at line 6531 of file regs.h.

#define ADC_GAIN_RESET   (0x00008000u)

Definition at line 6533 of file regs.h.

#define ADC_HVSELN   (0x00000800u)

Definition at line 6490 of file regs.h.

#define ADC_HVSELN_BIT   (11)

Definition at line 6492 of file regs.h.

#define ADC_HVSELN_BITS   (1)

Definition at line 6493 of file regs.h.

#define ADC_HVSELN_MASK   (0x00000800u)

Definition at line 6491 of file regs.h.

#define ADC_HVSELP   (0x00001000u)

Definition at line 6485 of file regs.h.

#define ADC_HVSELP_BIT   (12)

Definition at line 6487 of file regs.h.

#define ADC_HVSELP_BITS   (1)

Definition at line 6488 of file regs.h.

#define ADC_HVSELP_MASK   (0x00001000u)

Definition at line 6486 of file regs.h.

#define ADC_MUXN   (0x00000078u)

Definition at line 6500 of file regs.h.

#define ADC_MUXN_BIT   (3)

Definition at line 6502 of file regs.h.

#define ADC_MUXN_BITS   (4)

Definition at line 6503 of file regs.h.

#define ADC_MUXN_MASK   (0x00000078u)

Definition at line 6501 of file regs.h.

#define ADC_MUXP   (0x00000780u)

Definition at line 6495 of file regs.h.

#define ADC_MUXP_BIT   (7)

Definition at line 6497 of file regs.h.

#define ADC_MUXP_BITS   (4)

Definition at line 6498 of file regs.h.

#define ADC_MUXP_MASK   (0x00000780u)

Definition at line 6496 of file regs.h.

#define ADC_OFFSET   *((volatile int32u *)0x4000D008u)

Definition at line 6520 of file regs.h.

#define ADC_OFFSET_ADDR   (0x4000D008u)

Definition at line 6522 of file regs.h.

#define ADC_OFFSET_FIELD   (0x0000FFFFu)

Definition at line 6525 of file regs.h.

#define ADC_OFFSET_FIELD_BIT   (0)

Definition at line 6527 of file regs.h.

#define ADC_OFFSET_FIELD_BITS   (16)

Definition at line 6528 of file regs.h.

#define ADC_OFFSET_FIELD_MASK   (0x0000FFFFu)

Definition at line 6526 of file regs.h.

#define ADC_OFFSET_REG   *((volatile int32u *)0x4000D008u)

Definition at line 6521 of file regs.h.

#define ADC_OFFSET_RESET   (0x00000000u)

Definition at line 6523 of file regs.h.

#define ADC_PERIOD   (0x0000E000u)

Definition at line 6480 of file regs.h.

#define ADC_PERIOD_BIT   (13)

Definition at line 6482 of file regs.h.

#define ADC_PERIOD_BITS   (3)

Definition at line 6483 of file regs.h.

#define ADC_PERIOD_MASK   (0x0000E000u)

Definition at line 6481 of file regs.h.

#define AN_CAL_STATUS   *((volatile int32u *)0x40001100u)

Definition at line 1310 of file regs.h.

#define AN_CAL_STATUS_ADDR   (0x40001100u)

Definition at line 1312 of file regs.h.

#define AN_CAL_STATUS_REG   *((volatile int32u *)0x40001100u)

Definition at line 1311 of file regs.h.

#define AN_CAL_STATUS_RESET   (0x00000000u)

Definition at line 1313 of file regs.h.

#define AN_CAL_STATUS_VCO_CTRL   (0x0000000Cu)

Definition at line 1315 of file regs.h.

#define AN_CAL_STATUS_VCO_CTRL_BIT   (2)

Definition at line 1317 of file regs.h.

#define AN_CAL_STATUS_VCO_CTRL_BITS   (2)

Definition at line 1318 of file regs.h.

#define AN_CAL_STATUS_VCO_CTRL_MASK   (0x0000000Cu)

Definition at line 1316 of file regs.h.

#define AN_EN_TEST   *((volatile int32u *)0x4000110Cu)

Definition at line 1350 of file regs.h.

#define AN_EN_TEST_ADC_EN   (0x00002000u)

Definition at line 1365 of file regs.h.

#define AN_EN_TEST_ADC_EN_BIT   (13)

Definition at line 1367 of file regs.h.

#define AN_EN_TEST_ADC_EN_BITS   (1)

Definition at line 1368 of file regs.h.

#define AN_EN_TEST_ADC_EN_MASK   (0x00002000u)

Definition at line 1366 of file regs.h.

#define AN_EN_TEST_ADDR   (0x4000110Cu)

Definition at line 1352 of file regs.h.

#define AN_EN_TEST_AN_TEST_MODE   (0x00008000u)

Definition at line 1355 of file regs.h.

#define AN_EN_TEST_AN_TEST_MODE_BIT   (15)

Definition at line 1357 of file regs.h.

#define AN_EN_TEST_AN_TEST_MODE_BITS   (1)

Definition at line 1358 of file regs.h.

#define AN_EN_TEST_AN_TEST_MODE_MASK   (0x00008000u)

Definition at line 1356 of file regs.h.

#define AN_EN_TEST_BIAS_EN   (0x00000001u)

Definition at line 1420 of file regs.h.

#define AN_EN_TEST_BIAS_EN_BIT   (0)

Definition at line 1422 of file regs.h.

#define AN_EN_TEST_BIAS_EN_BITS   (1)

Definition at line 1423 of file regs.h.

#define AN_EN_TEST_BIAS_EN_MASK   (0x00000001u)

Definition at line 1421 of file regs.h.

#define AN_EN_TEST_CH_FILT_EN   (0x00000080u)

Definition at line 1395 of file regs.h.

#define AN_EN_TEST_CH_FILT_EN_BIT   (7)

Definition at line 1397 of file regs.h.

#define AN_EN_TEST_CH_FILT_EN_BITS   (1)

Definition at line 1398 of file regs.h.

#define AN_EN_TEST_CH_FILT_EN_MASK   (0x00000080u)

Definition at line 1396 of file regs.h.

#define AN_EN_TEST_IF_AMP_EN   (0x00000400u)

Definition at line 1380 of file regs.h.

#define AN_EN_TEST_IF_AMP_EN_BIT   (10)

Definition at line 1382 of file regs.h.

#define AN_EN_TEST_IF_AMP_EN_BITS   (1)

Definition at line 1383 of file regs.h.

#define AN_EN_TEST_IF_AMP_EN_MASK   (0x00000400u)

Definition at line 1381 of file regs.h.

#define AN_EN_TEST_LNA_EN   (0x00000200u)

Definition at line 1385 of file regs.h.

#define AN_EN_TEST_LNA_EN_BIT   (9)

Definition at line 1387 of file regs.h.

#define AN_EN_TEST_LNA_EN_BITS   (1)

Definition at line 1388 of file regs.h.

#define AN_EN_TEST_LNA_EN_MASK   (0x00000200u)

Definition at line 1386 of file regs.h.

#define AN_EN_TEST_MIXER_EN   (0x00000100u)

Definition at line 1390 of file regs.h.

#define AN_EN_TEST_MIXER_EN_BIT   (8)

Definition at line 1392 of file regs.h.

#define AN_EN_TEST_MIXER_EN_BITS   (1)

Definition at line 1393 of file regs.h.

#define AN_EN_TEST_MIXER_EN_MASK   (0x00000100u)

Definition at line 1391 of file regs.h.

#define AN_EN_TEST_MOD_DAC_EN   (0x00000040u)

Definition at line 1400 of file regs.h.

#define AN_EN_TEST_MOD_DAC_EN_BIT   (6)

Definition at line 1402 of file regs.h.

#define AN_EN_TEST_MOD_DAC_EN_BITS   (1)

Definition at line 1403 of file regs.h.

#define AN_EN_TEST_MOD_DAC_EN_MASK   (0x00000040u)

Definition at line 1401 of file regs.h.

#define AN_EN_TEST_PA_EN   (0x00000010u)

Definition at line 1405 of file regs.h.

#define AN_EN_TEST_PA_EN_BIT   (4)

Definition at line 1407 of file regs.h.

#define AN_EN_TEST_PA_EN_BITS   (1)

Definition at line 1408 of file regs.h.

#define AN_EN_TEST_PA_EN_MASK   (0x00000010u)

Definition at line 1406 of file regs.h.

#define AN_EN_TEST_PFD_EN   (0x00004000u)

Definition at line 1360 of file regs.h.

#define AN_EN_TEST_PFD_EN_BIT   (14)

Definition at line 1362 of file regs.h.

#define AN_EN_TEST_PFD_EN_BITS   (1)

Definition at line 1363 of file regs.h.

#define AN_EN_TEST_PFD_EN_MASK   (0x00004000u)

Definition at line 1361 of file regs.h.

#define AN_EN_TEST_PRE_FILT_EN   (0x00000800u)

Definition at line 1375 of file regs.h.

#define AN_EN_TEST_PRE_FILT_EN_BIT   (11)

Definition at line 1377 of file regs.h.

#define AN_EN_TEST_PRE_FILT_EN_BITS   (1)

Definition at line 1378 of file regs.h.

#define AN_EN_TEST_PRE_FILT_EN_MASK   (0x00000800u)

Definition at line 1376 of file regs.h.

#define AN_EN_TEST_PRESCALER_EN   (0x00000008u)

Definition at line 1410 of file regs.h.

#define AN_EN_TEST_PRESCALER_EN_BIT   (3)

Definition at line 1412 of file regs.h.

#define AN_EN_TEST_PRESCALER_EN_BITS   (1)

Definition at line 1413 of file regs.h.

#define AN_EN_TEST_PRESCALER_EN_MASK   (0x00000008u)

Definition at line 1411 of file regs.h.

#define AN_EN_TEST_REG   *((volatile int32u *)0x4000110Cu)

Definition at line 1351 of file regs.h.

#define AN_EN_TEST_RESET   (0x00000000u)

Definition at line 1353 of file regs.h.

#define AN_EN_TEST_UNUSED   (0x00001000u)

Definition at line 1370 of file regs.h.

#define AN_EN_TEST_UNUSED_BIT   (12)

Definition at line 1372 of file regs.h.

#define AN_EN_TEST_UNUSED_BITS   (1)

Definition at line 1373 of file regs.h.

#define AN_EN_TEST_UNUSED_MASK   (0x00001000u)

Definition at line 1371 of file regs.h.

#define AN_EN_TEST_VCO_EN   (0x00000004u)

Definition at line 1415 of file regs.h.

#define AN_EN_TEST_VCO_EN_BIT   (2)

Definition at line 1417 of file regs.h.

#define AN_EN_TEST_VCO_EN_BITS   (1)

Definition at line 1418 of file regs.h.

#define AN_EN_TEST_VCO_EN_MASK   (0x00000004u)

Definition at line 1416 of file regs.h.

#define ATEST_SEL   *((volatile int32u *)0x40001108u)

Definition at line 1335 of file regs.h.

#define ATEST_SEL_ADDR   (0x40001108u)

Definition at line 1337 of file regs.h.

#define ATEST_SEL_ATEST_CTRL   (0x0000FF00u)

Definition at line 1340 of file regs.h.

#define ATEST_SEL_ATEST_CTRL_BIT   (8)

Definition at line 1342 of file regs.h.

#define ATEST_SEL_ATEST_CTRL_BITS   (8)

Definition at line 1343 of file regs.h.

#define ATEST_SEL_ATEST_CTRL_MASK   (0x0000FF00u)

Definition at line 1341 of file regs.h.

#define ATEST_SEL_ATEST_SEL   (0x0000001Fu)

Definition at line 1345 of file regs.h.

#define ATEST_SEL_ATEST_SEL_BIT   (0)

Definition at line 1347 of file regs.h.

#define ATEST_SEL_ATEST_SEL_BITS   (5)

Definition at line 1348 of file regs.h.

#define ATEST_SEL_ATEST_SEL_MASK   (0x0000001Fu)

Definition at line 1346 of file regs.h.

#define ATEST_SEL_REG   *((volatile int32u *)0x40001108u)

Definition at line 1336 of file regs.h.

#define ATEST_SEL_RESET   (0x00000000u)

Definition at line 1338 of file regs.h.

#define BB_DEBUG   *((volatile int32u *)0x4000101Cu)

Definition at line 470 of file regs.h.

#define BB_DEBUG_ADDR   (0x4000101Cu)

Definition at line 472 of file regs.h.

#define BB_DEBUG_BB_DEBUG_SEL   (0x00000003u)

Definition at line 485 of file regs.h.

#define BB_DEBUG_BB_DEBUG_SEL_BIT   (0)

Definition at line 487 of file regs.h.

#define BB_DEBUG_BB_DEBUG_SEL_BITS   (2)

Definition at line 488 of file regs.h.

#define BB_DEBUG_BB_DEBUG_SEL_MASK   (0x00000003u)

Definition at line 486 of file regs.h.

#define BB_DEBUG_DEBUG_MUX_ADDR   (0x000000F0u)

Definition at line 480 of file regs.h.

#define BB_DEBUG_DEBUG_MUX_ADDR_BIT   (4)

Definition at line 482 of file regs.h.

#define BB_DEBUG_DEBUG_MUX_ADDR_BITS   (4)

Definition at line 483 of file regs.h.

#define BB_DEBUG_DEBUG_MUX_ADDR_MASK   (0x000000F0u)

Definition at line 481 of file regs.h.

#define BB_DEBUG_REG   *((volatile int32u *)0x4000101Cu)

Definition at line 471 of file regs.h.

#define BB_DEBUG_RESET   (0x00000002u)

Definition at line 473 of file regs.h.

#define BB_DEBUG_SYNC_REG_EN   (0x00008000u)

Definition at line 475 of file regs.h.

#define BB_DEBUG_SYNC_REG_EN_BIT   (15)

Definition at line 477 of file regs.h.

#define BB_DEBUG_SYNC_REG_EN_BITS   (1)

Definition at line 478 of file regs.h.

#define BB_DEBUG_SYNC_REG_EN_MASK   (0x00008000u)

Definition at line 476 of file regs.h.

#define BB_DEBUG_VIEW   *((volatile int32u *)0x40001020u)

Definition at line 490 of file regs.h.

#define BB_DEBUG_VIEW_ADDR   (0x40001020u)

Definition at line 492 of file regs.h.

#define BB_DEBUG_VIEW_BB_DEBUG_VIEW   (0x0000FFFFu)

Definition at line 495 of file regs.h.

#define BB_DEBUG_VIEW_BB_DEBUG_VIEW_BIT   (0)

Definition at line 497 of file regs.h.

#define BB_DEBUG_VIEW_BB_DEBUG_VIEW_BITS   (16)

Definition at line 498 of file regs.h.

#define BB_DEBUG_VIEW_BB_DEBUG_VIEW_MASK   (0x0000FFFFu)

Definition at line 496 of file regs.h.

#define BB_DEBUG_VIEW_REG   *((volatile int32u *)0x40001020u)

Definition at line 491 of file regs.h.

#define BB_DEBUG_VIEW_RESET   (0x00000000u)

Definition at line 493 of file regs.h.

#define BB_INT_MASK   *((volatile int32u *)0x4000A04Cu)

Definition at line 3700 of file regs.h.

#define BB_INT_MASK_ADDR   (0x4000A04Cu)

Definition at line 3702 of file regs.h.

#define BB_INT_MASK_BASEBAND_INT_MSK   (0x00000001u)

Definition at line 3710 of file regs.h.

#define BB_INT_MASK_BASEBAND_INT_MSK_BIT   (0)

Definition at line 3712 of file regs.h.

#define BB_INT_MASK_BASEBAND_INT_MSK_BITS   (1)

Definition at line 3713 of file regs.h.

#define BB_INT_MASK_BASEBAND_INT_MSK_MASK   (0x00000001u)

Definition at line 3711 of file regs.h.

#define BB_INT_MASK_REG   *((volatile int32u *)0x4000A04Cu)

Definition at line 3701 of file regs.h.

#define BB_INT_MASK_RESET   (0x00000000u)

Definition at line 3703 of file regs.h.

#define BB_INT_MASK_RSSI_INT_MSK   (0x00000002u)

Definition at line 3705 of file regs.h.

#define BB_INT_MASK_RSSI_INT_MSK_BIT   (1)

Definition at line 3707 of file regs.h.

#define BB_INT_MASK_RSSI_INT_MSK_BITS   (1)

Definition at line 3708 of file regs.h.

#define BB_INT_MASK_RSSI_INT_MSK_MASK   (0x00000002u)

Definition at line 3706 of file regs.h.

#define BB_INT_SRC   *((volatile int32u *)0x4000A00Cu)

Definition at line 3400 of file regs.h.

#define BB_INT_SRC_ADDR   (0x4000A00Cu)

Definition at line 3402 of file regs.h.

#define BB_INT_SRC_BASEBAND_INT_SRC   (0x00000001u)

Definition at line 3410 of file regs.h.

#define BB_INT_SRC_BASEBAND_INT_SRC_BIT   (0)

Definition at line 3412 of file regs.h.

#define BB_INT_SRC_BASEBAND_INT_SRC_BITS   (1)

Definition at line 3413 of file regs.h.

#define BB_INT_SRC_BASEBAND_INT_SRC_MASK   (0x00000001u)

Definition at line 3411 of file regs.h.

#define BB_INT_SRC_REG   *((volatile int32u *)0x4000A00Cu)

Definition at line 3401 of file regs.h.

#define BB_INT_SRC_RESET   (0x00000000u)

Definition at line 3403 of file regs.h.

#define BB_INT_SRC_RSSI_INT_SRC   (0x00000002u)

Definition at line 3405 of file regs.h.

#define BB_INT_SRC_RSSI_INT_SRC_BIT   (1)

Definition at line 3407 of file regs.h.

#define BB_INT_SRC_RSSI_INT_SRC_BITS   (1)

Definition at line 3408 of file regs.h.

#define BB_INT_SRC_RSSI_INT_SRC_MASK   (0x00000002u)

Definition at line 3406 of file regs.h.

#define BIAS_CAL_STATUS   *((volatile int32u *)0x40001104u)

Definition at line 1320 of file regs.h.

#define BIAS_CAL_STATUS_ADDR   (0x40001104u)

Definition at line 1322 of file regs.h.

#define BIAS_CAL_STATUS_ICOMP   (0x00000001u)

Definition at line 1330 of file regs.h.

#define BIAS_CAL_STATUS_ICOMP_BIT   (0)

Definition at line 1332 of file regs.h.

#define BIAS_CAL_STATUS_ICOMP_BITS   (1)

Definition at line 1333 of file regs.h.

#define BIAS_CAL_STATUS_ICOMP_MASK   (0x00000001u)

Definition at line 1331 of file regs.h.

#define BIAS_CAL_STATUS_REG   *((volatile int32u *)0x40001104u)

Definition at line 1321 of file regs.h.

#define BIAS_CAL_STATUS_RESET   (0x00000000u)

Definition at line 1323 of file regs.h.

#define BIAS_CAL_STATUS_VCOMP   (0x00000002u)

Definition at line 1325 of file regs.h.

#define BIAS_CAL_STATUS_VCOMP_BIT   (1)

Definition at line 1327 of file regs.h.

#define BIAS_CAL_STATUS_VCOMP_BITS   (1)

Definition at line 1328 of file regs.h.

#define BIAS_CAL_STATUS_VCOMP_MASK   (0x00000002u)

Definition at line 1326 of file regs.h.

#define BLOCK_ADC_BASE   (0x4000D000u)

Definition at line 6461 of file regs.h.

#define BLOCK_ADC_END   (0x4000D024u)

Definition at line 6462 of file regs.h.

#define BLOCK_ADC_SIZE   (BLOCK_ADC_END - BLOCK_ADC_BASE + 1)

Definition at line 6463 of file regs.h.

#define BLOCK_CM_LV_BASE   (0x40004000u)

Definition at line 2436 of file regs.h.

#define BLOCK_CM_LV_END   (0x40004034u)

Definition at line 2437 of file regs.h.

#define BLOCK_CM_LV_SIZE   (BLOCK_CM_LV_END - BLOCK_CM_LV_BASE + 1)

Definition at line 2438 of file regs.h.

#define BLOCK_GPIO_BASE   (0x4000B000u)

Definition at line 4556 of file regs.h.

#define BLOCK_GPIO_END   (0x4000BC1Cu)

Definition at line 4557 of file regs.h.

#define BLOCK_GPIO_SIZE   (BLOCK_GPIO_END - BLOCK_GPIO_BASE + 1)

Definition at line 4558 of file regs.h.

#define BLOCK_INTERRUPTS_BASE   (0x4000A000u)

Definition at line 3226 of file regs.h.

#define BLOCK_INTERRUPTS_END   (0x4000A86Cu)

Definition at line 3227 of file regs.h.

#define BLOCK_INTERRUPTS_SIZE   (BLOCK_INTERRUPTS_END - BLOCK_INTERRUPTS_BASE + 1)

Definition at line 3228 of file regs.h.

#define BLOCK_NVIC_BASE   (0xE000E000u)

Definition at line 9186 of file regs.h.

#define BLOCK_NVIC_END   (0xE000EFFFu)

Definition at line 9187 of file regs.h.

#define BLOCK_NVIC_SIZE   (BLOCK_NVIC_END - BLOCK_NVIC_BASE + 1)

Definition at line 9188 of file regs.h.

#define BLOCK_SERIAL_BASE   (0x4000C000u)

Definition at line 5497 of file regs.h.

#define BLOCK_SERIAL_END   (0x4000C870u)

Definition at line 5498 of file regs.h.

#define BLOCK_SERIAL_SIZE   (BLOCK_SERIAL_END - BLOCK_SERIAL_BASE + 1)

Definition at line 5499 of file regs.h.

#define BLOCK_TIM1_BASE   (0x4000E000u)

Definition at line 6626 of file regs.h.

#define BLOCK_TIM1_END   (0x4000E050u)

Definition at line 6627 of file regs.h.

#define BLOCK_TIM1_SIZE   (BLOCK_TIM1_END - BLOCK_TIM1_BASE + 1)

Definition at line 6628 of file regs.h.

#define BLOCK_TIM2_BASE   (0x4000F000u)

Definition at line 7136 of file regs.h.

#define BLOCK_TIM2_END   (0x4000F050u)

Definition at line 7137 of file regs.h.

#define BLOCK_TIM2_SIZE   (BLOCK_TIM2_END - BLOCK_TIM2_BASE + 1)

Definition at line 7138 of file regs.h.

#define BUS_FAULT   *((volatile int32u *)0x40004024u)

Definition at line 2565 of file regs.h.

#define BUS_FAULT_ADDR   (0x40004024u)

Definition at line 2567 of file regs.h.

#define BUS_FAULT_MISSED   (0x00000001u)

Definition at line 2585 of file regs.h.

#define BUS_FAULT_MISSED_BIT   (0)

Definition at line 2587 of file regs.h.

#define BUS_FAULT_MISSED_BITS   (1)

Definition at line 2588 of file regs.h.

#define BUS_FAULT_MISSED_MASK   (0x00000001u)

Definition at line 2586 of file regs.h.

#define BUS_FAULT_PROTECTED   (0x00000004u)

Definition at line 2575 of file regs.h.

#define BUS_FAULT_PROTECTED_BIT   (2)

Definition at line 2577 of file regs.h.

#define BUS_FAULT_PROTECTED_BITS   (1)

Definition at line 2578 of file regs.h.

#define BUS_FAULT_PROTECTED_MASK   (0x00000004u)

Definition at line 2576 of file regs.h.

#define BUS_FAULT_REG   *((volatile int32u *)0x40004024u)

Definition at line 2566 of file regs.h.

#define BUS_FAULT_RESERVED   (0x00000002u)

Definition at line 2580 of file regs.h.

#define BUS_FAULT_RESERVED_BIT   (1)

Definition at line 2582 of file regs.h.

#define BUS_FAULT_RESERVED_BITS   (1)

Definition at line 2583 of file regs.h.

#define BUS_FAULT_RESERVED_MASK   (0x00000002u)

Definition at line 2581 of file regs.h.

#define BUS_FAULT_RESET   (0x00000000u)

Definition at line 2568 of file regs.h.

#define BUS_FAULT_WRONGSIZE   (0x00000008u)

Definition at line 2570 of file regs.h.

#define BUS_FAULT_WRONGSIZE_BIT   (3)

Definition at line 2572 of file regs.h.

#define BUS_FAULT_WRONGSIZE_BITS   (1)

Definition at line 2573 of file regs.h.

#define BUS_FAULT_WRONGSIZE_MASK   (0x00000008u)

Definition at line 2571 of file regs.h.

#define CAL_ADC_CONFIG   *((volatile int32u *)0x40007004u)

Definition at line 2905 of file regs.h.

#define CAL_ADC_CONFIG_ADDR   (0x40007004u)

Definition at line 2907 of file regs.h.

#define CAL_ADC_CONFIG_CAL_ADC_CLKSEL   (0x00000004u)

Definition at line 2920 of file regs.h.

#define CAL_ADC_CONFIG_CAL_ADC_CLKSEL_BIT   (2)

Definition at line 2922 of file regs.h.

#define CAL_ADC_CONFIG_CAL_ADC_CLKSEL_BITS   (1)

Definition at line 2923 of file regs.h.

#define CAL_ADC_CONFIG_CAL_ADC_CLKSEL_MASK   (0x00000004u)

Definition at line 2921 of file regs.h.

#define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS   (0x00000002u)

Definition at line 2925 of file regs.h.

#define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS_BIT   (1)

Definition at line 2927 of file regs.h.

#define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS_BITS   (1)

Definition at line 2928 of file regs.h.

#define CAL_ADC_CONFIG_CAL_ADC_DITHER_DIS_MASK   (0x00000002u)

Definition at line 2926 of file regs.h.

#define CAL_ADC_CONFIG_CAL_ADC_EN   (0x00000001u)

Definition at line 2930 of file regs.h.

#define CAL_ADC_CONFIG_CAL_ADC_EN_BIT   (0)

Definition at line 2932 of file regs.h.

#define CAL_ADC_CONFIG_CAL_ADC_EN_BITS   (1)

Definition at line 2933 of file regs.h.

#define CAL_ADC_CONFIG_CAL_ADC_EN_MASK   (0x00000001u)

Definition at line 2931 of file regs.h.

#define CAL_ADC_CONFIG_CAL_ADC_MUX   (0x00000F80u)

Definition at line 2915 of file regs.h.

#define CAL_ADC_CONFIG_CAL_ADC_MUX_BIT   (7)

Definition at line 2917 of file regs.h.

#define CAL_ADC_CONFIG_CAL_ADC_MUX_BITS   (5)

Definition at line 2918 of file regs.h.

#define CAL_ADC_CONFIG_CAL_ADC_MUX_MASK   (0x00000F80u)

Definition at line 2916 of file regs.h.

#define CAL_ADC_CONFIG_CAL_ADC_RATE   (0x00007000u)

Definition at line 2910 of file regs.h.

#define CAL_ADC_CONFIG_CAL_ADC_RATE_BIT   (12)

Definition at line 2912 of file regs.h.

#define CAL_ADC_CONFIG_CAL_ADC_RATE_BITS   (3)

Definition at line 2913 of file regs.h.

#define CAL_ADC_CONFIG_CAL_ADC_RATE_MASK   (0x00007000u)

Definition at line 2911 of file regs.h.

#define CAL_ADC_CONFIG_REG   *((volatile int32u *)0x40007004u)

Definition at line 2906 of file regs.h.

#define CAL_ADC_CONFIG_RESET   (0x00000000u)

Definition at line 2908 of file regs.h.

#define CAL_ADC_DATA   *((volatile int32u *)0x40007000u)

Definition at line 2895 of file regs.h.

#define CAL_ADC_DATA_ADDR   (0x40007000u)

Definition at line 2897 of file regs.h.

#define CAL_ADC_DATA_CAL_ADC_DATA   (0x0000FFFFu)

Definition at line 2900 of file regs.h.

#define CAL_ADC_DATA_CAL_ADC_DATA_BIT   (0)

Definition at line 2902 of file regs.h.

#define CAL_ADC_DATA_CAL_ADC_DATA_BITS   (16)

Definition at line 2903 of file regs.h.

#define CAL_ADC_DATA_CAL_ADC_DATA_MASK   (0x0000FFFFu)

Definition at line 2901 of file regs.h.

#define CAL_ADC_DATA_REG   *((volatile int32u *)0x40007000u)

Definition at line 2896 of file regs.h.

#define CAL_ADC_DATA_RESET   (0x00000000u)

Definition at line 2898 of file regs.h.

#define CARRIER_THRESH   *((volatile int32u *)0x40001050u)

Definition at line 650 of file regs.h.

#define CARRIER_THRESH_ADDR   (0x40001050u)

Definition at line 652 of file regs.h.

#define CARRIER_THRESH_CARRIER_SPIKE_THRESH   (0x0000FF00u)

Definition at line 655 of file regs.h.

#define CARRIER_THRESH_CARRIER_SPIKE_THRESH_BIT   (8)

Definition at line 657 of file regs.h.

#define CARRIER_THRESH_CARRIER_SPIKE_THRESH_BITS   (8)

Definition at line 658 of file regs.h.

#define CARRIER_THRESH_CARRIER_SPIKE_THRESH_MASK   (0x0000FF00u)

Definition at line 656 of file regs.h.

#define CARRIER_THRESH_CARRIER_THRESH   (0x000000FFu)

Definition at line 660 of file regs.h.

#define CARRIER_THRESH_CARRIER_THRESH_BIT   (0)

Definition at line 662 of file regs.h.

#define CARRIER_THRESH_CARRIER_THRESH_BITS   (8)

Definition at line 663 of file regs.h.

#define CARRIER_THRESH_CARRIER_THRESH_MASK   (0x000000FFu)

Definition at line 661 of file regs.h.

#define CARRIER_THRESH_REG   *((volatile int32u *)0x40001050u)

Definition at line 651 of file regs.h.

#define CARRIER_THRESH_RESET   (0x00002332u)

Definition at line 653 of file regs.h.

#define CBC_STATE_0   *((volatile int32u *)0x40003008u)

Definition at line 2335 of file regs.h.

#define CBC_STATE_0_ADDR   (0x40003008u)

Definition at line 2337 of file regs.h.

#define CBC_STATE_0_CBC_STATE   (0xFFFFFFFFu)

Definition at line 2340 of file regs.h.

#define CBC_STATE_0_CBC_STATE_BIT   (0)

Definition at line 2342 of file regs.h.

#define CBC_STATE_0_CBC_STATE_BITS   (32)

Definition at line 2343 of file regs.h.

#define CBC_STATE_0_CBC_STATE_MASK   (0xFFFFFFFFu)

Definition at line 2341 of file regs.h.

#define CBC_STATE_0_REG   *((volatile int32u *)0x40003008u)

Definition at line 2336 of file regs.h.

#define CBC_STATE_0_RESET   (0x00000000u)

Definition at line 2338 of file regs.h.

#define CBC_STATE_1   *((volatile int32u *)0x4000300Cu)

Definition at line 2345 of file regs.h.

#define CBC_STATE_1_ADDR   (0x4000300Cu)

Definition at line 2347 of file regs.h.

#define CBC_STATE_1_CBC_STATE_1   (0xFFFFFFFFu)

Definition at line 2350 of file regs.h.

#define CBC_STATE_1_CBC_STATE_1_BIT   (0)

Definition at line 2352 of file regs.h.

#define CBC_STATE_1_CBC_STATE_1_BITS   (32)

Definition at line 2353 of file regs.h.

#define CBC_STATE_1_CBC_STATE_1_MASK   (0xFFFFFFFFu)

Definition at line 2351 of file regs.h.

#define CBC_STATE_1_REG   *((volatile int32u *)0x4000300Cu)

Definition at line 2346 of file regs.h.

#define CBC_STATE_1_RESET   (0x00000000u)

Definition at line 2348 of file regs.h.

#define CBC_STATE_2   *((volatile int32u *)0x40003010u)

Definition at line 2355 of file regs.h.

#define CBC_STATE_2_ADDR   (0x40003010u)

Definition at line 2357 of file regs.h.

#define CBC_STATE_2_CBC_STATE_2   (0xFFFFFFFFu)

Definition at line 2360 of file regs.h.

#define CBC_STATE_2_CBC_STATE_2_BIT   (0)

Definition at line 2362 of file regs.h.

#define CBC_STATE_2_CBC_STATE_2_BITS   (32)

Definition at line 2363 of file regs.h.

#define CBC_STATE_2_CBC_STATE_2_MASK   (0xFFFFFFFFu)

Definition at line 2361 of file regs.h.

#define CBC_STATE_2_REG   *((volatile int32u *)0x40003010u)

Definition at line 2356 of file regs.h.

#define CBC_STATE_2_RESET   (0x00000000u)

Definition at line 2358 of file regs.h.

#define CBC_STATE_3   *((volatile int32u *)0x40003014u)

Definition at line 2365 of file regs.h.

#define CBC_STATE_3_ADDR   (0x40003014u)

Definition at line 2367 of file regs.h.

#define CBC_STATE_3_CBC_STATE_3   (0xFFFFFFFFu)

Definition at line 2370 of file regs.h.

#define CBC_STATE_3_CBC_STATE_3_BIT   (0)

Definition at line 2372 of file regs.h.

#define CBC_STATE_3_CBC_STATE_3_BITS   (32)

Definition at line 2373 of file regs.h.

#define CBC_STATE_3_CBC_STATE_3_MASK   (0xFFFFFFFFu)

Definition at line 2371 of file regs.h.

#define CBC_STATE_3_REG   *((volatile int32u *)0x40003014u)

Definition at line 2366 of file regs.h.

#define CBC_STATE_3_RESET   (0x00000000u)

Definition at line 2368 of file regs.h.

#define CCA_MODE   *((volatile int32u *)0x400010BCu)

Definition at line 1055 of file regs.h.

#define CCA_MODE_ADDR   (0x400010BCu)

Definition at line 1057 of file regs.h.

#define CCA_MODE_CCA_MODE   (0x00000003u)

Definition at line 1060 of file regs.h.

#define CCA_MODE_CCA_MODE_BIT   (0)

Definition at line 1062 of file regs.h.

#define CCA_MODE_CCA_MODE_BITS   (2)

Definition at line 1063 of file regs.h.

#define CCA_MODE_CCA_MODE_MASK   (0x00000003u)

Definition at line 1061 of file regs.h.

#define CCA_MODE_REG   *((volatile int32u *)0x400010BCu)

Definition at line 1056 of file regs.h.

#define CCA_MODE_RESET   (0x00000000u)

Definition at line 1058 of file regs.h.

#define CLK1K_CAL   *((volatile int32u *)0x40000010u)

Definition at line 85 of file regs.h.

#define CLK1K_CAL_ADDR   (0x40000010u)

Definition at line 87 of file regs.h.

#define CLK1K_CAL_REG   *((volatile int32u *)0x40000010u)

Definition at line 86 of file regs.h.

#define CLK1K_CAL_RESET   (0x00005000u)

Definition at line 88 of file regs.h.

#define CLK1K_FRACTIONAL   (0x000007FFu)

Definition at line 95 of file regs.h.

#define CLK1K_FRACTIONAL_BIT   (0)

Definition at line 97 of file regs.h.

#define CLK1K_FRACTIONAL_BITS   (11)

Definition at line 98 of file regs.h.

#define CLK1K_FRACTIONAL_MASK   (0x000007FFu)

Definition at line 96 of file regs.h.

#define CLK1K_INTEGER   (0x0000F800u)

Definition at line 90 of file regs.h.

#define CLK1K_INTEGER_BIT   (11)

Definition at line 92 of file regs.h.

#define CLK1K_INTEGER_BITS   (5)

Definition at line 93 of file regs.h.

#define CLK1K_INTEGER_MASK   (0x0000F800u)

Definition at line 91 of file regs.h.

#define CLK_PERIOD   *((volatile int32u *)0x40004014u)

Definition at line 2520 of file regs.h.

#define CLK_PERIOD_ADDR   (0x40004014u)

Definition at line 2522 of file regs.h.

#define CLK_PERIOD_FIELD   (0x0000FFFFu)

Definition at line 2525 of file regs.h.

#define CLK_PERIOD_FIELD_BIT   (0)

Definition at line 2527 of file regs.h.

#define CLK_PERIOD_FIELD_BITS   (16)

Definition at line 2528 of file regs.h.

#define CLK_PERIOD_FIELD_MASK   (0x0000FFFFu)

Definition at line 2526 of file regs.h.

#define CLK_PERIOD_REG   *((volatile int32u *)0x40004014u)

Definition at line 2521 of file regs.h.

#define CLK_PERIOD_RESET   (0x00000000u)

Definition at line 2523 of file regs.h.

#define CLK_PERIODMODE   *((volatile int32u *)0x40004010u)

Definition at line 2510 of file regs.h.

#define CLK_PERIODMODE_ADDR   (0x40004010u)

Definition at line 2512 of file regs.h.

#define CLK_PERIODMODE_FIELD   (0x00000003u)

Definition at line 2515 of file regs.h.

#define CLK_PERIODMODE_FIELD_BIT   (0)

Definition at line 2517 of file regs.h.

#define CLK_PERIODMODE_FIELD_BITS   (2)

Definition at line 2518 of file regs.h.

#define CLK_PERIODMODE_FIELD_MASK   (0x00000003u)

Definition at line 2516 of file regs.h.

#define CLK_PERIODMODE_REG   *((volatile int32u *)0x40004010u)

Definition at line 2511 of file regs.h.

#define CLK_PERIODMODE_RESET   (0x00000000u)

Definition at line 2513 of file regs.h.

#define CLKRC_TUNE   *((volatile int32u *)0x4000000Cu)

Definition at line 75 of file regs.h.

#define CLKRC_TUNE_ADDR   (0x4000000Cu)

Definition at line 77 of file regs.h.

#define CLKRC_TUNE_FIELD   (0x0000000Fu)

Definition at line 80 of file regs.h.

#define CLKRC_TUNE_FIELD_BIT   (0)

Definition at line 82 of file regs.h.

#define CLKRC_TUNE_FIELD_BITS   (4)

Definition at line 83 of file regs.h.

#define CLKRC_TUNE_FIELD_MASK   (0x0000000Fu)

Definition at line 81 of file regs.h.

#define CLKRC_TUNE_REG   *((volatile int32u *)0x4000000Cu)

Definition at line 76 of file regs.h.

#define CLKRC_TUNE_RESET   (0x00000000u)

Definition at line 78 of file regs.h.

#define CPU_CLKSEL   *((volatile int32u *)0x40004020u)

Definition at line 2555 of file regs.h.

#define CPU_CLKSEL_ADDR   (0x40004020u)

Definition at line 2557 of file regs.h.

#define CPU_CLKSEL_FIELD   (0x00000001u)

Definition at line 2560 of file regs.h.

#define CPU_CLKSEL_FIELD_BIT   (0)

Definition at line 2562 of file regs.h.

#define CPU_CLKSEL_FIELD_BITS   (1)

Definition at line 2563 of file regs.h.

#define CPU_CLKSEL_FIELD_MASK   (0x00000001u)

Definition at line 2561 of file regs.h.

#define CPU_CLKSEL_REG   *((volatile int32u *)0x40004020u)

Definition at line 2556 of file regs.h.

#define CPU_CLKSEL_RESET   (0x00000000u)

Definition at line 2558 of file regs.h.

#define CPWRUPREQ_STATUS   *((volatile int32u *)0x40000034u)

Definition at line 330 of file regs.h.

#define CPWRUPREQ_STATUS_ADDR   (0x40000034u)

Definition at line 332 of file regs.h.

#define CPWRUPREQ_STATUS_CPWRUPREQ   (0x00000001u)

Definition at line 335 of file regs.h.

#define CPWRUPREQ_STATUS_CPWRUPREQ_BIT   (0)

Definition at line 337 of file regs.h.

#define CPWRUPREQ_STATUS_CPWRUPREQ_BITS   (1)

Definition at line 338 of file regs.h.

#define CPWRUPREQ_STATUS_CPWRUPREQ_MASK   (0x00000001u)

Definition at line 336 of file regs.h.

#define CPWRUPREQ_STATUS_REG   *((volatile int32u *)0x40000034u)

Definition at line 331 of file regs.h.

#define CPWRUPREQ_STATUS_RESET   (0x00000000u)

Definition at line 333 of file regs.h.

#define CSYSPWRUPACK_INHIBIT   *((volatile int32u *)0x40000040u)

Definition at line 360 of file regs.h.

#define CSYSPWRUPACK_INHIBIT_ADDR   (0x40000040u)

Definition at line 362 of file regs.h.

#define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT   (0x00000001u)

Definition at line 365 of file regs.h.

#define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_BIT   (0)

Definition at line 367 of file regs.h.

#define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_BITS   (1)

Definition at line 368 of file regs.h.

#define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_MASK   (0x00000001u)

Definition at line 366 of file regs.h.

#define CSYSPWRUPACK_INHIBIT_REG   *((volatile int32u *)0x40000040u)

Definition at line 361 of file regs.h.

#define CSYSPWRUPACK_INHIBIT_RESET   (0x00000000u)

Definition at line 363 of file regs.h.

#define CSYSPWRUPACK_STATUS   *((volatile int32u *)0x4000003Cu)

Definition at line 350 of file regs.h.

#define CSYSPWRUPACK_STATUS_ADDR   (0x4000003Cu)

Definition at line 352 of file regs.h.

#define CSYSPWRUPACK_STATUS_CSYSPWRUPACK   (0x00000001u)

Definition at line 355 of file regs.h.

#define CSYSPWRUPACK_STATUS_CSYSPWRUPACK_BIT   (0)

Definition at line 357 of file regs.h.

#define CSYSPWRUPACK_STATUS_CSYSPWRUPACK_BITS   (1)

Definition at line 358 of file regs.h.

#define CSYSPWRUPACK_STATUS_CSYSPWRUPACK_MASK   (0x00000001u)

Definition at line 356 of file regs.h.

#define CSYSPWRUPACK_STATUS_REG   *((volatile int32u *)0x4000003Cu)

Definition at line 351 of file regs.h.

#define CSYSPWRUPACK_STATUS_RESET   (0x00000000u)

Definition at line 353 of file regs.h.

#define CSYSPWRUPREQ_STATUS   *((volatile int32u *)0x40000038u)

Definition at line 340 of file regs.h.

#define CSYSPWRUPREQ_STATUS_ADDR   (0x40000038u)

Definition at line 342 of file regs.h.

#define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ   (0x00000001u)

Definition at line 345 of file regs.h.

#define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_BIT   (0)

Definition at line 347 of file regs.h.

#define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_BITS   (1)

Definition at line 348 of file regs.h.

#define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_MASK   (0x00000001u)

Definition at line 346 of file regs.h.

#define CSYSPWRUPREQ_STATUS_REG   *((volatile int32u *)0x40000038u)

Definition at line 341 of file regs.h.

#define CSYSPWRUPREQ_STATUS_RESET   (0x00000000u)

Definition at line 343 of file regs.h.

#define CT   *((volatile int32u *)0x40003030u)

Definition at line 2385 of file regs.h.

#define CT_ADDR   (0x40003030u)

Definition at line 2387 of file regs.h.

#define CT_CT   (0xFFFFFFFFu)

Definition at line 2390 of file regs.h.

#define CT_CT_BIT   (0)

Definition at line 2392 of file regs.h.

#define CT_CT_BITS   (32)

Definition at line 2393 of file regs.h.

#define CT_CT_MASK   (0xFFFFFFFFu)

Definition at line 2391 of file regs.h.

#define CT_REG   *((volatile int32u *)0x40003030u)

Definition at line 2386 of file regs.h.

#define CT_RESET   (0x00000000u)

Definition at line 2388 of file regs.h.

#define DATA_BASEBAND_BASE   (0x40001000u)

Definition at line 381 of file regs.h.

#define DATA_BASEBAND_END   (0x40001114u)

Definition at line 382 of file regs.h.

#define DATA_BASEBAND_SIZE   (DATA_BASEBAND_END - DATA_BASEBAND_BASE + 1)

Definition at line 383 of file regs.h.

#define DATA_BIG_INFO_BASE   (0x08040000u)

Definition at line 21 of file regs.h.

#define DATA_BIG_INFO_BASE_BASE   (0x00000000u)

Definition at line 16 of file regs.h.

#define DATA_BIG_INFO_BASE_END   (0x000007FFu)

Definition at line 17 of file regs.h.

#define DATA_BIG_INFO_BASE_SIZE   (DATA_BIG_INFO_BASE_END - DATA_BIG_INFO_BASE_BASE + 1)

Definition at line 18 of file regs.h.

#define DATA_BIG_INFO_END   (0x080407FFu)

Definition at line 22 of file regs.h.

#define DATA_BIG_INFO_SIZE   (DATA_BIG_INFO_END - DATA_BIG_INFO_BASE + 1)

Definition at line 23 of file regs.h.

#define DATA_CAL_ADC_BASE   (0x40007000u)

Definition at line 2891 of file regs.h.

#define DATA_CAL_ADC_END   (0x40007004u)

Definition at line 2892 of file regs.h.

#define DATA_CAL_ADC_SIZE   (DATA_CAL_ADC_END - DATA_CAL_ADC_BASE + 1)

Definition at line 2893 of file regs.h.

#define DATA_CM_HV_BASE   (0x40000000u)

Definition at line 36 of file regs.h.

#define DATA_CM_HV_END   (0x40000044u)

Definition at line 37 of file regs.h.

#define DATA_CM_HV_SIZE   (DATA_CM_HV_END - DATA_CM_HV_BASE + 1)

Definition at line 38 of file regs.h.

#define DATA_DWT_BASE   (0xE0001000u)

Definition at line 8406 of file regs.h.

#define DATA_DWT_END   (0xE0001FFFu)

Definition at line 8407 of file regs.h.

#define DATA_DWT_SIZE   (DATA_DWT_END - DATA_DWT_BASE + 1)

Definition at line 8408 of file regs.h.

#define DATA_EMU_REGS_BASE   (0x40009000u)

Definition at line 3211 of file regs.h.

#define DATA_EMU_REGS_END   (0x40009000u)

Definition at line 3212 of file regs.h.

#define DATA_EMU_REGS_SIZE   (DATA_EMU_REGS_END - DATA_EMU_REGS_BASE + 1)

Definition at line 3213 of file regs.h.

#define DATA_ETM_BASE   (0xE0041000u)

Definition at line 11266 of file regs.h.

#define DATA_ETM_END   (0xE0041FFFu)

Definition at line 11267 of file regs.h.

#define DATA_ETM_SIZE   (DATA_ETM_END - DATA_ETM_BASE + 1)

Definition at line 11268 of file regs.h.

#define DATA_EXT_DEVICE_BASE   (0xA0000000u)

Definition at line 7671 of file regs.h.

#define DATA_EXT_DEVICE_END   (0xDFFFFFFFu)

Definition at line 7672 of file regs.h.

#define DATA_EXT_DEVICE_SIZE   (DATA_EXT_DEVICE_END - DATA_EXT_DEVICE_BASE + 1)

Definition at line 7673 of file regs.h.

#define DATA_EXT_RAM_BASE   (0x60000000u)

Definition at line 7666 of file regs.h.

#define DATA_EXT_RAM_END   (0x9FFFFFFFu)

Definition at line 7667 of file regs.h.

#define DATA_EXT_RAM_SIZE   (DATA_EXT_RAM_END - DATA_EXT_RAM_BASE + 1)

Definition at line 7668 of file regs.h.

#define DATA_FLASH_BASE   (0x08000000u)

Definition at line 11 of file regs.h.

#define DATA_FLASH_BASE_BASE   (0x00000000u)

Definition at line 6 of file regs.h.

#define DATA_FLASH_BASE_END   (0x0001FFFFu)

Definition at line 7 of file regs.h.

#define DATA_FLASH_BASE_SIZE   (DATA_FLASH_BASE_END - DATA_FLASH_BASE_BASE + 1)

Definition at line 8 of file regs.h.

#define DATA_FLASH_CONTROL_BASE   (0x40008000u)

Definition at line 2936 of file regs.h.

#define DATA_FLASH_CONTROL_END   (0x40008084u)

Definition at line 2937 of file regs.h.

#define DATA_FLASH_CONTROL_SIZE   (DATA_FLASH_CONTROL_END - DATA_FLASH_CONTROL_BASE + 1)

Definition at line 2938 of file regs.h.

#define DATA_FLASH_END   (0x0801FFFFu)

Definition at line 12 of file regs.h.

#define DATA_FLASH_SIZE   (DATA_FLASH_END - DATA_FLASH_BASE + 1)

Definition at line 13 of file regs.h.

#define DATA_FPB_BASE   (0xE0002000u)

Definition at line 8866 of file regs.h.

#define DATA_FPB_END   (0xE0002FFFu)

Definition at line 8867 of file regs.h.

#define DATA_FPB_SIZE   (DATA_FPB_END - DATA_FPB_BASE + 1)

Definition at line 8868 of file regs.h.

#define DATA_ITM_BASE   (0xE0000000u)

Definition at line 7676 of file regs.h.

#define DATA_ITM_END   (0xE0000FFFu)

Definition at line 7677 of file regs.h.

#define DATA_ITM_SIZE   (DATA_ITM_END - DATA_ITM_BASE + 1)

Definition at line 7678 of file regs.h.

#define DATA_MAC_BASE   (0x40002000u)

Definition at line 1451 of file regs.h.

#define DATA_MAC_END   (0x400020C8u)

Definition at line 1452 of file regs.h.

#define DATA_MAC_SIZE   (DATA_MAC_END - DATA_MAC_BASE + 1)

Definition at line 1453 of file regs.h.

#define DATA_RAM_CTRL_BASE   (0x40005000u)

Definition at line 2636 of file regs.h.

#define DATA_RAM_CTRL_END   (0x40005028u)

Definition at line 2637 of file regs.h.

#define DATA_RAM_CTRL_SIZE   (DATA_RAM_CTRL_END - DATA_RAM_CTRL_BASE + 1)

Definition at line 2638 of file regs.h.

#define DATA_ROM_TAB_BASE   (0xE00FF000u)

Definition at line 11271 of file regs.h.

#define DATA_ROM_TAB_END   (0xE00FFFFFu)

Definition at line 11272 of file regs.h.

#define DATA_ROM_TAB_SIZE   (DATA_ROM_TAB_END - DATA_ROM_TAB_BASE + 1)

Definition at line 11273 of file regs.h.

#define DATA_SECURITY_BASE   (0x40003000u)

Definition at line 2276 of file regs.h.

#define DATA_SECURITY_END   (0x40003044u)

Definition at line 2277 of file regs.h.

#define DATA_SECURITY_SIZE   (DATA_SECURITY_END - DATA_SECURITY_BASE + 1)

Definition at line 2278 of file regs.h.

#define DATA_SLOW_TIMERS_BASE   (0x40006000u)

Definition at line 2766 of file regs.h.

#define DATA_SLOW_TIMERS_END   (0x40006024u)

Definition at line 2767 of file regs.h.

#define DATA_SLOW_TIMERS_SIZE   (DATA_SLOW_TIMERS_END - DATA_SLOW_TIMERS_BASE + 1)

Definition at line 2768 of file regs.h.

#define DATA_SMALL_INFO_BASE   (0x08040800u)

Definition at line 26 of file regs.h.

#define DATA_SMALL_INFO_END   (0x080409FFu)

Definition at line 27 of file regs.h.

#define DATA_SMALL_INFO_SIZE   (DATA_SMALL_INFO_END - DATA_SMALL_INFO_BASE + 1)

Definition at line 28 of file regs.h.

#define DATA_SRAM_BASE   (0x20000000u)

Definition at line 31 of file regs.h.

#define DATA_SRAM_END   (0x20001FFFu)

Definition at line 32 of file regs.h.

#define DATA_SRAM_SIZE   (DATA_SRAM_END - DATA_SRAM_BASE + 1)

Definition at line 33 of file regs.h.

#define DATA_TPIU_BASE   (0xE0040000u)

Definition at line 11121 of file regs.h.

#define DATA_TPIU_END   (0xE0040EF8u)

Definition at line 11122 of file regs.h.

#define DATA_TPIU_SIZE   (DATA_TPIU_END - DATA_TPIU_BASE + 1)

Definition at line 11123 of file regs.h.

#define DATA_VENDOR_BASE   (0xE0100000u)

Definition at line 11536 of file regs.h.

#define DATA_VENDOR_END   (0xFFFFFFFFu)

Definition at line 11537 of file regs.h.

#define DATA_VENDOR_SIZE   (DATA_VENDOR_END - DATA_VENDOR_BASE + 1)

Definition at line 11538 of file regs.h.

#define DBG_MBOX   *((volatile int32u *)0x40000030u)

Definition at line 320 of file regs.h.

#define DBG_MBOX_ADDR   (0x40000030u)

Definition at line 322 of file regs.h.

#define DBG_MBOX_DBG_MBOX   (0x0000FFFFu)

Definition at line 325 of file regs.h.

#define DBG_MBOX_DBG_MBOX_BIT   (0)

Definition at line 327 of file regs.h.

#define DBG_MBOX_DBG_MBOX_BITS   (16)

Definition at line 328 of file regs.h.

#define DBG_MBOX_DBG_MBOX_MASK   (0x0000FFFFu)

Definition at line 326 of file regs.h.

#define DBG_MBOX_REG   *((volatile int32u *)0x40000030u)

Definition at line 321 of file regs.h.

#define DBG_MBOX_RESET   (0x00000000u)

Definition at line 323 of file regs.h.

#define DEBUG_BB_MODE   *((volatile int32u *)0x40001018u)

Definition at line 455 of file regs.h.

#define DEBUG_BB_MODE_ADDR   (0x40001018u)

Definition at line 457 of file regs.h.

#define DEBUG_BB_MODE_DEBUG_BB_MODE   (0x00000003u)

Definition at line 465 of file regs.h.

#define DEBUG_BB_MODE_DEBUG_BB_MODE_BIT   (0)

Definition at line 467 of file regs.h.

#define DEBUG_BB_MODE_DEBUG_BB_MODE_BITS   (2)

Definition at line 468 of file regs.h.

#define DEBUG_BB_MODE_DEBUG_BB_MODE_EN   (0x00008000u)

Definition at line 460 of file regs.h.

#define DEBUG_BB_MODE_DEBUG_BB_MODE_EN_BIT   (15)

Definition at line 462 of file regs.h.

#define DEBUG_BB_MODE_DEBUG_BB_MODE_EN_BITS   (1)

Definition at line 463 of file regs.h.

#define DEBUG_BB_MODE_DEBUG_BB_MODE_EN_MASK   (0x00008000u)

Definition at line 461 of file regs.h.

#define DEBUG_BB_MODE_DEBUG_BB_MODE_MASK   (0x00000003u)

Definition at line 466 of file regs.h.

#define DEBUG_BB_MODE_REG   *((volatile int32u *)0x40001018u)

Definition at line 456 of file regs.h.

#define DEBUG_BB_MODE_RESET   (0x00000000u)

Definition at line 458 of file regs.h.

#define DEBUG_CRDR   *((volatile int32u *)0xE000EDF8u)

Definition at line 10910 of file regs.h.

#define DEBUG_CRDR_ADDR   (0xE000EDF8u)

Definition at line 10912 of file regs.h.

#define DEBUG_CRDR_DBGTMP   (0xFFFFFFFFu)

Definition at line 10915 of file regs.h.

#define DEBUG_CRDR_DBGTMP_BIT   (0)

Definition at line 10917 of file regs.h.

#define DEBUG_CRDR_DBGTMP_BITS   (32)

Definition at line 10918 of file regs.h.

#define DEBUG_CRDR_DBGTMP_MASK   (0xFFFFFFFFu)

Definition at line 10916 of file regs.h.

#define DEBUG_CRDR_REG   *((volatile int32u *)0xE000EDF8u)

Definition at line 10911 of file regs.h.

#define DEBUG_CRDR_RESET   (0x00000000u)

Definition at line 10913 of file regs.h.

#define DEBUG_CRSR   *((volatile int32u *)0xE000EDF4u)

Definition at line 10895 of file regs.h.

#define DEBUG_CRSR_ADDR   (0xE000EDF4u)

Definition at line 10897 of file regs.h.

#define DEBUG_CRSR_REG   *((volatile int32u *)0xE000EDF4u)

Definition at line 10896 of file regs.h.

#define DEBUG_CRSR_REGSEL   (0x0000001Fu)

Definition at line 10905 of file regs.h.

#define DEBUG_CRSR_REGSEL_BIT   (0)

Definition at line 10907 of file regs.h.

#define DEBUG_CRSR_REGSEL_BITS   (5)

Definition at line 10908 of file regs.h.

#define DEBUG_CRSR_REGSEL_MASK   (0x0000001Fu)

Definition at line 10906 of file regs.h.

#define DEBUG_CRSR_REGWnR   (0x00010000u)

Definition at line 10900 of file regs.h.

#define DEBUG_CRSR_REGWnR_BIT   (16)

Definition at line 10902 of file regs.h.

#define DEBUG_CRSR_REGWnR_BITS   (1)

Definition at line 10903 of file regs.h.

#define DEBUG_CRSR_REGWnR_MASK   (0x00010000u)

Definition at line 10901 of file regs.h.

#define DEBUG_CRSR_RESET   (0x00000000u)

Definition at line 10898 of file regs.h.

#define DEBUG_EMCR   *((volatile int32u *)0xE000EDFCu)

Definition at line 10920 of file regs.h.

#define DEBUG_EMCR_ADDR   (0xE000EDFCu)

Definition at line 10922 of file regs.h.

#define DEBUG_EMCR_MON_EN   (0x00010000u)

Definition at line 10945 of file regs.h.

#define DEBUG_EMCR_MON_EN_BIT   (16)

Definition at line 10947 of file regs.h.

#define DEBUG_EMCR_MON_EN_BITS   (1)

Definition at line 10948 of file regs.h.

#define DEBUG_EMCR_MON_EN_MASK   (0x00010000u)

Definition at line 10946 of file regs.h.

#define DEBUG_EMCR_MON_PEND   (0x00020000u)

Definition at line 10940 of file regs.h.

#define DEBUG_EMCR_MON_PEND_BIT   (17)

Definition at line 10942 of file regs.h.

#define DEBUG_EMCR_MON_PEND_BITS   (1)

Definition at line 10943 of file regs.h.

#define DEBUG_EMCR_MON_PEND_MASK   (0x00020000u)

Definition at line 10941 of file regs.h.

#define DEBUG_EMCR_MON_REQ   (0x00080000u)

Definition at line 10930 of file regs.h.

#define DEBUG_EMCR_MON_REQ_BIT   (19)

Definition at line 10932 of file regs.h.

#define DEBUG_EMCR_MON_REQ_BITS   (1)

Definition at line 10933 of file regs.h.

#define DEBUG_EMCR_MON_REQ_MASK   (0x00080000u)

Definition at line 10931 of file regs.h.

#define DEBUG_EMCR_MON_STEP   (0x00040000u)

Definition at line 10935 of file regs.h.

#define DEBUG_EMCR_MON_STEP_BIT   (18)

Definition at line 10937 of file regs.h.

#define DEBUG_EMCR_MON_STEP_BITS   (1)

Definition at line 10938 of file regs.h.

#define DEBUG_EMCR_MON_STEP_MASK   (0x00040000u)

Definition at line 10936 of file regs.h.

#define DEBUG_EMCR_REG   *((volatile int32u *)0xE000EDFCu)

Definition at line 10921 of file regs.h.

#define DEBUG_EMCR_RESET   (0x00000000u)

Definition at line 10923 of file regs.h.

#define DEBUG_EMCR_TRCENA   (0x01000000u)

Definition at line 10925 of file regs.h.

#define DEBUG_EMCR_TRCENA_BIT   (24)

Definition at line 10927 of file regs.h.

#define DEBUG_EMCR_TRCENA_BITS   (1)

Definition at line 10928 of file regs.h.

#define DEBUG_EMCR_TRCENA_MASK   (0x01000000u)

Definition at line 10926 of file regs.h.

#define DEBUG_EMCR_VC_BUSERR   (0x00000100u)

Definition at line 10960 of file regs.h.

#define DEBUG_EMCR_VC_BUSERR_BIT   (8)

Definition at line 10962 of file regs.h.

#define DEBUG_EMCR_VC_BUSERR_BITS   (1)

Definition at line 10963 of file regs.h.

#define DEBUG_EMCR_VC_BUSERR_MASK   (0x00000100u)

Definition at line 10961 of file regs.h.

#define DEBUG_EMCR_VC_CHKERR   (0x00000040u)

Definition at line 10970 of file regs.h.

#define DEBUG_EMCR_VC_CHKERR_BIT   (6)

Definition at line 10972 of file regs.h.

#define DEBUG_EMCR_VC_CHKERR_BITS   (1)

Definition at line 10973 of file regs.h.

#define DEBUG_EMCR_VC_CHKERR_MASK   (0x00000040u)

Definition at line 10971 of file regs.h.

#define DEBUG_EMCR_VC_CORERESET   (0x00000001u)

Definition at line 10985 of file regs.h.

#define DEBUG_EMCR_VC_CORERESET_BIT   (0)

Definition at line 10987 of file regs.h.

#define DEBUG_EMCR_VC_CORERESET_BITS   (1)

Definition at line 10988 of file regs.h.

#define DEBUG_EMCR_VC_CORERESET_MASK   (0x00000001u)

Definition at line 10986 of file regs.h.

#define DEBUG_EMCR_VC_HARDERR   (0x00000400u)

Definition at line 10950 of file regs.h.

#define DEBUG_EMCR_VC_HARDERR_BIT   (10)

Definition at line 10952 of file regs.h.

#define DEBUG_EMCR_VC_HARDERR_BITS   (1)

Definition at line 10953 of file regs.h.

#define DEBUG_EMCR_VC_HARDERR_MASK   (0x00000400u)

Definition at line 10951 of file regs.h.

#define DEBUG_EMCR_VC_INTERR   (0x00000200u)

Definition at line 10955 of file regs.h.

#define DEBUG_EMCR_VC_INTERR_BIT   (9)

Definition at line 10957 of file regs.h.

#define DEBUG_EMCR_VC_INTERR_BITS   (1)

Definition at line 10958 of file regs.h.

#define DEBUG_EMCR_VC_INTERR_MASK   (0x00000200u)

Definition at line 10956 of file regs.h.

#define DEBUG_EMCR_VC_MMERR   (0x00000010u)

Definition at line 10980 of file regs.h.

#define DEBUG_EMCR_VC_MMERR_BIT   (4)

Definition at line 10982 of file regs.h.

#define DEBUG_EMCR_VC_MMERR_BITS   (1)

Definition at line 10983 of file regs.h.

#define DEBUG_EMCR_VC_MMERR_MASK   (0x00000010u)

Definition at line 10981 of file regs.h.

#define DEBUG_EMCR_VC_NOCPERR   (0x00000020u)

Definition at line 10975 of file regs.h.

#define DEBUG_EMCR_VC_NOCPERR_BIT   (5)

Definition at line 10977 of file regs.h.

#define DEBUG_EMCR_VC_NOCPERR_BITS   (1)

Definition at line 10978 of file regs.h.

#define DEBUG_EMCR_VC_NOCPERR_MASK   (0x00000020u)

Definition at line 10976 of file regs.h.

#define DEBUG_EMCR_VC_STATERR   (0x00000080u)

Definition at line 10965 of file regs.h.

#define DEBUG_EMCR_VC_STATERR_BIT   (7)

Definition at line 10967 of file regs.h.

#define DEBUG_EMCR_VC_STATERR_BITS   (1)

Definition at line 10968 of file regs.h.

#define DEBUG_EMCR_VC_STATERR_MASK   (0x00000080u)

Definition at line 10966 of file regs.h.

#define DEBUG_HCSR   *((volatile int32u *)0xE000EDF0u)

Definition at line 10830 of file regs.h.

#define DEBUG_HCSR_ADDR   (0xE000EDF0u)

Definition at line 10832 of file regs.h.

#define DEBUG_HCSR_C_DEBUGEN   (0x00000001u)

Definition at line 10890 of file regs.h.

#define DEBUG_HCSR_C_DEBUGEN_BIT   (0)

Definition at line 10892 of file regs.h.

#define DEBUG_HCSR_C_DEBUGEN_BITS   (1)

Definition at line 10893 of file regs.h.

#define DEBUG_HCSR_C_DEBUGEN_MASK   (0x00000001u)

Definition at line 10891 of file regs.h.

#define DEBUG_HCSR_C_HALT   (0x00000002u)

Definition at line 10885 of file regs.h.

#define DEBUG_HCSR_C_HALT_BIT   (1)

Definition at line 10887 of file regs.h.

#define DEBUG_HCSR_C_HALT_BITS   (1)

Definition at line 10888 of file regs.h.

#define DEBUG_HCSR_C_HALT_MASK   (0x00000002u)

Definition at line 10886 of file regs.h.

#define DEBUG_HCSR_C_MASKINTS   (0x00000008u)

Definition at line 10875 of file regs.h.

#define DEBUG_HCSR_C_MASKINTS_BIT   (3)

Definition at line 10877 of file regs.h.

#define DEBUG_HCSR_C_MASKINTS_BITS   (1)

Definition at line 10878 of file regs.h.

#define DEBUG_HCSR_C_MASKINTS_MASK   (0x00000008u)

Definition at line 10876 of file regs.h.

#define DEBUG_HCSR_C_SNAPSTALL   (0x00000020u)

Definition at line 10870 of file regs.h.

#define DEBUG_HCSR_C_SNAPSTALL_BIT   (5)

Definition at line 10872 of file regs.h.

#define DEBUG_HCSR_C_SNAPSTALL_BITS   (1)

Definition at line 10873 of file regs.h.

#define DEBUG_HCSR_C_SNAPSTALL_MASK   (0x00000020u)

Definition at line 10871 of file regs.h.

#define DEBUG_HCSR_C_STEP   (0x00000004u)

Definition at line 10880 of file regs.h.

#define DEBUG_HCSR_C_STEP_BIT   (2)

Definition at line 10882 of file regs.h.

#define DEBUG_HCSR_C_STEP_BITS   (1)

Definition at line 10883 of file regs.h.

#define DEBUG_HCSR_C_STEP_MASK   (0x00000004u)

Definition at line 10881 of file regs.h.

#define DEBUG_HCSR_DBGKEY   (0xFFFF0000u)

Definition at line 10865 of file regs.h.

#define DEBUG_HCSR_DBGKEY_BIT   (16)

Definition at line 10867 of file regs.h.

#define DEBUG_HCSR_DBGKEY_BITS   (16)

Definition at line 10868 of file regs.h.

#define DEBUG_HCSR_DBGKEY_MASK   (0xFFFF0000u)

Definition at line 10866 of file regs.h.

#define DEBUG_HCSR_REG   *((volatile int32u *)0xE000EDF0u)

Definition at line 10831 of file regs.h.

#define DEBUG_HCSR_RESET   (0x00000000u)

Definition at line 10833 of file regs.h.

#define DEBUG_HCSR_S_HALT   (0x00020000u)

Definition at line 10855 of file regs.h.

#define DEBUG_HCSR_S_HALT_BIT   (17)

Definition at line 10857 of file regs.h.

#define DEBUG_HCSR_S_HALT_BITS   (1)

Definition at line 10858 of file regs.h.

#define DEBUG_HCSR_S_HALT_MASK   (0x00020000u)

Definition at line 10856 of file regs.h.

#define DEBUG_HCSR_S_LOCKUP   (0x00080000u)

Definition at line 10845 of file regs.h.

#define DEBUG_HCSR_S_LOCKUP_BIT   (19)

Definition at line 10847 of file regs.h.

#define DEBUG_HCSR_S_LOCKUP_BITS   (1)

Definition at line 10848 of file regs.h.

#define DEBUG_HCSR_S_LOCKUP_MASK   (0x00080000u)

Definition at line 10846 of file regs.h.

#define DEBUG_HCSR_S_REGRDY   (0x00010000u)

Definition at line 10860 of file regs.h.

#define DEBUG_HCSR_S_REGRDY_BIT   (16)

Definition at line 10862 of file regs.h.

#define DEBUG_HCSR_S_REGRDY_BITS   (1)

Definition at line 10863 of file regs.h.

#define DEBUG_HCSR_S_REGRDY_MASK   (0x00010000u)

Definition at line 10861 of file regs.h.

#define DEBUG_HCSR_S_RESET_ST   (0x02000000u)

Definition at line 10835 of file regs.h.

#define DEBUG_HCSR_S_RESET_ST_BIT   (25)

Definition at line 10837 of file regs.h.

#define DEBUG_HCSR_S_RESET_ST_BITS   (1)

Definition at line 10838 of file regs.h.

#define DEBUG_HCSR_S_RESET_ST_MASK   (0x02000000u)

Definition at line 10836 of file regs.h.

#define DEBUG_HCSR_S_RETIRE_ST   (0x01000000u)

Definition at line 10840 of file regs.h.

#define DEBUG_HCSR_S_RETIRE_ST_BIT   (24)

Definition at line 10842 of file regs.h.

#define DEBUG_HCSR_S_RETIRE_ST_BITS   (1)

Definition at line 10843 of file regs.h.

#define DEBUG_HCSR_S_RETIRE_ST_MASK   (0x01000000u)

Definition at line 10841 of file regs.h.

#define DEBUG_HCSR_S_SLEEP   (0x00040000u)

Definition at line 10850 of file regs.h.

#define DEBUG_HCSR_S_SLEEP_BIT   (18)

Definition at line 10852 of file regs.h.

#define DEBUG_HCSR_S_SLEEP_BITS   (1)

Definition at line 10853 of file regs.h.

#define DEBUG_HCSR_S_SLEEP_MASK   (0x00040000u)

Definition at line 10851 of file regs.h.

#define DITHER_AMPLITUDE   *((volatile int32u *)0x40001060u)

Definition at line 700 of file regs.h.

#define DITHER_AMPLITUDE_ADDR   (0x40001060u)

Definition at line 702 of file regs.h.

#define DITHER_AMPLITUDE_DITHER_AMP   (0x0000003Fu)

Definition at line 705 of file regs.h.

#define DITHER_AMPLITUDE_DITHER_AMP_BIT   (0)

Definition at line 707 of file regs.h.

#define DITHER_AMPLITUDE_DITHER_AMP_BITS   (6)

Definition at line 708 of file regs.h.

#define DITHER_AMPLITUDE_DITHER_AMP_MASK   (0x0000003Fu)

Definition at line 706 of file regs.h.

#define DITHER_AMPLITUDE_REG   *((volatile int32u *)0x40001060u)

Definition at line 701 of file regs.h.

#define DITHER_AMPLITUDE_RESET   (0x0000003Fu)

Definition at line 703 of file regs.h.

#define DITHER_DIS   *((volatile int32u *)0x40004018u)

Definition at line 2530 of file regs.h.

#define DITHER_DIS_ADDR   (0x40004018u)

Definition at line 2532 of file regs.h.

#define DITHER_DIS_DITHER_DIS   (0x00000001u)

Definition at line 2535 of file regs.h.

#define DITHER_DIS_DITHER_DIS_BIT   (0)

Definition at line 2537 of file regs.h.

#define DITHER_DIS_DITHER_DIS_BITS   (1)

Definition at line 2538 of file regs.h.

#define DITHER_DIS_DITHER_DIS_MASK   (0x00000001u)

Definition at line 2536 of file regs.h.

#define DITHER_DIS_REG   *((volatile int32u *)0x40004018u)

Definition at line 2531 of file regs.h.

#define DITHER_DIS_RESET   (0x00000000u)

Definition at line 2533 of file regs.h.

#define DMA_PROT_ADDR   *((volatile int32u *)0x40005020u)

Definition at line 2720 of file regs.h.

#define DMA_PROT_ADDR_ADDR   (0x40005020u)

Definition at line 2722 of file regs.h.

#define DMA_PROT_ADDR_DMA_PROT_ADDR   (0x00001FFFu)

Definition at line 2730 of file regs.h.

#define DMA_PROT_ADDR_DMA_PROT_ADDR_BIT   (0)

Definition at line 2732 of file regs.h.

#define DMA_PROT_ADDR_DMA_PROT_ADDR_BITS   (13)

Definition at line 2733 of file regs.h.

#define DMA_PROT_ADDR_DMA_PROT_ADDR_MASK   (0x00001FFFu)

Definition at line 2731 of file regs.h.

#define DMA_PROT_ADDR_DMA_PROT_OFFS   (0xFFFFE000u)

Definition at line 2725 of file regs.h.

#define DMA_PROT_ADDR_DMA_PROT_OFFS_BIT   (13)

Definition at line 2727 of file regs.h.

#define DMA_PROT_ADDR_DMA_PROT_OFFS_BITS   (19)

Definition at line 2728 of file regs.h.

#define DMA_PROT_ADDR_DMA_PROT_OFFS_MASK   (0xFFFFE000u)

Definition at line 2726 of file regs.h.

#define DMA_PROT_ADDR_REG   *((volatile int32u *)0x40005020u)

Definition at line 2721 of file regs.h.

#define DMA_PROT_ADDR_RESET   (0x20000000u)

Definition at line 2723 of file regs.h.

#define DMA_PROT_CH   *((volatile int32u *)0x40005024u)

Definition at line 2735 of file regs.h.

#define DMA_PROT_CH_ADDR   (0x40005024u)

Definition at line 2737 of file regs.h.

#define DMA_PROT_CH_DMA_PROT_CH   (0x00000007u)

Definition at line 2740 of file regs.h.

#define DMA_PROT_CH_DMA_PROT_CH_BIT   (0)

Definition at line 2742 of file regs.h.

#define DMA_PROT_CH_DMA_PROT_CH_BITS   (3)

Definition at line 2743 of file regs.h.

#define DMA_PROT_CH_DMA_PROT_CH_MASK   (0x00000007u)

Definition at line 2741 of file regs.h.

#define DMA_PROT_CH_REG   *((volatile int32u *)0x40005024u)

Definition at line 2736 of file regs.h.

#define DMA_PROT_CH_RESET   (0x00000000u)

Definition at line 2738 of file regs.h.

#define DMA_STATE   *((volatile int32u *)0x400020B4u)

Definition at line 2200 of file regs.h.

#define DMA_STATE_ADDR   (0x400020B4u)

Definition at line 2202 of file regs.h.

#define DMA_STATE_DMA_RX_STATE   (0x00000038u)

Definition at line 2205 of file regs.h.

#define DMA_STATE_DMA_RX_STATE_BIT   (3)

Definition at line 2207 of file regs.h.

#define DMA_STATE_DMA_RX_STATE_BITS   (3)

Definition at line 2208 of file regs.h.

#define DMA_STATE_DMA_RX_STATE_MASK   (0x00000038u)

Definition at line 2206 of file regs.h.

#define DMA_STATE_DMA_TX_STATE   (0x00000007u)

Definition at line 2210 of file regs.h.

#define DMA_STATE_DMA_TX_STATE_BIT   (0)

Definition at line 2212 of file regs.h.

#define DMA_STATE_DMA_TX_STATE_BITS   (3)

Definition at line 2213 of file regs.h.

#define DMA_STATE_DMA_TX_STATE_MASK   (0x00000007u)

Definition at line 2211 of file regs.h.

#define DMA_STATE_REG   *((volatile int32u *)0x400020B4u)

Definition at line 2201 of file regs.h.

#define DMA_STATE_RESET   (0x00000000u)

Definition at line 2203 of file regs.h.

#define DWT_CELLID0   *((volatile int32u *)0xE0001FF0u)

Definition at line 8825 of file regs.h.

#define DWT_CELLID0_ADDR   (0xE0001FF0u)

Definition at line 8827 of file regs.h.

#define DWT_CELLID0_CELLID   (0xFFFFFFFFu)

Definition at line 8830 of file regs.h.

#define DWT_CELLID0_CELLID_BIT   (0)

Definition at line 8832 of file regs.h.

#define DWT_CELLID0_CELLID_BITS   (32)

Definition at line 8833 of file regs.h.

#define DWT_CELLID0_CELLID_MASK   (0xFFFFFFFFu)

Definition at line 8831 of file regs.h.

#define DWT_CELLID0_REG   *((volatile int32u *)0xE0001FF0u)

Definition at line 8826 of file regs.h.

#define DWT_CELLID0_RESET   (0x0000000Du)

Definition at line 8828 of file regs.h.

#define DWT_CELLID1   *((volatile int32u *)0xE0001FF4u)

Definition at line 8835 of file regs.h.

#define DWT_CELLID1_ADDR   (0xE0001FF4u)

Definition at line 8837 of file regs.h.

#define DWT_CELLID1_CELLID   (0xFFFFFFFFu)

Definition at line 8840 of file regs.h.

#define DWT_CELLID1_CELLID_BIT   (0)

Definition at line 8842 of file regs.h.

#define DWT_CELLID1_CELLID_BITS   (32)

Definition at line 8843 of file regs.h.

#define DWT_CELLID1_CELLID_MASK   (0xFFFFFFFFu)

Definition at line 8841 of file regs.h.

#define DWT_CELLID1_REG   *((volatile int32u *)0xE0001FF4u)

Definition at line 8836 of file regs.h.

#define DWT_CELLID1_RESET   (0x000000E0u)

Definition at line 8838 of file regs.h.

#define DWT_CELLID2   *((volatile int32u *)0xE0001FF8u)

Definition at line 8845 of file regs.h.

#define DWT_CELLID2_ADDR   (0xE0001FF8u)

Definition at line 8847 of file regs.h.

#define DWT_CELLID2_CELLID   (0xFFFFFFFFu)

Definition at line 8850 of file regs.h.

#define DWT_CELLID2_CELLID_BIT   (0)

Definition at line 8852 of file regs.h.

#define DWT_CELLID2_CELLID_BITS   (32)

Definition at line 8853 of file regs.h.

#define DWT_CELLID2_CELLID_MASK   (0xFFFFFFFFu)

Definition at line 8851 of file regs.h.

#define DWT_CELLID2_REG   *((volatile int32u *)0xE0001FF8u)

Definition at line 8846 of file regs.h.

#define DWT_CELLID2_RESET   (0x00000005u)

Definition at line 8848 of file regs.h.

#define DWT_CELLID3   *((volatile int32u *)0xE0001FFCu)

Definition at line 8855 of file regs.h.

#define DWT_CELLID3_ADDR   (0xE0001FFCu)

Definition at line 8857 of file regs.h.

#define DWT_CELLID3_CELLID   (0xFFFFFFFFu)

Definition at line 8860 of file regs.h.

#define DWT_CELLID3_CELLID_BIT   (0)

Definition at line 8862 of file regs.h.

#define DWT_CELLID3_CELLID_BITS   (32)

Definition at line 8863 of file regs.h.

#define DWT_CELLID3_CELLID_MASK   (0xFFFFFFFFu)

Definition at line 8861 of file regs.h.

#define DWT_CELLID3_REG   *((volatile int32u *)0xE0001FFCu)

Definition at line 8856 of file regs.h.

#define DWT_CELLID3_RESET   (0x000000B1u)

Definition at line 8858 of file regs.h.

#define DWT_COMP0   *((volatile int32u *)0xE0001020u)

Definition at line 8555 of file regs.h.

#define DWT_COMP0_ADDR   (0xE0001020u)

Definition at line 8557 of file regs.h.

#define DWT_COMP0_COMP0   (0xFFFFFFFFu)

Definition at line 8560 of file regs.h.

#define DWT_COMP0_COMP0_BIT   (0)

Definition at line 8562 of file regs.h.

#define DWT_COMP0_COMP0_BITS   (32)

Definition at line 8563 of file regs.h.

#define DWT_COMP0_COMP0_MASK   (0xFFFFFFFFu)

Definition at line 8561 of file regs.h.

#define DWT_COMP0_REG   *((volatile int32u *)0xE0001020u)

Definition at line 8556 of file regs.h.

#define DWT_COMP0_RESET   (0x00000000u)

Definition at line 8558 of file regs.h.

#define DWT_COMP1   *((volatile int32u *)0xE0001030u)

Definition at line 8600 of file regs.h.

#define DWT_COMP1_ADDR   (0xE0001030u)

Definition at line 8602 of file regs.h.

#define DWT_COMP1_COMP1   (0xFFFFFFFFu)

Definition at line 8605 of file regs.h.

#define DWT_COMP1_COMP1_BIT   (0)

Definition at line 8607 of file regs.h.

#define DWT_COMP1_COMP1_BITS   (32)

Definition at line 8608 of file regs.h.

#define DWT_COMP1_COMP1_MASK   (0xFFFFFFFFu)

Definition at line 8606 of file regs.h.

#define DWT_COMP1_REG   *((volatile int32u *)0xE0001030u)

Definition at line 8601 of file regs.h.

#define DWT_COMP1_RESET   (0x00000000u)

Definition at line 8603 of file regs.h.

#define DWT_COMP2   *((volatile int32u *)0xE0001040u)

Definition at line 8665 of file regs.h.

#define DWT_COMP2_ADDR   (0xE0001040u)

Definition at line 8667 of file regs.h.

#define DWT_COMP2_COMP2   (0xFFFFFFFFu)

Definition at line 8670 of file regs.h.

#define DWT_COMP2_COMP2_BIT   (0)

Definition at line 8672 of file regs.h.

#define DWT_COMP2_COMP2_BITS   (32)

Definition at line 8673 of file regs.h.

#define DWT_COMP2_COMP2_MASK   (0xFFFFFFFFu)

Definition at line 8671 of file regs.h.

#define DWT_COMP2_REG   *((volatile int32u *)0xE0001040u)

Definition at line 8666 of file regs.h.

#define DWT_COMP2_RESET   (0x00000000u)

Definition at line 8668 of file regs.h.

#define DWT_COMP3   *((volatile int32u *)0xE0001050u)

Definition at line 8705 of file regs.h.

#define DWT_COMP3_ADDR   (0xE0001050u)

Definition at line 8707 of file regs.h.

#define DWT_COMP3_COMP3   (0xFFFFFFFFu)

Definition at line 8710 of file regs.h.

#define DWT_COMP3_COMP3_BIT   (0)

Definition at line 8712 of file regs.h.

#define DWT_COMP3_COMP3_BITS   (32)

Definition at line 8713 of file regs.h.

#define DWT_COMP3_COMP3_MASK   (0xFFFFFFFFu)

Definition at line 8711 of file regs.h.

#define DWT_COMP3_REG   *((volatile int32u *)0xE0001050u)

Definition at line 8706 of file regs.h.

#define DWT_COMP3_RESET   (0x00000000u)

Definition at line 8708 of file regs.h.

#define DWT_CPICNT   *((volatile int32u *)0xE0001008u)

Definition at line 8495 of file regs.h.

#define DWT_CPICNT_ADDR   (0xE0001008u)

Definition at line 8497 of file regs.h.

#define DWT_CPICNT_CPICNT   (0x000000FFu)

Definition at line 8500 of file regs.h.

#define DWT_CPICNT_CPICNT_BIT   (0)

Definition at line 8502 of file regs.h.

#define DWT_CPICNT_CPICNT_BITS   (8)

Definition at line 8503 of file regs.h.

#define DWT_CPICNT_CPICNT_MASK   (0x000000FFu)

Definition at line 8501 of file regs.h.

#define DWT_CPICNT_REG   *((volatile int32u *)0xE0001008u)

Definition at line 8496 of file regs.h.

#define DWT_CPICNT_RESET   (0x00000000u)

Definition at line 8498 of file regs.h.

#define DWT_CTRL   *((volatile int32u *)0xE0001000u)

Definition at line 8410 of file regs.h.

#define DWT_CTRL_ADDR   (0xE0001000u)

Definition at line 8412 of file regs.h.

#define DWT_CTRL_CPIEVTENA   (0x00020000u)

Definition at line 8445 of file regs.h.

#define DWT_CTRL_CPIEVTENA_BIT   (17)

Definition at line 8447 of file regs.h.

#define DWT_CTRL_CPIEVTENA_BITS   (1)

Definition at line 8448 of file regs.h.

#define DWT_CTRL_CPIEVTENA_MASK   (0x00020000u)

Definition at line 8446 of file regs.h.

#define DWT_CTRL_CYCCNTENA   (0x00000001u)

Definition at line 8480 of file regs.h.

#define DWT_CTRL_CYCCNTENA_BIT   (0)

Definition at line 8482 of file regs.h.

#define DWT_CTRL_CYCCNTENA_BITS   (1)

Definition at line 8483 of file regs.h.

#define DWT_CTRL_CYCCNTENA_MASK   (0x00000001u)

Definition at line 8481 of file regs.h.

#define DWT_CTRL_CYCEVTENA   (0x00400000u)

Definition at line 8420 of file regs.h.

#define DWT_CTRL_CYCEVTENA_BIT   (22)

Definition at line 8422 of file regs.h.

#define DWT_CTRL_CYCEVTENA_BITS   (1)

Definition at line 8423 of file regs.h.

#define DWT_CTRL_CYCEVTENA_MASK   (0x00400000u)

Definition at line 8421 of file regs.h.

#define DWT_CTRL_CYCTAP   (0x00000200u)

Definition at line 8465 of file regs.h.

#define DWT_CTRL_CYCTAP_BIT   (9)

Definition at line 8467 of file regs.h.

#define DWT_CTRL_CYCTAP_BITS   (1)

Definition at line 8468 of file regs.h.

#define DWT_CTRL_CYCTAP_MASK   (0x00000200u)

Definition at line 8466 of file regs.h.

#define DWT_CTRL_EXCEVTENA   (0x00040000u)

Definition at line 8440 of file regs.h.

#define DWT_CTRL_EXCEVTENA_BIT   (18)

Definition at line 8442 of file regs.h.

#define DWT_CTRL_EXCEVTENA_BITS   (1)

Definition at line 8443 of file regs.h.

#define DWT_CTRL_EXCEVTENA_MASK   (0x00040000u)

Definition at line 8441 of file regs.h.

#define DWT_CTRL_EXCTRCENA   (0x00010000u)

Definition at line 8450 of file regs.h.

#define DWT_CTRL_EXCTRCENA_BIT   (16)

Definition at line 8452 of file regs.h.

#define DWT_CTRL_EXCTRCENA_BITS   (1)

Definition at line 8453 of file regs.h.

#define DWT_CTRL_EXCTRCENA_MASK   (0x00010000u)

Definition at line 8451 of file regs.h.

#define DWT_CTRL_FOLDEVTENA   (0x00200000u)

Definition at line 8425 of file regs.h.

#define DWT_CTRL_FOLDEVTENA_BIT   (21)

Definition at line 8427 of file regs.h.

#define DWT_CTRL_FOLDEVTENA_BITS   (1)

Definition at line 8428 of file regs.h.

#define DWT_CTRL_FOLDEVTENA_MASK   (0x00200000u)

Definition at line 8426 of file regs.h.

#define DWT_CTRL_LSUEVTENA   (0x00100000u)

Definition at line 8430 of file regs.h.

#define DWT_CTRL_LSUEVTENA_BIT   (20)

Definition at line 8432 of file regs.h.

#define DWT_CTRL_LSUEVTENA_BITS   (1)

Definition at line 8433 of file regs.h.

#define DWT_CTRL_LSUEVTENA_MASK   (0x00100000u)

Definition at line 8431 of file regs.h.

#define DWT_CTRL_NUMCOMP   (0xF0000000u)

Definition at line 8415 of file regs.h.

#define DWT_CTRL_NUMCOMP_BIT   (28)

Definition at line 8417 of file regs.h.

#define DWT_CTRL_NUMCOMP_BITS   (4)

Definition at line 8418 of file regs.h.

#define DWT_CTRL_NUMCOMP_MASK   (0xF0000000u)

Definition at line 8416 of file regs.h.

#define DWT_CTRL_PCSAMPLEENA   (0x00001000u)

Definition at line 8455 of file regs.h.

#define DWT_CTRL_PCSAMPLEENA_BIT   (12)

Definition at line 8457 of file regs.h.

#define DWT_CTRL_PCSAMPLEENA_BITS   (1)

Definition at line 8458 of file regs.h.

#define DWT_CTRL_PCSAMPLEENA_MASK   (0x00001000u)

Definition at line 8456 of file regs.h.

#define DWT_CTRL_POSTCNT   (0x000001E0u)

Definition at line 8470 of file regs.h.

#define DWT_CTRL_POSTCNT_BIT   (5)

Definition at line 8472 of file regs.h.

#define DWT_CTRL_POSTCNT_BITS   (4)

Definition at line 8473 of file regs.h.

#define DWT_CTRL_POSTCNT_MASK   (0x000001E0u)

Definition at line 8471 of file regs.h.

#define DWT_CTRL_POSTPRESET   (0x0000001Eu)

Definition at line 8475 of file regs.h.

#define DWT_CTRL_POSTPRESET_BIT   (1)

Definition at line 8477 of file regs.h.

#define DWT_CTRL_POSTPRESET_BITS   (4)

Definition at line 8478 of file regs.h.

#define DWT_CTRL_POSTPRESET_MASK   (0x0000001Eu)

Definition at line 8476 of file regs.h.

#define DWT_CTRL_REG   *((volatile int32u *)0xE0001000u)

Definition at line 8411 of file regs.h.

#define DWT_CTRL_RESET   (0x40000000u)

Definition at line 8413 of file regs.h.

#define DWT_CTRL_SLEEPEVTENA   (0x00080000u)

Definition at line 8435 of file regs.h.

#define DWT_CTRL_SLEEPEVTENA_BIT   (19)

Definition at line 8437 of file regs.h.

#define DWT_CTRL_SLEEPEVTENA_BITS   (1)

Definition at line 8438 of file regs.h.

#define DWT_CTRL_SLEEPEVTENA_MASK   (0x00080000u)

Definition at line 8436 of file regs.h.

#define DWT_CTRL_SYNCTAP   (0x00000C00u)

Definition at line 8460 of file regs.h.

#define DWT_CTRL_SYNCTAP_BIT   (10)

Definition at line 8462 of file regs.h.

#define DWT_CTRL_SYNCTAP_BITS   (2)

Definition at line 8463 of file regs.h.

#define DWT_CTRL_SYNCTAP_MASK   (0x00000C00u)

Definition at line 8461 of file regs.h.

#define DWT_CYCCNT   *((volatile int32u *)0xE0001004u)

Definition at line 8485 of file regs.h.

#define DWT_CYCCNT_ADDR   (0xE0001004u)

Definition at line 8487 of file regs.h.

#define DWT_CYCCNT_CYCCNT   (0xFFFFFFFFu)

Definition at line 8490 of file regs.h.

#define DWT_CYCCNT_CYCCNT_BIT   (0)

Definition at line 8492 of file regs.h.

#define DWT_CYCCNT_CYCCNT_BITS   (32)

Definition at line 8493 of file regs.h.

#define DWT_CYCCNT_CYCCNT_MASK   (0xFFFFFFFFu)

Definition at line 8491 of file regs.h.

#define DWT_CYCCNT_REG   *((volatile int32u *)0xE0001004u)

Definition at line 8486 of file regs.h.

#define DWT_CYCCNT_RESET   (0x00000000u)

Definition at line 8488 of file regs.h.

#define DWT_EXCCNT   *((volatile int32u *)0xE000100Cu)

Definition at line 8505 of file regs.h.

#define DWT_EXCCNT_ADDR   (0xE000100Cu)

Definition at line 8507 of file regs.h.

#define DWT_EXCCNT_EXCCNT   (0x000000FFu)

Definition at line 8510 of file regs.h.

#define DWT_EXCCNT_EXCCNT_BIT   (0)

Definition at line 8512 of file regs.h.

#define DWT_EXCCNT_EXCCNT_BITS   (8)

Definition at line 8513 of file regs.h.

#define DWT_EXCCNT_EXCCNT_MASK   (0x000000FFu)

Definition at line 8511 of file regs.h.

#define DWT_EXCCNT_REG   *((volatile int32u *)0xE000100Cu)

Definition at line 8506 of file regs.h.

#define DWT_EXCCNT_RESET   (0x00000000u)

Definition at line 8508 of file regs.h.

#define DWT_FOLDCNT   *((volatile int32u *)0xE0001018u)

Definition at line 8535 of file regs.h.

#define DWT_FOLDCNT_ADDR   (0xE0001018u)

Definition at line 8537 of file regs.h.

#define DWT_FOLDCNT_CPICNT   (0x000000FFu)

Definition at line 8540 of file regs.h.

#define DWT_FOLDCNT_CPICNT_BIT   (0)

Definition at line 8542 of file regs.h.

#define DWT_FOLDCNT_CPICNT_BITS   (8)

Definition at line 8543 of file regs.h.

#define DWT_FOLDCNT_CPICNT_MASK   (0x000000FFu)

Definition at line 8541 of file regs.h.

#define DWT_FOLDCNT_REG   *((volatile int32u *)0xE0001018u)

Definition at line 8536 of file regs.h.

#define DWT_FOLDCNT_RESET   (0x00000000u)

Definition at line 8538 of file regs.h.

#define DWT_FUNCTION0   *((volatile int32u *)0xE0001028u)

Definition at line 8575 of file regs.h.

#define DWT_FUNCTION0_ADDR   (0xE0001028u)

Definition at line 8577 of file regs.h.

#define DWT_FUNCTION0_CYCMATCH   (0x00000080u)

Definition at line 8585 of file regs.h.

#define DWT_FUNCTION0_CYCMATCH_BIT   (7)

Definition at line 8587 of file regs.h.

#define DWT_FUNCTION0_CYCMATCH_BITS   (1)

Definition at line 8588 of file regs.h.

#define DWT_FUNCTION0_CYCMATCH_MASK   (0x00000080u)

Definition at line 8586 of file regs.h.

#define DWT_FUNCTION0_EMITRANGE   (0x00000020u)

Definition at line 8590 of file regs.h.

#define DWT_FUNCTION0_EMITRANGE_BIT   (5)

Definition at line 8592 of file regs.h.

#define DWT_FUNCTION0_EMITRANGE_BITS   (1)

Definition at line 8593 of file regs.h.

#define DWT_FUNCTION0_EMITRANGE_MASK   (0x00000020u)

Definition at line 8591 of file regs.h.

#define DWT_FUNCTION0_FUNCTION   (0x0000000Fu)

Definition at line 8595 of file regs.h.

#define DWT_FUNCTION0_FUNCTION_BIT   (0)

Definition at line 8597 of file regs.h.

#define DWT_FUNCTION0_FUNCTION_BITS   (4)

Definition at line 8598 of file regs.h.

#define DWT_FUNCTION0_FUNCTION_MASK   (0x0000000Fu)

Definition at line 8596 of file regs.h.

#define DWT_FUNCTION0_MATCHED   (0x01000000u)

Definition at line 8580 of file regs.h.

#define DWT_FUNCTION0_MATCHED_BIT   (24)

Definition at line 8582 of file regs.h.

#define DWT_FUNCTION0_MATCHED_BITS   (1)

Definition at line 8583 of file regs.h.

#define DWT_FUNCTION0_MATCHED_MASK   (0x01000000u)

Definition at line 8581 of file regs.h.

#define DWT_FUNCTION0_REG   *((volatile int32u *)0xE0001028u)

Definition at line 8576 of file regs.h.

#define DWT_FUNCTION0_RESET   (0x00000000u)

Definition at line 8578 of file regs.h.

#define DWT_FUNCTION1   *((volatile int32u *)0xE0001038u)

Definition at line 8620 of file regs.h.

#define DWT_FUNCTION1_ADDR   (0xE0001038u)

Definition at line 8622 of file regs.h.

#define DWT_FUNCTION1_DATAVADDR0   (0x0000F000u)

Definition at line 8635 of file regs.h.

#define DWT_FUNCTION1_DATAVADDR0_BIT   (12)

Definition at line 8637 of file regs.h.

#define DWT_FUNCTION1_DATAVADDR0_BITS   (4)

Definition at line 8638 of file regs.h.

#define DWT_FUNCTION1_DATAVADDR0_MASK   (0x0000F000u)

Definition at line 8636 of file regs.h.

#define DWT_FUNCTION1_DATAVADDR1   (0x000F0000u)

Definition at line 8630 of file regs.h.

#define DWT_FUNCTION1_DATAVADDR1_BIT   (16)

Definition at line 8632 of file regs.h.

#define DWT_FUNCTION1_DATAVADDR1_BITS   (4)

Definition at line 8633 of file regs.h.

#define DWT_FUNCTION1_DATAVADDR1_MASK   (0x000F0000u)

Definition at line 8631 of file regs.h.

#define DWT_FUNCTION1_DATAVMATCH   (0x00000100u)

Definition at line 8650 of file regs.h.

#define DWT_FUNCTION1_DATAVMATCH_BIT   (8)

Definition at line 8652 of file regs.h.

#define DWT_FUNCTION1_DATAVMATCH_BITS   (1)

Definition at line 8653 of file regs.h.

#define DWT_FUNCTION1_DATAVMATCH_MASK   (0x00000100u)

Definition at line 8651 of file regs.h.

#define DWT_FUNCTION1_DATAVSIZE   (0x00000C00u)

Definition at line 8640 of file regs.h.

#define DWT_FUNCTION1_DATAVSIZE_BIT   (10)

Definition at line 8642 of file regs.h.

#define DWT_FUNCTION1_DATAVSIZE_BITS   (2)

Definition at line 8643 of file regs.h.

#define DWT_FUNCTION1_DATAVSIZE_MASK   (0x00000C00u)

Definition at line 8641 of file regs.h.

#define DWT_FUNCTION1_EMITRANGE   (0x00000020u)

Definition at line 8655 of file regs.h.

#define DWT_FUNCTION1_EMITRANGE_BIT   (5)

Definition at line 8657 of file regs.h.

#define DWT_FUNCTION1_EMITRANGE_BITS   (1)

Definition at line 8658 of file regs.h.

#define DWT_FUNCTION1_EMITRANGE_MASK   (0x00000020u)

Definition at line 8656 of file regs.h.

#define DWT_FUNCTION1_FUNCTION   (0x0000000Fu)

Definition at line 8660 of file regs.h.

#define DWT_FUNCTION1_FUNCTION_BIT   (0)

Definition at line 8662 of file regs.h.

#define DWT_FUNCTION1_FUNCTION_BITS   (4)

Definition at line 8663 of file regs.h.

#define DWT_FUNCTION1_FUNCTION_MASK   (0x0000000Fu)

Definition at line 8661 of file regs.h.

#define DWT_FUNCTION1_LNK1ENA   (0x00000200u)

Definition at line 8645 of file regs.h.

#define DWT_FUNCTION1_LNK1ENA_BIT   (9)

Definition at line 8647 of file regs.h.

#define DWT_FUNCTION1_LNK1ENA_BITS   (1)

Definition at line 8648 of file regs.h.

#define DWT_FUNCTION1_LNK1ENA_MASK   (0x00000200u)

Definition at line 8646 of file regs.h.

#define DWT_FUNCTION1_MATCHED   (0x01000000u)

Definition at line 8625 of file regs.h.

#define DWT_FUNCTION1_MATCHED_BIT   (24)

Definition at line 8627 of file regs.h.

#define DWT_FUNCTION1_MATCHED_BITS   (1)

Definition at line 8628 of file regs.h.

#define DWT_FUNCTION1_MATCHED_MASK   (0x01000000u)

Definition at line 8626 of file regs.h.

#define DWT_FUNCTION1_REG   *((volatile int32u *)0xE0001038u)

Definition at line 8621 of file regs.h.

#define DWT_FUNCTION1_RESET   (0x00000200u)

Definition at line 8623 of file regs.h.

#define DWT_FUNCTION2   *((volatile int32u *)0xE0001048u)

Definition at line 8685 of file regs.h.

#define DWT_FUNCTION2_ADDR   (0xE0001048u)

Definition at line 8687 of file regs.h.

#define DWT_FUNCTION2_EMITRANGE   (0x00000020u)

Definition at line 8695 of file regs.h.

#define DWT_FUNCTION2_EMITRANGE_BIT   (5)

Definition at line 8697 of file regs.h.

#define DWT_FUNCTION2_EMITRANGE_BITS   (1)

Definition at line 8698 of file regs.h.

#define DWT_FUNCTION2_EMITRANGE_MASK   (0x00000020u)

Definition at line 8696 of file regs.h.

#define DWT_FUNCTION2_FUNCTION   (0x0000000Fu)

Definition at line 8700 of file regs.h.

#define DWT_FUNCTION2_FUNCTION_BIT   (0)

Definition at line 8702 of file regs.h.

#define DWT_FUNCTION2_FUNCTION_BITS   (4)

Definition at line 8703 of file regs.h.

#define DWT_FUNCTION2_FUNCTION_MASK   (0x0000000Fu)

Definition at line 8701 of file regs.h.

#define DWT_FUNCTION2_MATCHED   (0x01000000u)

Definition at line 8690 of file regs.h.

#define DWT_FUNCTION2_MATCHED_BIT   (24)

Definition at line 8692 of file regs.h.

#define DWT_FUNCTION2_MATCHED_BITS   (1)

Definition at line 8693 of file regs.h.

#define DWT_FUNCTION2_MATCHED_MASK   (0x01000000u)

Definition at line 8691 of file regs.h.

#define DWT_FUNCTION2_REG   *((volatile int32u *)0xE0001048u)

Definition at line 8686 of file regs.h.

#define DWT_FUNCTION2_RESET   (0x00000000u)

Definition at line 8688 of file regs.h.

#define DWT_FUNCTION3   *((volatile int32u *)0xE0001058u)

Definition at line 8725 of file regs.h.

#define DWT_FUNCTION3_ADDR   (0xE0001058u)

Definition at line 8727 of file regs.h.

#define DWT_FUNCTION3_EMITRANGE   (0x00000020u)

Definition at line 8735 of file regs.h.

#define DWT_FUNCTION3_EMITRANGE_BIT   (5)

Definition at line 8737 of file regs.h.

#define DWT_FUNCTION3_EMITRANGE_BITS   (1)

Definition at line 8738 of file regs.h.

#define DWT_FUNCTION3_EMITRANGE_MASK   (0x00000020u)

Definition at line 8736 of file regs.h.

#define DWT_FUNCTION3_FUNCTION   (0x0000000Fu)

Definition at line 8740 of file regs.h.

#define DWT_FUNCTION3_FUNCTION_BIT   (0)

Definition at line 8742 of file regs.h.

#define DWT_FUNCTION3_FUNCTION_BITS   (4)

Definition at line 8743 of file regs.h.

#define DWT_FUNCTION3_FUNCTION_MASK   (0x0000000Fu)

Definition at line 8741 of file regs.h.

#define DWT_FUNCTION3_MATCHED   (0x01000000u)

Definition at line 8730 of file regs.h.

#define DWT_FUNCTION3_MATCHED_BIT   (24)

Definition at line 8732 of file regs.h.

#define DWT_FUNCTION3_MATCHED_BITS   (1)

Definition at line 8733 of file regs.h.

#define DWT_FUNCTION3_MATCHED_MASK   (0x01000000u)

Definition at line 8731 of file regs.h.

#define DWT_FUNCTION3_REG   *((volatile int32u *)0xE0001058u)

Definition at line 8726 of file regs.h.

#define DWT_FUNCTION3_RESET   (0x00000000u)

Definition at line 8728 of file regs.h.

#define DWT_LSUCNT   *((volatile int32u *)0xE0001014u)

Definition at line 8525 of file regs.h.

#define DWT_LSUCNT_ADDR   (0xE0001014u)

Definition at line 8527 of file regs.h.

#define DWT_LSUCNT_CPICNT   (0x000000FFu)

Definition at line 8530 of file regs.h.

#define DWT_LSUCNT_CPICNT_BIT   (0)

Definition at line 8532 of file regs.h.

#define DWT_LSUCNT_CPICNT_BITS   (8)

Definition at line 8533 of file regs.h.

#define DWT_LSUCNT_CPICNT_MASK   (0x000000FFu)

Definition at line 8531 of file regs.h.

#define DWT_LSUCNT_REG   *((volatile int32u *)0xE0001014u)

Definition at line 8526 of file regs.h.

#define DWT_LSUCNT_RESET   (0x00000000u)

Definition at line 8528 of file regs.h.

#define DWT_MASK0   *((volatile int32u *)0xE0001024u)

Definition at line 8565 of file regs.h.

#define DWT_MASK0_ADDR   (0xE0001024u)

Definition at line 8567 of file regs.h.

#define DWT_MASK0_MASK0   (0x0000001Fu)

Definition at line 8570 of file regs.h.

#define DWT_MASK0_MASK0_BIT   (0)

Definition at line 8572 of file regs.h.

#define DWT_MASK0_MASK0_BITS   (5)

Definition at line 8573 of file regs.h.

#define DWT_MASK0_MASK0_MASK   (0x0000001Fu)

Definition at line 8571 of file regs.h.

#define DWT_MASK0_REG   *((volatile int32u *)0xE0001024u)

Definition at line 8566 of file regs.h.

#define DWT_MASK0_RESET   (0x00000000u)

Definition at line 8568 of file regs.h.

#define DWT_MASK1   *((volatile int32u *)0xE0001034u)

Definition at line 8610 of file regs.h.

#define DWT_MASK1_ADDR   (0xE0001034u)

Definition at line 8612 of file regs.h.

#define DWT_MASK1_MASK1   (0x0000001Fu)

Definition at line 8615 of file regs.h.

#define DWT_MASK1_MASK1_BIT   (0)

Definition at line 8617 of file regs.h.

#define DWT_MASK1_MASK1_BITS   (5)

Definition at line 8618 of file regs.h.

#define DWT_MASK1_MASK1_MASK   (0x0000001Fu)

Definition at line 8616 of file regs.h.

#define DWT_MASK1_REG   *((volatile int32u *)0xE0001034u)

Definition at line 8611 of file regs.h.

#define DWT_MASK1_RESET   (0x00000000u)

Definition at line 8613 of file regs.h.

#define DWT_MASK2   *((volatile int32u *)0xE0001044u)

Definition at line 8675 of file regs.h.

#define DWT_MASK2_ADDR   (0xE0001044u)

Definition at line 8677 of file regs.h.

#define DWT_MASK2_MASK2   (0x0000001Fu)

Definition at line 8680 of file regs.h.

#define DWT_MASK2_MASK2_BIT   (0)

Definition at line 8682 of file regs.h.

#define DWT_MASK2_MASK2_BITS   (5)

Definition at line 8683 of file regs.h.

#define DWT_MASK2_MASK2_MASK   (0x0000001Fu)

Definition at line 8681 of file regs.h.

#define DWT_MASK2_REG   *((volatile int32u *)0xE0001044u)

Definition at line 8676 of file regs.h.

#define DWT_MASK2_RESET   (0x00000000u)

Definition at line 8678 of file regs.h.

#define DWT_MASK3   *((volatile int32u *)0xE0001054u)

Definition at line 8715 of file regs.h.

#define DWT_MASK3_ADDR   (0xE0001054u)

Definition at line 8717 of file regs.h.

#define DWT_MASK3_MASK3   (0x0000001Fu)

Definition at line 8720 of file regs.h.

#define DWT_MASK3_MASK3_BIT   (0)

Definition at line 8722 of file regs.h.

#define DWT_MASK3_MASK3_BITS   (5)

Definition at line 8723 of file regs.h.

#define DWT_MASK3_MASK3_MASK   (0x0000001Fu)

Definition at line 8721 of file regs.h.

#define DWT_MASK3_REG   *((volatile int32u *)0xE0001054u)

Definition at line 8716 of file regs.h.

#define DWT_MASK3_RESET   (0x00000000u)

Definition at line 8718 of file regs.h.

#define DWT_PCSR   *((volatile int32u *)0xE000101Cu)

Definition at line 8545 of file regs.h.

#define DWT_PCSR_ADDR   (0xE000101Cu)

Definition at line 8547 of file regs.h.

#define DWT_PCSR_EIASAMPLE   (0xFFFFFFFFu)

Definition at line 8550 of file regs.h.

#define DWT_PCSR_EIASAMPLE_BIT   (0)

Definition at line 8552 of file regs.h.

#define DWT_PCSR_EIASAMPLE_BITS   (32)

Definition at line 8553 of file regs.h.

#define DWT_PCSR_EIASAMPLE_MASK   (0xFFFFFFFFu)

Definition at line 8551 of file regs.h.

#define DWT_PCSR_REG   *((volatile int32u *)0xE000101Cu)

Definition at line 8546 of file regs.h.

#define DWT_PCSR_RESET   (0x00000000u)

Definition at line 8548 of file regs.h.

#define DWT_PERIPHID0   *((volatile int32u *)0xE0001FE0u)

Definition at line 8785 of file regs.h.

#define DWT_PERIPHID0_ADDR   (0xE0001FE0u)

Definition at line 8787 of file regs.h.

#define DWT_PERIPHID0_PERIPHID   (0xFFFFFFFFu)

Definition at line 8790 of file regs.h.

#define DWT_PERIPHID0_PERIPHID_BIT   (0)

Definition at line 8792 of file regs.h.

#define DWT_PERIPHID0_PERIPHID_BITS   (32)

Definition at line 8793 of file regs.h.

#define DWT_PERIPHID0_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 8791 of file regs.h.

#define DWT_PERIPHID0_REG   *((volatile int32u *)0xE0001FE0u)

Definition at line 8786 of file regs.h.

#define DWT_PERIPHID0_RESET   (0x00000002u)

Definition at line 8788 of file regs.h.

#define DWT_PERIPHID1   *((volatile int32u *)0xE0001FE4u)

Definition at line 8795 of file regs.h.

#define DWT_PERIPHID1_ADDR   (0xE0001FE4u)

Definition at line 8797 of file regs.h.

#define DWT_PERIPHID1_PERIPHID   (0xFFFFFFFFu)

Definition at line 8800 of file regs.h.

#define DWT_PERIPHID1_PERIPHID_BIT   (0)

Definition at line 8802 of file regs.h.

#define DWT_PERIPHID1_PERIPHID_BITS   (32)

Definition at line 8803 of file regs.h.

#define DWT_PERIPHID1_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 8801 of file regs.h.

#define DWT_PERIPHID1_REG   *((volatile int32u *)0xE0001FE4u)

Definition at line 8796 of file regs.h.

#define DWT_PERIPHID1_RESET   (0x00000000u)

Definition at line 8798 of file regs.h.

#define DWT_PERIPHID2   *((volatile int32u *)0xE0001FE8u)

Definition at line 8805 of file regs.h.

#define DWT_PERIPHID2_ADDR   (0xE0001FE8u)

Definition at line 8807 of file regs.h.

#define DWT_PERIPHID2_PERIPHID   (0xFFFFFFFFu)

Definition at line 8810 of file regs.h.

#define DWT_PERIPHID2_PERIPHID_BIT   (0)

Definition at line 8812 of file regs.h.

#define DWT_PERIPHID2_PERIPHID_BITS   (32)

Definition at line 8813 of file regs.h.

#define DWT_PERIPHID2_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 8811 of file regs.h.

#define DWT_PERIPHID2_REG   *((volatile int32u *)0xE0001FE8u)

Definition at line 8806 of file regs.h.

#define DWT_PERIPHID2_RESET   (0x0000001Bu)

Definition at line 8808 of file regs.h.

#define DWT_PERIPHID3   *((volatile int32u *)0xE0001FECu)

Definition at line 8815 of file regs.h.

#define DWT_PERIPHID3_ADDR   (0xE0001FECu)

Definition at line 8817 of file regs.h.

#define DWT_PERIPHID3_PERIPHID   (0xFFFFFFFFu)

Definition at line 8820 of file regs.h.

#define DWT_PERIPHID3_PERIPHID_BIT   (0)

Definition at line 8822 of file regs.h.

#define DWT_PERIPHID3_PERIPHID_BITS   (32)

Definition at line 8823 of file regs.h.

#define DWT_PERIPHID3_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 8821 of file regs.h.

#define DWT_PERIPHID3_REG   *((volatile int32u *)0xE0001FECu)

Definition at line 8816 of file regs.h.

#define DWT_PERIPHID3_RESET   (0x00000000u)

Definition at line 8818 of file regs.h.

#define DWT_PERIPHID4   *((volatile int32u *)0xE0001FD0u)

Definition at line 8745 of file regs.h.

#define DWT_PERIPHID4_ADDR   (0xE0001FD0u)

Definition at line 8747 of file regs.h.

#define DWT_PERIPHID4_PERIPHID   (0xFFFFFFFFu)

Definition at line 8750 of file regs.h.

#define DWT_PERIPHID4_PERIPHID_BIT   (0)

Definition at line 8752 of file regs.h.

#define DWT_PERIPHID4_PERIPHID_BITS   (32)

Definition at line 8753 of file regs.h.

#define DWT_PERIPHID4_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 8751 of file regs.h.

#define DWT_PERIPHID4_REG   *((volatile int32u *)0xE0001FD0u)

Definition at line 8746 of file regs.h.

#define DWT_PERIPHID4_RESET   (0x00000004u)

Definition at line 8748 of file regs.h.

#define DWT_PERIPHID5   *((volatile int32u *)0xE0001FD4u)

Definition at line 8755 of file regs.h.

#define DWT_PERIPHID5_ADDR   (0xE0001FD4u)

Definition at line 8757 of file regs.h.

#define DWT_PERIPHID5_PERIPHID   (0xFFFFFFFFu)

Definition at line 8760 of file regs.h.

#define DWT_PERIPHID5_PERIPHID_BIT   (0)

Definition at line 8762 of file regs.h.

#define DWT_PERIPHID5_PERIPHID_BITS   (32)

Definition at line 8763 of file regs.h.

#define DWT_PERIPHID5_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 8761 of file regs.h.

#define DWT_PERIPHID5_REG   *((volatile int32u *)0xE0001FD4u)

Definition at line 8756 of file regs.h.

#define DWT_PERIPHID5_RESET   (0x00000000u)

Definition at line 8758 of file regs.h.

#define DWT_PERIPHID6   *((volatile int32u *)0xE0001FD8u)

Definition at line 8765 of file regs.h.

#define DWT_PERIPHID6_ADDR   (0xE0001FD8u)

Definition at line 8767 of file regs.h.

#define DWT_PERIPHID6_PERIPHID   (0xFFFFFFFFu)

Definition at line 8770 of file regs.h.

#define DWT_PERIPHID6_PERIPHID_BIT   (0)

Definition at line 8772 of file regs.h.

#define DWT_PERIPHID6_PERIPHID_BITS   (32)

Definition at line 8773 of file regs.h.

#define DWT_PERIPHID6_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 8771 of file regs.h.

#define DWT_PERIPHID6_REG   *((volatile int32u *)0xE0001FD8u)

Definition at line 8766 of file regs.h.

#define DWT_PERIPHID6_RESET   (0x00000000u)

Definition at line 8768 of file regs.h.

#define DWT_PERIPHID7   *((volatile int32u *)0xE0001FDCu)

Definition at line 8775 of file regs.h.

#define DWT_PERIPHID7_ADDR   (0xE0001FDCu)

Definition at line 8777 of file regs.h.

#define DWT_PERIPHID7_PERIPHID   (0xFFFFFFFFu)

Definition at line 8780 of file regs.h.

#define DWT_PERIPHID7_PERIPHID_BIT   (0)

Definition at line 8782 of file regs.h.

#define DWT_PERIPHID7_PERIPHID_BITS   (32)

Definition at line 8783 of file regs.h.

#define DWT_PERIPHID7_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 8781 of file regs.h.

#define DWT_PERIPHID7_REG   *((volatile int32u *)0xE0001FDCu)

Definition at line 8776 of file regs.h.

#define DWT_PERIPHID7_RESET   (0x00000000u)

Definition at line 8778 of file regs.h.

#define DWT_SLEEPCNT   *((volatile int32u *)0xE0001010u)

Definition at line 8515 of file regs.h.

#define DWT_SLEEPCNT_ADDR   (0xE0001010u)

Definition at line 8517 of file regs.h.

#define DWT_SLEEPCNT_REG   *((volatile int32u *)0xE0001010u)

Definition at line 8516 of file regs.h.

#define DWT_SLEEPCNT_RESET   (0x00000000u)

Definition at line 8518 of file regs.h.

#define DWT_SLEEPCNT_SLEEPCNT   (0x000000FFu)

Definition at line 8520 of file regs.h.

#define DWT_SLEEPCNT_SLEEPCNT_BIT   (0)

Definition at line 8522 of file regs.h.

#define DWT_SLEEPCNT_SLEEPCNT_BITS   (8)

Definition at line 8523 of file regs.h.

#define DWT_SLEEPCNT_SLEEPCNT_MASK   (0x000000FFu)

Definition at line 8521 of file regs.h.

#define EVENT_CTRL   *((volatile int32u *)0x40000004u)

Definition at line 50 of file regs.h.

#define EVENT_CTRL_ADDR   (0x40000004u)

Definition at line 52 of file regs.h.

#define EVENT_CTRL_REG   *((volatile int32u *)0x40000004u)

Definition at line 51 of file regs.h.

#define EVENT_CTRL_RESET   (0x00000000u)

Definition at line 53 of file regs.h.

#define EXT_ADDR_0   *((volatile int32u *)0x40002098u)

Definition at line 2105 of file regs.h.

#define EXT_ADDR_0_ADDR   (0x40002098u)

Definition at line 2107 of file regs.h.

#define EXT_ADDR_0_EXT_ADDR_0   (0x0000FFFFu)

Definition at line 2110 of file regs.h.

#define EXT_ADDR_0_EXT_ADDR_0_BIT   (0)

Definition at line 2112 of file regs.h.

#define EXT_ADDR_0_EXT_ADDR_0_BITS   (16)

Definition at line 2113 of file regs.h.

#define EXT_ADDR_0_EXT_ADDR_0_MASK   (0x0000FFFFu)

Definition at line 2111 of file regs.h.

#define EXT_ADDR_0_REG   *((volatile int32u *)0x40002098u)

Definition at line 2106 of file regs.h.

#define EXT_ADDR_0_RESET   (0x00000000u)

Definition at line 2108 of file regs.h.

#define EXT_ADDR_1   *((volatile int32u *)0x4000209Cu)

Definition at line 2115 of file regs.h.

#define EXT_ADDR_1_ADDR   (0x4000209Cu)

Definition at line 2117 of file regs.h.

#define EXT_ADDR_1_EXT_ADDR_1   (0x0000FFFFu)

Definition at line 2120 of file regs.h.

#define EXT_ADDR_1_EXT_ADDR_1_BIT   (0)

Definition at line 2122 of file regs.h.

#define EXT_ADDR_1_EXT_ADDR_1_BITS   (16)

Definition at line 2123 of file regs.h.

#define EXT_ADDR_1_EXT_ADDR_1_MASK   (0x0000FFFFu)

Definition at line 2121 of file regs.h.

#define EXT_ADDR_1_REG   *((volatile int32u *)0x4000209Cu)

Definition at line 2116 of file regs.h.

#define EXT_ADDR_1_RESET   (0x00000000u)

Definition at line 2118 of file regs.h.

#define EXT_ADDR_2   *((volatile int32u *)0x400020A0u)

Definition at line 2125 of file regs.h.

#define EXT_ADDR_2_ADDR   (0x400020A0u)

Definition at line 2127 of file regs.h.

#define EXT_ADDR_2_EXT_ADDR_2   (0x0000FFFFu)

Definition at line 2130 of file regs.h.

#define EXT_ADDR_2_EXT_ADDR_2_BIT   (0)

Definition at line 2132 of file regs.h.

#define EXT_ADDR_2_EXT_ADDR_2_BITS   (16)

Definition at line 2133 of file regs.h.

#define EXT_ADDR_2_EXT_ADDR_2_MASK   (0x0000FFFFu)

Definition at line 2131 of file regs.h.

#define EXT_ADDR_2_REG   *((volatile int32u *)0x400020A0u)

Definition at line 2126 of file regs.h.

#define EXT_ADDR_2_RESET   (0x00000000u)

Definition at line 2128 of file regs.h.

#define EXT_ADDR_3   *((volatile int32u *)0x400020A4u)

Definition at line 2135 of file regs.h.

#define EXT_ADDR_3_ADDR   (0x400020A4u)

Definition at line 2137 of file regs.h.

#define EXT_ADDR_3_EXT_ADDR_3   (0x0000FFFFu)

Definition at line 2140 of file regs.h.

#define EXT_ADDR_3_EXT_ADDR_3_BIT   (0)

Definition at line 2142 of file regs.h.

#define EXT_ADDR_3_EXT_ADDR_3_BITS   (16)

Definition at line 2143 of file regs.h.

#define EXT_ADDR_3_EXT_ADDR_3_MASK   (0x0000FFFFu)

Definition at line 2141 of file regs.h.

#define EXT_ADDR_3_REG   *((volatile int32u *)0x400020A4u)

Definition at line 2136 of file regs.h.

#define EXT_ADDR_3_RESET   (0x00000000u)

Definition at line 2138 of file regs.h.

#define FIXED_CODE_EN   *((volatile int32u *)0x40001034u)

Definition at line 550 of file regs.h.

#define FIXED_CODE_EN_ADDR   (0x40001034u)

Definition at line 552 of file regs.h.

#define FIXED_CODE_EN_FIXED_CODE_EN   (0x00000001u)

Definition at line 555 of file regs.h.

#define FIXED_CODE_EN_FIXED_CODE_EN_BIT   (0)

Definition at line 557 of file regs.h.

#define FIXED_CODE_EN_FIXED_CODE_EN_BITS   (1)

Definition at line 558 of file regs.h.

#define FIXED_CODE_EN_FIXED_CODE_EN_MASK   (0x00000001u)

Definition at line 556 of file regs.h.

#define FIXED_CODE_EN_REG   *((volatile int32u *)0x40001034u)

Definition at line 551 of file regs.h.

#define FIXED_CODE_EN_RESET   (0x00000000u)

Definition at line 553 of file regs.h.

#define FIXED_CODE_H   *((volatile int32u *)0x40001038u)

Definition at line 560 of file regs.h.

#define FIXED_CODE_H_ADDR   (0x40001038u)

Definition at line 562 of file regs.h.

#define FIXED_CODE_H_FIXED_CODE_H   (0x0000FFFFu)

Definition at line 565 of file regs.h.

#define FIXED_CODE_H_FIXED_CODE_H_BIT   (0)

Definition at line 567 of file regs.h.

#define FIXED_CODE_H_FIXED_CODE_H_BITS   (16)

Definition at line 568 of file regs.h.

#define FIXED_CODE_H_FIXED_CODE_H_MASK   (0x0000FFFFu)

Definition at line 566 of file regs.h.

#define FIXED_CODE_H_REG   *((volatile int32u *)0x40001038u)

Definition at line 561 of file regs.h.

#define FIXED_CODE_H_RESET   (0x00000000u)

Definition at line 563 of file regs.h.

#define FIXED_CODE_L   *((volatile int32u *)0x4000103Cu)

Definition at line 570 of file regs.h.

#define FIXED_CODE_L_ADDR   (0x4000103Cu)

Definition at line 572 of file regs.h.

#define FIXED_CODE_L_FIXED_CODE_L   (0x0000FFFFu)

Definition at line 575 of file regs.h.

#define FIXED_CODE_L_FIXED_CODE_L_BIT   (0)

Definition at line 577 of file regs.h.

#define FIXED_CODE_L_FIXED_CODE_L_BITS   (16)

Definition at line 578 of file regs.h.

#define FIXED_CODE_L_FIXED_CODE_L_MASK   (0x0000FFFFu)

Definition at line 576 of file regs.h.

#define FIXED_CODE_L_REG   *((volatile int32u *)0x4000103Cu)

Definition at line 571 of file regs.h.

#define FIXED_CODE_L_RESET   (0x00000000u)

Definition at line 573 of file regs.h.

#define FIXED_CODE_L_SHADOW   *((volatile int32u *)0x40001040u)

Definition at line 580 of file regs.h.

#define FIXED_CODE_L_SHADOW_ADDR   (0x40001040u)

Definition at line 582 of file regs.h.

#define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW   (0x0000FFFFu)

Definition at line 585 of file regs.h.

#define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_BIT   (0)

Definition at line 587 of file regs.h.

#define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_BITS   (16)

Definition at line 588 of file regs.h.

#define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_MASK   (0x0000FFFFu)

Definition at line 586 of file regs.h.

#define FIXED_CODE_L_SHADOW_REG   *((volatile int32u *)0x40001040u)

Definition at line 581 of file regs.h.

#define FIXED_CODE_L_SHADOW_RESET   (0x00000000u)

Definition at line 583 of file regs.h.

#define FLASH_ACCESS   *((volatile int32u *)0x40008000u)

Definition at line 2940 of file regs.h.

#define FLASH_ACCESS_ADDR   (0x40008000u)

Definition at line 2942 of file regs.h.

#define FLASH_ACCESS_CODE_LATENCY   (0x00000007u)

Definition at line 2960 of file regs.h.

#define FLASH_ACCESS_CODE_LATENCY_BIT   (0)

Definition at line 2962 of file regs.h.

#define FLASH_ACCESS_CODE_LATENCY_BITS   (3)

Definition at line 2963 of file regs.h.

#define FLASH_ACCESS_CODE_LATENCY_MASK   (0x00000007u)

Definition at line 2961 of file regs.h.

#define FLASH_ACCESS_HALFCYCLE_ACCESS   (0x00000008u)

Definition at line 2955 of file regs.h.

#define FLASH_ACCESS_HALFCYCLE_ACCESS_BIT   (3)

Definition at line 2957 of file regs.h.

#define FLASH_ACCESS_HALFCYCLE_ACCESS_BITS   (1)

Definition at line 2958 of file regs.h.

#define FLASH_ACCESS_HALFCYCLE_ACCESS_MASK   (0x00000008u)

Definition at line 2956 of file regs.h.

#define FLASH_ACCESS_PREFETCH_EN   (0x00000010u)

Definition at line 2950 of file regs.h.

#define FLASH_ACCESS_PREFETCH_EN_BIT   (4)

Definition at line 2952 of file regs.h.

#define FLASH_ACCESS_PREFETCH_EN_BITS   (1)

Definition at line 2953 of file regs.h.

#define FLASH_ACCESS_PREFETCH_EN_MASK   (0x00000010u)

Definition at line 2951 of file regs.h.

#define FLASH_ACCESS_PREFETCH_STATUS   (0x00000020u)

Definition at line 2945 of file regs.h.

#define FLASH_ACCESS_PREFETCH_STATUS_BIT   (5)

Definition at line 2947 of file regs.h.

#define FLASH_ACCESS_PREFETCH_STATUS_BITS   (1)

Definition at line 2948 of file regs.h.

#define FLASH_ACCESS_PREFETCH_STATUS_MASK   (0x00000020u)

Definition at line 2946 of file regs.h.

#define FLASH_ACCESS_REG   *((volatile int32u *)0x40008000u)

Definition at line 2941 of file regs.h.

#define FLASH_ACCESS_RESET   (0x00000031u)

Definition at line 2943 of file regs.h.

#define FLASH_ADDR   *((volatile int32u *)0x40008014u)

Definition at line 3090 of file regs.h.

#define FLASH_ADDR_ADDR   (0x40008014u)

Definition at line 3092 of file regs.h.

#define FLASH_ADDR_FAR   (0xFFFFFFFFu)

Definition at line 3095 of file regs.h.

#define FLASH_ADDR_FAR_BIT   (0)

Definition at line 3097 of file regs.h.

#define FLASH_ADDR_FAR_BITS   (32)

Definition at line 3098 of file regs.h.

#define FLASH_ADDR_FAR_MASK   (0xFFFFFFFFu)

Definition at line 3096 of file regs.h.

#define FLASH_ADDR_REG   *((volatile int32u *)0x40008014u)

Definition at line 3091 of file regs.h.

#define FLASH_ADDR_RESET   (0x00000000u)

Definition at line 3093 of file regs.h.

#define FLASH_CTRL   *((volatile int32u *)0x40008010u)

Definition at line 3020 of file regs.h.

#define FLASH_CTRL_ADDR   (0x40008010u)

Definition at line 3022 of file regs.h.

#define FLASH_CTRL_EARLYBSYIE   (0x00000800u)

Definition at line 3030 of file regs.h.

#define FLASH_CTRL_EARLYBSYIE_BIT   (11)

Definition at line 3032 of file regs.h.

#define FLASH_CTRL_EARLYBSYIE_BITS   (1)

Definition at line 3033 of file regs.h.

#define FLASH_CTRL_EARLYBSYIE_MASK   (0x00000800u)

Definition at line 3031 of file regs.h.

#define FLASH_CTRL_EOPIE   (0x00001000u)

Definition at line 3025 of file regs.h.

#define FLASH_CTRL_EOPIE_BIT   (12)

Definition at line 3027 of file regs.h.

#define FLASH_CTRL_EOPIE_BITS   (1)

Definition at line 3028 of file regs.h.

#define FLASH_CTRL_EOPIE_MASK   (0x00001000u)

Definition at line 3026 of file regs.h.

#define FLASH_CTRL_ERRIE   (0x00000400u)

Definition at line 3035 of file regs.h.

#define FLASH_CTRL_ERRIE_BIT   (10)

Definition at line 3037 of file regs.h.

#define FLASH_CTRL_ERRIE_BITS   (1)

Definition at line 3038 of file regs.h.

#define FLASH_CTRL_ERRIE_MASK   (0x00000400u)

Definition at line 3036 of file regs.h.

#define FLASH_CTRL_FLA_START   (0x00000040u)

Definition at line 3055 of file regs.h.

#define FLASH_CTRL_FLA_START_BIT   (6)

Definition at line 3057 of file regs.h.

#define FLASH_CTRL_FLA_START_BITS   (1)

Definition at line 3058 of file regs.h.

#define FLASH_CTRL_FLA_START_MASK   (0x00000040u)

Definition at line 3056 of file regs.h.

#define FLASH_CTRL_FSTPROG   (0x00000100u)

Definition at line 3045 of file regs.h.

#define FLASH_CTRL_FSTPROG_BIT   (8)

Definition at line 3047 of file regs.h.

#define FLASH_CTRL_FSTPROG_BITS   (1)

Definition at line 3048 of file regs.h.

#define FLASH_CTRL_FSTPROG_MASK   (0x00000100u)

Definition at line 3046 of file regs.h.

#define FLASH_CTRL_GLOBALERASE   (0x00000008u)

Definition at line 3070 of file regs.h.

#define FLASH_CTRL_GLOBALERASE_BIT   (3)

Definition at line 3072 of file regs.h.

#define FLASH_CTRL_GLOBALERASE_BITS   (1)

Definition at line 3073 of file regs.h.

#define FLASH_CTRL_GLOBALERASE_MASK   (0x00000008u)

Definition at line 3071 of file regs.h.

#define FLASH_CTRL_LOCK   (0x00000080u)

Definition at line 3050 of file regs.h.

#define FLASH_CTRL_LOCK_BIT   (7)

Definition at line 3052 of file regs.h.

#define FLASH_CTRL_LOCK_BITS   (1)

Definition at line 3053 of file regs.h.

#define FLASH_CTRL_LOCK_MASK   (0x00000080u)

Definition at line 3051 of file regs.h.

#define FLASH_CTRL_MASSERASE   (0x00000004u)

Definition at line 3075 of file regs.h.

#define FLASH_CTRL_MASSERASE_BIT   (2)

Definition at line 3077 of file regs.h.

#define FLASH_CTRL_MASSERASE_BITS   (1)

Definition at line 3078 of file regs.h.

#define FLASH_CTRL_MASSERASE_MASK   (0x00000004u)

Definition at line 3076 of file regs.h.

#define FLASH_CTRL_OPTERASE   (0x00000020u)

Definition at line 3060 of file regs.h.

#define FLASH_CTRL_OPTERASE_BIT   (5)

Definition at line 3062 of file regs.h.

#define FLASH_CTRL_OPTERASE_BITS   (1)

Definition at line 3063 of file regs.h.

#define FLASH_CTRL_OPTERASE_MASK   (0x00000020u)

Definition at line 3061 of file regs.h.

#define FLASH_CTRL_OPTPROG   (0x00000010u)

Definition at line 3065 of file regs.h.

#define FLASH_CTRL_OPTPROG_BIT   (4)

Definition at line 3067 of file regs.h.

#define FLASH_CTRL_OPTPROG_BITS   (1)

Definition at line 3068 of file regs.h.

#define FLASH_CTRL_OPTPROG_MASK   (0x00000010u)

Definition at line 3066 of file regs.h.

#define FLASH_CTRL_OPTWREN   (0x00000200u)

Definition at line 3040 of file regs.h.

#define FLASH_CTRL_OPTWREN_BIT   (9)

Definition at line 3042 of file regs.h.

#define FLASH_CTRL_OPTWREN_BITS   (1)

Definition at line 3043 of file regs.h.

#define FLASH_CTRL_OPTWREN_MASK   (0x00000200u)

Definition at line 3041 of file regs.h.

#define FLASH_CTRL_PAGEERASE   (0x00000002u)

Definition at line 3080 of file regs.h.

#define FLASH_CTRL_PAGEERASE_BIT   (1)

Definition at line 3082 of file regs.h.

#define FLASH_CTRL_PAGEERASE_BITS   (1)

Definition at line 3083 of file regs.h.

#define FLASH_CTRL_PAGEERASE_MASK   (0x00000002u)

Definition at line 3081 of file regs.h.

#define FLASH_CTRL_PROG   (0x00000001u)

Definition at line 3085 of file regs.h.

#define FLASH_CTRL_PROG_BIT   (0)

Definition at line 3087 of file regs.h.

#define FLASH_CTRL_PROG_BITS   (1)

Definition at line 3088 of file regs.h.

#define FLASH_CTRL_PROG_MASK   (0x00000001u)

Definition at line 3086 of file regs.h.

#define FLASH_CTRL_REG   *((volatile int32u *)0x40008010u)

Definition at line 3021 of file regs.h.

#define FLASH_CTRL_RESET   (0x00000080u)

Definition at line 3023 of file regs.h.

#define FLASH_DATA0   *((volatile int32u *)0x40008084u)

Definition at line 3200 of file regs.h.

#define FLASH_DATA0_ADDR   (0x40008084u)

Definition at line 3202 of file regs.h.

#define FLASH_DATA0_FDR0   (0xFFFFFFFFu)

Definition at line 3205 of file regs.h.

#define FLASH_DATA0_FDR0_BIT   (0)

Definition at line 3207 of file regs.h.

#define FLASH_DATA0_FDR0_BITS   (32)

Definition at line 3208 of file regs.h.

#define FLASH_DATA0_FDR0_MASK   (0xFFFFFFFFu)

Definition at line 3206 of file regs.h.

#define FLASH_DATA0_REG   *((volatile int32u *)0x40008084u)

Definition at line 3201 of file regs.h.

#define FLASH_DATA0_RESET   (0xFFFFFFFFu)

Definition at line 3203 of file regs.h.

#define FLASH_STATUS   *((volatile int32u *)0x4000800Cu)

Definition at line 2985 of file regs.h.

#define FLASH_STATUS_ADDR   (0x4000800Cu)

Definition at line 2987 of file regs.h.

#define FLASH_STATUS_EARLY_BSY   (0x00000002u)

Definition at line 3010 of file regs.h.

#define FLASH_STATUS_EARLY_BSY_BIT   (1)

Definition at line 3012 of file regs.h.

#define FLASH_STATUS_EARLY_BSY_BITS   (1)

Definition at line 3013 of file regs.h.

#define FLASH_STATUS_EARLY_BSY_MASK   (0x00000002u)

Definition at line 3011 of file regs.h.

#define FLASH_STATUS_EOP   (0x00000020u)

Definition at line 2990 of file regs.h.

#define FLASH_STATUS_EOP_BIT   (5)

Definition at line 2992 of file regs.h.

#define FLASH_STATUS_EOP_BITS   (1)

Definition at line 2993 of file regs.h.

#define FLASH_STATUS_EOP_MASK   (0x00000020u)

Definition at line 2991 of file regs.h.

#define FLASH_STATUS_FLA_BSY   (0x00000001u)

Definition at line 3015 of file regs.h.

#define FLASH_STATUS_FLA_BSY_BIT   (0)

Definition at line 3017 of file regs.h.

#define FLASH_STATUS_FLA_BSY_BITS   (1)

Definition at line 3018 of file regs.h.

#define FLASH_STATUS_FLA_BSY_MASK   (0x00000001u)

Definition at line 3016 of file regs.h.

#define FLASH_STATUS_PAGE_PROG_ERR   (0x00000008u)

Definition at line 3000 of file regs.h.

#define FLASH_STATUS_PAGE_PROG_ERR_BIT   (3)

Definition at line 3002 of file regs.h.

#define FLASH_STATUS_PAGE_PROG_ERR_BITS   (1)

Definition at line 3003 of file regs.h.

#define FLASH_STATUS_PAGE_PROG_ERR_MASK   (0x00000008u)

Definition at line 3001 of file regs.h.

#define FLASH_STATUS_PROG_ERR   (0x00000004u)

Definition at line 3005 of file regs.h.

#define FLASH_STATUS_PROG_ERR_BIT   (2)

Definition at line 3007 of file regs.h.

#define FLASH_STATUS_PROG_ERR_BITS   (1)

Definition at line 3008 of file regs.h.

#define FLASH_STATUS_PROG_ERR_MASK   (0x00000004u)

Definition at line 3006 of file regs.h.

#define FLASH_STATUS_REG   *((volatile int32u *)0x4000800Cu)

Definition at line 2986 of file regs.h.

#define FLASH_STATUS_RESET   (0x00000000u)

Definition at line 2988 of file regs.h.

#define FLASH_STATUS_WRP_ERR   (0x00000010u)

Definition at line 2995 of file regs.h.

#define FLASH_STATUS_WRP_ERR_BIT   (4)

Definition at line 2997 of file regs.h.

#define FLASH_STATUS_WRP_ERR_BITS   (1)

Definition at line 2998 of file regs.h.

#define FLASH_STATUS_WRP_ERR_MASK   (0x00000010u)

Definition at line 2996 of file regs.h.

#define FLASH_TEST_CTRL   *((volatile int32u *)0x40008080u)

Definition at line 3135 of file regs.h.

#define FLASH_TEST_CTRL_ADDR   (0x40008080u)

Definition at line 3137 of file regs.h.

#define FLASH_TEST_CTRL_ERASE   (0x00000800u)

Definition at line 3145 of file regs.h.

#define FLASH_TEST_CTRL_ERASE_BIT   (11)

Definition at line 3147 of file regs.h.

#define FLASH_TEST_CTRL_ERASE_BITS   (1)

Definition at line 3148 of file regs.h.

#define FLASH_TEST_CTRL_ERASE_MASK   (0x00000800u)

Definition at line 3146 of file regs.h.

#define FLASH_TEST_CTRL_IFREN   (0x00000040u)

Definition at line 3170 of file regs.h.

#define FLASH_TEST_CTRL_IFREN_BIT   (6)

Definition at line 3172 of file regs.h.

#define FLASH_TEST_CTRL_IFREN_BITS   (1)

Definition at line 3173 of file regs.h.

#define FLASH_TEST_CTRL_IFREN_MASK   (0x00000040u)

Definition at line 3171 of file regs.h.

#define FLASH_TEST_CTRL_MAS1   (0x00000400u)

Definition at line 3150 of file regs.h.

#define FLASH_TEST_CTRL_MAS1_BIT   (10)

Definition at line 3152 of file regs.h.

#define FLASH_TEST_CTRL_MAS1_BITS   (1)

Definition at line 3153 of file regs.h.

#define FLASH_TEST_CTRL_MAS1_MASK   (0x00000400u)

Definition at line 3151 of file regs.h.

#define FLASH_TEST_CTRL_NVSTR   (0x00000100u)

Definition at line 3160 of file regs.h.

#define FLASH_TEST_CTRL_NVSTR_BIT   (8)

Definition at line 3162 of file regs.h.

#define FLASH_TEST_CTRL_NVSTR_BITS   (1)

Definition at line 3163 of file regs.h.

#define FLASH_TEST_CTRL_NVSTR_MASK   (0x00000100u)

Definition at line 3161 of file regs.h.

#define FLASH_TEST_CTRL_REG   *((volatile int32u *)0x40008080u)

Definition at line 3136 of file regs.h.

#define FLASH_TEST_CTRL_RESET   (0x00000000u)

Definition at line 3138 of file regs.h.

#define FLASH_TEST_CTRL_SE   (0x00000080u)

Definition at line 3165 of file regs.h.

#define FLASH_TEST_CTRL_SE_BIT   (7)

Definition at line 3167 of file regs.h.

#define FLASH_TEST_CTRL_SE_BITS   (1)

Definition at line 3168 of file regs.h.

#define FLASH_TEST_CTRL_SE_MASK   (0x00000080u)

Definition at line 3166 of file regs.h.

#define FLASH_TEST_CTRL_SW   (0x00000006u)

Definition at line 3190 of file regs.h.

#define FLASH_TEST_CTRL_SW_BIT   (1)

Definition at line 3192 of file regs.h.

#define FLASH_TEST_CTRL_SW_BITS   (2)

Definition at line 3193 of file regs.h.

#define FLASH_TEST_CTRL_SW_CTRL   (0x00000008u)

Definition at line 3185 of file regs.h.

#define FLASH_TEST_CTRL_SW_CTRL_BIT   (3)

Definition at line 3187 of file regs.h.

#define FLASH_TEST_CTRL_SW_CTRL_BITS   (1)

Definition at line 3188 of file regs.h.

#define FLASH_TEST_CTRL_SW_CTRL_MASK   (0x00000008u)

Definition at line 3186 of file regs.h.

#define FLASH_TEST_CTRL_SW_EN   (0x00000001u)

Definition at line 3195 of file regs.h.

#define FLASH_TEST_CTRL_SW_EN_BIT   (0)

Definition at line 3197 of file regs.h.

#define FLASH_TEST_CTRL_SW_EN_BITS   (1)

Definition at line 3198 of file regs.h.

#define FLASH_TEST_CTRL_SW_EN_MASK   (0x00000001u)

Definition at line 3196 of file regs.h.

#define FLASH_TEST_CTRL_SW_MASK   (0x00000006u)

Definition at line 3191 of file regs.h.

#define FLASH_TEST_CTRL_TEST_PROG   (0x00000200u)

Definition at line 3155 of file regs.h.

#define FLASH_TEST_CTRL_TEST_PROG_BIT   (9)

Definition at line 3157 of file regs.h.

#define FLASH_TEST_CTRL_TEST_PROG_BITS   (1)

Definition at line 3158 of file regs.h.

#define FLASH_TEST_CTRL_TEST_PROG_MASK   (0x00000200u)

Definition at line 3156 of file regs.h.

#define FLASH_TEST_CTRL_TMR   (0x00001000u)

Definition at line 3140 of file regs.h.

#define FLASH_TEST_CTRL_TMR_BIT   (12)

Definition at line 3142 of file regs.h.

#define FLASH_TEST_CTRL_TMR_BITS   (1)

Definition at line 3143 of file regs.h.

#define FLASH_TEST_CTRL_TMR_MASK   (0x00001000u)

Definition at line 3141 of file regs.h.

#define FLASH_TEST_CTRL_XE   (0x00000010u)

Definition at line 3180 of file regs.h.

#define FLASH_TEST_CTRL_XE_BIT   (4)

Definition at line 3182 of file regs.h.

#define FLASH_TEST_CTRL_XE_BITS   (1)

Definition at line 3183 of file regs.h.

#define FLASH_TEST_CTRL_XE_MASK   (0x00000010u)

Definition at line 3181 of file regs.h.

#define FLASH_TEST_CTRL_YE   (0x00000020u)

Definition at line 3175 of file regs.h.

#define FLASH_TEST_CTRL_YE_BIT   (5)

Definition at line 3177 of file regs.h.

#define FLASH_TEST_CTRL_YE_BITS   (1)

Definition at line 3178 of file regs.h.

#define FLASH_TEST_CTRL_YE_MASK   (0x00000020u)

Definition at line 3176 of file regs.h.

#define FPB_CELLID0   *((volatile int32u *)0xE0002FF0u)

Definition at line 9145 of file regs.h.

#define FPB_CELLID0_ADDR   (0xE0002FF0u)

Definition at line 9147 of file regs.h.

#define FPB_CELLID0_CELLID   (0xFFFFFFFFu)

Definition at line 9150 of file regs.h.

#define FPB_CELLID0_CELLID_BIT   (0)

Definition at line 9152 of file regs.h.

#define FPB_CELLID0_CELLID_BITS   (32)

Definition at line 9153 of file regs.h.

#define FPB_CELLID0_CELLID_MASK   (0xFFFFFFFFu)

Definition at line 9151 of file regs.h.

#define FPB_CELLID0_REG   *((volatile int32u *)0xE0002FF0u)

Definition at line 9146 of file regs.h.

#define FPB_CELLID0_RESET   (0x0000000Du)

Definition at line 9148 of file regs.h.

#define FPB_CELLID1   *((volatile int32u *)0xE0002FF4u)

Definition at line 9155 of file regs.h.

#define FPB_CELLID1_ADDR   (0xE0002FF4u)

Definition at line 9157 of file regs.h.

#define FPB_CELLID1_CELLID   (0xFFFFFFFFu)

Definition at line 9160 of file regs.h.

#define FPB_CELLID1_CELLID_BIT   (0)

Definition at line 9162 of file regs.h.

#define FPB_CELLID1_CELLID_BITS   (32)

Definition at line 9163 of file regs.h.

#define FPB_CELLID1_CELLID_MASK   (0xFFFFFFFFu)

Definition at line 9161 of file regs.h.

#define FPB_CELLID1_REG   *((volatile int32u *)0xE0002FF4u)

Definition at line 9156 of file regs.h.

#define FPB_CELLID1_RESET   (0x000000E0u)

Definition at line 9158 of file regs.h.

#define FPB_CELLID2   *((volatile int32u *)0xE0002FF8u)

Definition at line 9165 of file regs.h.

#define FPB_CELLID2_ADDR   (0xE0002FF8u)

Definition at line 9167 of file regs.h.

#define FPB_CELLID2_CELLID   (0xFFFFFFFFu)

Definition at line 9170 of file regs.h.

#define FPB_CELLID2_CELLID_BIT   (0)

Definition at line 9172 of file regs.h.

#define FPB_CELLID2_CELLID_BITS   (32)

Definition at line 9173 of file regs.h.

#define FPB_CELLID2_CELLID_MASK   (0xFFFFFFFFu)

Definition at line 9171 of file regs.h.

#define FPB_CELLID2_REG   *((volatile int32u *)0xE0002FF8u)

Definition at line 9166 of file regs.h.

#define FPB_CELLID2_RESET   (0x00000005u)

Definition at line 9168 of file regs.h.

#define FPB_CELLID3   *((volatile int32u *)0xE0002FFCu)

Definition at line 9175 of file regs.h.

#define FPB_CELLID3_ADDR   (0xE0002FFCu)

Definition at line 9177 of file regs.h.

#define FPB_CELLID3_CELLID   (0xFFFFFFFFu)

Definition at line 9180 of file regs.h.

#define FPB_CELLID3_CELLID_BIT   (0)

Definition at line 9182 of file regs.h.

#define FPB_CELLID3_CELLID_BITS   (32)

Definition at line 9183 of file regs.h.

#define FPB_CELLID3_CELLID_MASK   (0xFFFFFFFFu)

Definition at line 9181 of file regs.h.

#define FPB_CELLID3_REG   *((volatile int32u *)0xE0002FFCu)

Definition at line 9176 of file regs.h.

#define FPB_CELLID3_RESET   (0x000000B1u)

Definition at line 9178 of file regs.h.

#define FPB_COMP0   *((volatile int32u *)0xE0002008u)

Definition at line 8905 of file regs.h.

#define FPB_COMP0_ADDR   (0xE0002008u)

Definition at line 8907 of file regs.h.

#define FPB_COMP0_COMP   (0x1FFFFFFCu)

Definition at line 8915 of file regs.h.

#define FPB_COMP0_COMP_BIT   (2)

Definition at line 8917 of file regs.h.

#define FPB_COMP0_COMP_BITS   (27)

Definition at line 8918 of file regs.h.

#define FPB_COMP0_COMP_MASK   (0x1FFFFFFCu)

Definition at line 8916 of file regs.h.

#define FPB_COMP0_enable   (0x00000001u)

Definition at line 8920 of file regs.h.

#define FPB_COMP0_enable_BIT   (0)

Definition at line 8922 of file regs.h.

#define FPB_COMP0_enable_BITS   (1)

Definition at line 8923 of file regs.h.

#define FPB_COMP0_enable_MASK   (0x00000001u)

Definition at line 8921 of file regs.h.

#define FPB_COMP0_REG   *((volatile int32u *)0xE0002008u)

Definition at line 8906 of file regs.h.

#define FPB_COMP0_REPLACE   (0xC0000000u)

Definition at line 8910 of file regs.h.

#define FPB_COMP0_REPLACE_BIT   (30)

Definition at line 8912 of file regs.h.

#define FPB_COMP0_REPLACE_BITS   (2)

Definition at line 8913 of file regs.h.

#define FPB_COMP0_REPLACE_MASK   (0xC0000000u)

Definition at line 8911 of file regs.h.

#define FPB_COMP0_RESET   (0x00000000u)

Definition at line 8908 of file regs.h.

#define FPB_COMP1   *((volatile int32u *)0xE000200Cu)

Definition at line 8925 of file regs.h.

#define FPB_COMP1_ADDR   (0xE000200Cu)

Definition at line 8927 of file regs.h.

#define FPB_COMP1_COMP   (0x1FFFFFFCu)

Definition at line 8935 of file regs.h.

#define FPB_COMP1_COMP_BIT   (2)

Definition at line 8937 of file regs.h.

#define FPB_COMP1_COMP_BITS   (27)

Definition at line 8938 of file regs.h.

#define FPB_COMP1_COMP_MASK   (0x1FFFFFFCu)

Definition at line 8936 of file regs.h.

#define FPB_COMP1_enable   (0x00000001u)

Definition at line 8940 of file regs.h.

#define FPB_COMP1_enable_BIT   (0)

Definition at line 8942 of file regs.h.

#define FPB_COMP1_enable_BITS   (1)

Definition at line 8943 of file regs.h.

#define FPB_COMP1_enable_MASK   (0x00000001u)

Definition at line 8941 of file regs.h.

#define FPB_COMP1_REG   *((volatile int32u *)0xE000200Cu)

Definition at line 8926 of file regs.h.

#define FPB_COMP1_REPLACE   (0xC0000000u)

Definition at line 8930 of file regs.h.

#define FPB_COMP1_REPLACE_BIT   (30)

Definition at line 8932 of file regs.h.

#define FPB_COMP1_REPLACE_BITS   (2)

Definition at line 8933 of file regs.h.

#define FPB_COMP1_REPLACE_MASK   (0xC0000000u)

Definition at line 8931 of file regs.h.

#define FPB_COMP1_RESET   (0x00000000u)

Definition at line 8928 of file regs.h.

#define FPB_COMP2   *((volatile int32u *)0xE0002010u)

Definition at line 8945 of file regs.h.

#define FPB_COMP2_ADDR   (0xE0002010u)

Definition at line 8947 of file regs.h.

#define FPB_COMP2_COMP   (0x1FFFFFFCu)

Definition at line 8955 of file regs.h.

#define FPB_COMP2_COMP_BIT   (2)

Definition at line 8957 of file regs.h.

#define FPB_COMP2_COMP_BITS   (27)

Definition at line 8958 of file regs.h.

#define FPB_COMP2_COMP_MASK   (0x1FFFFFFCu)

Definition at line 8956 of file regs.h.

#define FPB_COMP2_enable   (0x00000001u)

Definition at line 8960 of file regs.h.

#define FPB_COMP2_enable_BIT   (0)

Definition at line 8962 of file regs.h.

#define FPB_COMP2_enable_BITS   (1)

Definition at line 8963 of file regs.h.

#define FPB_COMP2_enable_MASK   (0x00000001u)

Definition at line 8961 of file regs.h.

#define FPB_COMP2_REG   *((volatile int32u *)0xE0002010u)

Definition at line 8946 of file regs.h.

#define FPB_COMP2_REPLACE   (0xC0000000u)

Definition at line 8950 of file regs.h.

#define FPB_COMP2_REPLACE_BIT   (30)

Definition at line 8952 of file regs.h.

#define FPB_COMP2_REPLACE_BITS   (2)

Definition at line 8953 of file regs.h.

#define FPB_COMP2_REPLACE_MASK   (0xC0000000u)

Definition at line 8951 of file regs.h.

#define FPB_COMP2_RESET   (0x00000000u)

Definition at line 8948 of file regs.h.

#define FPB_COMP3   *((volatile int32u *)0xE0002014u)

Definition at line 8965 of file regs.h.

#define FPB_COMP3_ADDR   (0xE0002014u)

Definition at line 8967 of file regs.h.

#define FPB_COMP3_COMP   (0x1FFFFFFCu)

Definition at line 8975 of file regs.h.

#define FPB_COMP3_COMP_BIT   (2)

Definition at line 8977 of file regs.h.

#define FPB_COMP3_COMP_BITS   (27)

Definition at line 8978 of file regs.h.

#define FPB_COMP3_COMP_MASK   (0x1FFFFFFCu)

Definition at line 8976 of file regs.h.

#define FPB_COMP3_enable   (0x00000001u)

Definition at line 8980 of file regs.h.

#define FPB_COMP3_enable_BIT   (0)

Definition at line 8982 of file regs.h.

#define FPB_COMP3_enable_BITS   (1)

Definition at line 8983 of file regs.h.

#define FPB_COMP3_enable_MASK   (0x00000001u)

Definition at line 8981 of file regs.h.

#define FPB_COMP3_REG   *((volatile int32u *)0xE0002014u)

Definition at line 8966 of file regs.h.

#define FPB_COMP3_REPLACE   (0xC0000000u)

Definition at line 8970 of file regs.h.

#define FPB_COMP3_REPLACE_BIT   (30)

Definition at line 8972 of file regs.h.

#define FPB_COMP3_REPLACE_BITS   (2)

Definition at line 8973 of file regs.h.

#define FPB_COMP3_REPLACE_MASK   (0xC0000000u)

Definition at line 8971 of file regs.h.

#define FPB_COMP3_RESET   (0x00000000u)

Definition at line 8968 of file regs.h.

#define FPB_COMP4   *((volatile int32u *)0xE0002018u)

Definition at line 8985 of file regs.h.

#define FPB_COMP4_ADDR   (0xE0002018u)

Definition at line 8987 of file regs.h.

#define FPB_COMP4_COMP   (0x1FFFFFFCu)

Definition at line 8995 of file regs.h.

#define FPB_COMP4_COMP_BIT   (2)

Definition at line 8997 of file regs.h.

#define FPB_COMP4_COMP_BITS   (27)

Definition at line 8998 of file regs.h.

#define FPB_COMP4_COMP_MASK   (0x1FFFFFFCu)

Definition at line 8996 of file regs.h.

#define FPB_COMP4_enable   (0x00000001u)

Definition at line 9000 of file regs.h.

#define FPB_COMP4_enable_BIT   (0)

Definition at line 9002 of file regs.h.

#define FPB_COMP4_enable_BITS   (1)

Definition at line 9003 of file regs.h.

#define FPB_COMP4_enable_MASK   (0x00000001u)

Definition at line 9001 of file regs.h.

#define FPB_COMP4_REG   *((volatile int32u *)0xE0002018u)

Definition at line 8986 of file regs.h.

#define FPB_COMP4_REPLACE   (0xC0000000u)

Definition at line 8990 of file regs.h.

#define FPB_COMP4_REPLACE_BIT   (30)

Definition at line 8992 of file regs.h.

#define FPB_COMP4_REPLACE_BITS   (2)

Definition at line 8993 of file regs.h.

#define FPB_COMP4_REPLACE_MASK   (0xC0000000u)

Definition at line 8991 of file regs.h.

#define FPB_COMP4_RESET   (0x00000000u)

Definition at line 8988 of file regs.h.

#define FPB_COMP5   *((volatile int32u *)0xE000201Cu)

Definition at line 9005 of file regs.h.

#define FPB_COMP5_ADDR   (0xE000201Cu)

Definition at line 9007 of file regs.h.

#define FPB_COMP5_COMP   (0x1FFFFFFCu)

Definition at line 9015 of file regs.h.

#define FPB_COMP5_COMP_BIT   (2)

Definition at line 9017 of file regs.h.

#define FPB_COMP5_COMP_BITS   (27)

Definition at line 9018 of file regs.h.

#define FPB_COMP5_COMP_MASK   (0x1FFFFFFCu)

Definition at line 9016 of file regs.h.

#define FPB_COMP5_enable   (0x00000001u)

Definition at line 9020 of file regs.h.

#define FPB_COMP5_enable_BIT   (0)

Definition at line 9022 of file regs.h.

#define FPB_COMP5_enable_BITS   (1)

Definition at line 9023 of file regs.h.

#define FPB_COMP5_enable_MASK   (0x00000001u)

Definition at line 9021 of file regs.h.

#define FPB_COMP5_REG   *((volatile int32u *)0xE000201Cu)

Definition at line 9006 of file regs.h.

#define FPB_COMP5_REPLACE   (0xC0000000u)

Definition at line 9010 of file regs.h.

#define FPB_COMP5_REPLACE_BIT   (30)

Definition at line 9012 of file regs.h.

#define FPB_COMP5_REPLACE_BITS   (2)

Definition at line 9013 of file regs.h.

#define FPB_COMP5_REPLACE_MASK   (0xC0000000u)

Definition at line 9011 of file regs.h.

#define FPB_COMP5_RESET   (0x00000000u)

Definition at line 9008 of file regs.h.

#define FPB_COMP6   *((volatile int32u *)0xE0002020u)

Definition at line 9025 of file regs.h.

#define FPB_COMP6_ADDR   (0xE0002020u)

Definition at line 9027 of file regs.h.

#define FPB_COMP6_COMP   (0x1FFFFFFCu)

Definition at line 9035 of file regs.h.

#define FPB_COMP6_COMP_BIT   (2)

Definition at line 9037 of file regs.h.

#define FPB_COMP6_COMP_BITS   (27)

Definition at line 9038 of file regs.h.

#define FPB_COMP6_COMP_MASK   (0x1FFFFFFCu)

Definition at line 9036 of file regs.h.

#define FPB_COMP6_enable   (0x00000001u)

Definition at line 9040 of file regs.h.

#define FPB_COMP6_enable_BIT   (0)

Definition at line 9042 of file regs.h.

#define FPB_COMP6_enable_BITS   (1)

Definition at line 9043 of file regs.h.

#define FPB_COMP6_enable_MASK   (0x00000001u)

Definition at line 9041 of file regs.h.

#define FPB_COMP6_REG   *((volatile int32u *)0xE0002020u)

Definition at line 9026 of file regs.h.

#define FPB_COMP6_REPLACE   (0xC0000000u)

Definition at line 9030 of file regs.h.

#define FPB_COMP6_REPLACE_BIT   (30)

Definition at line 9032 of file regs.h.

#define FPB_COMP6_REPLACE_BITS   (2)

Definition at line 9033 of file regs.h.

#define FPB_COMP6_REPLACE_MASK   (0xC0000000u)

Definition at line 9031 of file regs.h.

#define FPB_COMP6_RESET   (0x00000000u)

Definition at line 9028 of file regs.h.

#define FPB_COMP7   *((volatile int32u *)0xE0002024u)

Definition at line 9045 of file regs.h.

#define FPB_COMP7_ADDR   (0xE0002024u)

Definition at line 9047 of file regs.h.

#define FPB_COMP7_COMP   (0x1FFFFFFCu)

Definition at line 9055 of file regs.h.

#define FPB_COMP7_COMP_BIT   (2)

Definition at line 9057 of file regs.h.

#define FPB_COMP7_COMP_BITS   (27)

Definition at line 9058 of file regs.h.

#define FPB_COMP7_COMP_MASK   (0x1FFFFFFCu)

Definition at line 9056 of file regs.h.

#define FPB_COMP7_enable   (0x00000001u)

Definition at line 9060 of file regs.h.

#define FPB_COMP7_enable_BIT   (0)

Definition at line 9062 of file regs.h.

#define FPB_COMP7_enable_BITS   (1)

Definition at line 9063 of file regs.h.

#define FPB_COMP7_enable_MASK   (0x00000001u)

Definition at line 9061 of file regs.h.

#define FPB_COMP7_REG   *((volatile int32u *)0xE0002024u)

Definition at line 9046 of file regs.h.

#define FPB_COMP7_REPLACE   (0xC0000000u)

Definition at line 9050 of file regs.h.

#define FPB_COMP7_REPLACE_BIT   (30)

Definition at line 9052 of file regs.h.

#define FPB_COMP7_REPLACE_BITS   (2)

Definition at line 9053 of file regs.h.

#define FPB_COMP7_REPLACE_MASK   (0xC0000000u)

Definition at line 9051 of file regs.h.

#define FPB_COMP7_RESET   (0x00000000u)

Definition at line 9048 of file regs.h.

#define FPB_CTRL   *((volatile int32u *)0xE0002000u)

Definition at line 8870 of file regs.h.

#define FPB_CTRL_ADDR   (0xE0002000u)

Definition at line 8872 of file regs.h.

#define FPB_CTRL_enable   (0x00000001u)

Definition at line 8890 of file regs.h.

#define FPB_CTRL_enable_BIT   (0)

Definition at line 8892 of file regs.h.

#define FPB_CTRL_enable_BITS   (1)

Definition at line 8893 of file regs.h.

#define FPB_CTRL_enable_MASK   (0x00000001u)

Definition at line 8891 of file regs.h.

#define FPB_CTRL_KEY   (0x00000002u)

Definition at line 8885 of file regs.h.

#define FPB_CTRL_KEY_BIT   (1)

Definition at line 8887 of file regs.h.

#define FPB_CTRL_KEY_BITS   (1)

Definition at line 8888 of file regs.h.

#define FPB_CTRL_KEY_MASK   (0x00000002u)

Definition at line 8886 of file regs.h.

#define FPB_CTRL_NUM_CODE   (0x000000F0u)

Definition at line 8880 of file regs.h.

#define FPB_CTRL_NUM_CODE_BIT   (4)

Definition at line 8882 of file regs.h.

#define FPB_CTRL_NUM_CODE_BITS   (4)

Definition at line 8883 of file regs.h.

#define FPB_CTRL_NUM_CODE_MASK   (0x000000F0u)

Definition at line 8881 of file regs.h.

#define FPB_CTRL_NUM_LIT   (0x00000F00u)

Definition at line 8875 of file regs.h.

#define FPB_CTRL_NUM_LIT_BIT   (8)

Definition at line 8877 of file regs.h.

#define FPB_CTRL_NUM_LIT_BITS   (4)

Definition at line 8878 of file regs.h.

#define FPB_CTRL_NUM_LIT_MASK   (0x00000F00u)

Definition at line 8876 of file regs.h.

#define FPB_CTRL_REG   *((volatile int32u *)0xE0002000u)

Definition at line 8871 of file regs.h.

#define FPB_CTRL_RESET   (0x00000000u)

Definition at line 8873 of file regs.h.

#define FPB_PERIPHID0   *((volatile int32u *)0xE0002FE0u)

Definition at line 9105 of file regs.h.

#define FPB_PERIPHID0_ADDR   (0xE0002FE0u)

Definition at line 9107 of file regs.h.

#define FPB_PERIPHID0_PERIPHID   (0xFFFFFFFFu)

Definition at line 9110 of file regs.h.

#define FPB_PERIPHID0_PERIPHID_BIT   (0)

Definition at line 9112 of file regs.h.

#define FPB_PERIPHID0_PERIPHID_BITS   (32)

Definition at line 9113 of file regs.h.

#define FPB_PERIPHID0_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 9111 of file regs.h.

#define FPB_PERIPHID0_REG   *((volatile int32u *)0xE0002FE0u)

Definition at line 9106 of file regs.h.

#define FPB_PERIPHID0_RESET   (0x00000003u)

Definition at line 9108 of file regs.h.

#define FPB_PERIPHID1   *((volatile int32u *)0xE0002FE4u)

Definition at line 9115 of file regs.h.

#define FPB_PERIPHID1_ADDR   (0xE0002FE4u)

Definition at line 9117 of file regs.h.

#define FPB_PERIPHID1_PERIPHID   (0xFFFFFFFFu)

Definition at line 9120 of file regs.h.

#define FPB_PERIPHID1_PERIPHID_BIT   (0)

Definition at line 9122 of file regs.h.

#define FPB_PERIPHID1_PERIPHID_BITS   (32)

Definition at line 9123 of file regs.h.

#define FPB_PERIPHID1_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 9121 of file regs.h.

#define FPB_PERIPHID1_REG   *((volatile int32u *)0xE0002FE4u)

Definition at line 9116 of file regs.h.

#define FPB_PERIPHID1_RESET   (0x000000B0u)

Definition at line 9118 of file regs.h.

#define FPB_PERIPHID2   *((volatile int32u *)0xE0002FE8u)

Definition at line 9125 of file regs.h.

#define FPB_PERIPHID2_ADDR   (0xE0002FE8u)

Definition at line 9127 of file regs.h.

#define FPB_PERIPHID2_PERIPHID   (0xFFFFFFFFu)

Definition at line 9130 of file regs.h.

#define FPB_PERIPHID2_PERIPHID_BIT   (0)

Definition at line 9132 of file regs.h.

#define FPB_PERIPHID2_PERIPHID_BITS   (32)

Definition at line 9133 of file regs.h.

#define FPB_PERIPHID2_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 9131 of file regs.h.

#define FPB_PERIPHID2_REG   *((volatile int32u *)0xE0002FE8u)

Definition at line 9126 of file regs.h.

#define FPB_PERIPHID2_RESET   (0x0000000Bu)

Definition at line 9128 of file regs.h.

#define FPB_PERIPHID3   *((volatile int32u *)0xE0002FECu)

Definition at line 9135 of file regs.h.

#define FPB_PERIPHID3_ADDR   (0xE0002FECu)

Definition at line 9137 of file regs.h.

#define FPB_PERIPHID3_PERIPHID   (0xFFFFFFFFu)

Definition at line 9140 of file regs.h.

#define FPB_PERIPHID3_PERIPHID_BIT   (0)

Definition at line 9142 of file regs.h.

#define FPB_PERIPHID3_PERIPHID_BITS   (32)

Definition at line 9143 of file regs.h.

#define FPB_PERIPHID3_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 9141 of file regs.h.

#define FPB_PERIPHID3_REG   *((volatile int32u *)0xE0002FECu)

Definition at line 9136 of file regs.h.

#define FPB_PERIPHID3_RESET   (0x00000000u)

Definition at line 9138 of file regs.h.

#define FPB_PERIPHID4   *((volatile int32u *)0xE0002FD0u)

Definition at line 9065 of file regs.h.

#define FPB_PERIPHID4_ADDR   (0xE0002FD0u)

Definition at line 9067 of file regs.h.

#define FPB_PERIPHID4_PERIPHID   (0xFFFFFFFFu)

Definition at line 9070 of file regs.h.

#define FPB_PERIPHID4_PERIPHID_BIT   (0)

Definition at line 9072 of file regs.h.

#define FPB_PERIPHID4_PERIPHID_BITS   (32)

Definition at line 9073 of file regs.h.

#define FPB_PERIPHID4_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 9071 of file regs.h.

#define FPB_PERIPHID4_REG   *((volatile int32u *)0xE0002FD0u)

Definition at line 9066 of file regs.h.

#define FPB_PERIPHID4_RESET   (0x00000004u)

Definition at line 9068 of file regs.h.

#define FPB_PERIPHID5   *((volatile int32u *)0xE0002FD4u)

Definition at line 9075 of file regs.h.

#define FPB_PERIPHID5_ADDR   (0xE0002FD4u)

Definition at line 9077 of file regs.h.

#define FPB_PERIPHID5_PERIPHID   (0xFFFFFFFFu)

Definition at line 9080 of file regs.h.

#define FPB_PERIPHID5_PERIPHID_BIT   (0)

Definition at line 9082 of file regs.h.

#define FPB_PERIPHID5_PERIPHID_BITS   (32)

Definition at line 9083 of file regs.h.

#define FPB_PERIPHID5_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 9081 of file regs.h.

#define FPB_PERIPHID5_REG   *((volatile int32u *)0xE0002FD4u)

Definition at line 9076 of file regs.h.

#define FPB_PERIPHID5_RESET   (0x00000000u)

Definition at line 9078 of file regs.h.

#define FPB_PERIPHID6   *((volatile int32u *)0xE0002FD8u)

Definition at line 9085 of file regs.h.

#define FPB_PERIPHID6_ADDR   (0xE0002FD8u)

Definition at line 9087 of file regs.h.

#define FPB_PERIPHID6_PERIPHID   (0xFFFFFFFFu)

Definition at line 9090 of file regs.h.

#define FPB_PERIPHID6_PERIPHID_BIT   (0)

Definition at line 9092 of file regs.h.

#define FPB_PERIPHID6_PERIPHID_BITS   (32)

Definition at line 9093 of file regs.h.

#define FPB_PERIPHID6_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 9091 of file regs.h.

#define FPB_PERIPHID6_REG   *((volatile int32u *)0xE0002FD8u)

Definition at line 9086 of file regs.h.

#define FPB_PERIPHID6_RESET   (0x00000000u)

Definition at line 9088 of file regs.h.

#define FPB_PERIPHID7   *((volatile int32u *)0xE0002FDCu)

Definition at line 9095 of file regs.h.

#define FPB_PERIPHID7_ADDR   (0xE0002FDCu)

Definition at line 9097 of file regs.h.

#define FPB_PERIPHID7_PERIPHID   (0xFFFFFFFFu)

Definition at line 9100 of file regs.h.

#define FPB_PERIPHID7_PERIPHID_BIT   (0)

Definition at line 9102 of file regs.h.

#define FPB_PERIPHID7_PERIPHID_BITS   (32)

Definition at line 9103 of file regs.h.

#define FPB_PERIPHID7_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 9101 of file regs.h.

#define FPB_PERIPHID7_REG   *((volatile int32u *)0xE0002FDCu)

Definition at line 9096 of file regs.h.

#define FPB_PERIPHID7_RESET   (0x00000000u)

Definition at line 9098 of file regs.h.

#define FPB_REMAP   *((volatile int32u *)0xE0002004u)

Definition at line 8895 of file regs.h.

#define FPB_REMAP_ADDR   (0xE0002004u)

Definition at line 8897 of file regs.h.

#define FPB_REMAP_REG   *((volatile int32u *)0xE0002004u)

Definition at line 8896 of file regs.h.

#define FPB_REMAP_REMAP   (0x1FFFFFE0u)

Definition at line 8900 of file regs.h.

#define FPB_REMAP_REMAP_BIT   (5)

Definition at line 8902 of file regs.h.

#define FPB_REMAP_REMAP_BITS   (24)

Definition at line 8903 of file regs.h.

#define FPB_REMAP_REMAP_MASK   (0x1FFFFFE0u)

Definition at line 8901 of file regs.h.

#define FPB_REMAP_RESET   (0x20000000u)

Definition at line 8898 of file regs.h.

#define FPEC_CLKACK   (0x00000001u)

Definition at line 2620 of file regs.h.

#define FPEC_CLKACK_BIT   (0)

Definition at line 2622 of file regs.h.

#define FPEC_CLKACK_BITS   (1)

Definition at line 2623 of file regs.h.

#define FPEC_CLKACK_MASK   (0x00000001u)

Definition at line 2621 of file regs.h.

#define FPEC_CLKBSY   (0x00000002u)

Definition at line 2615 of file regs.h.

#define FPEC_CLKBSY_BIT   (1)

Definition at line 2617 of file regs.h.

#define FPEC_CLKBSY_BITS   (1)

Definition at line 2618 of file regs.h.

#define FPEC_CLKBSY_MASK   (0x00000002u)

Definition at line 2616 of file regs.h.

#define FPEC_CLKREQ   *((volatile int32u *)0x4000402Cu)

Definition at line 2600 of file regs.h.

#define FPEC_CLKREQ_ADDR   (0x4000402Cu)

Definition at line 2602 of file regs.h.

#define FPEC_CLKREQ_FIELD   (0x00000001u)

Definition at line 2605 of file regs.h.

#define FPEC_CLKREQ_FIELD_BIT   (0)

Definition at line 2607 of file regs.h.

#define FPEC_CLKREQ_FIELD_BITS   (1)

Definition at line 2608 of file regs.h.

#define FPEC_CLKREQ_FIELD_MASK   (0x00000001u)

Definition at line 2606 of file regs.h.

#define FPEC_CLKREQ_REG   *((volatile int32u *)0x4000402Cu)

Definition at line 2601 of file regs.h.

#define FPEC_CLKREQ_RESET   (0x00000000u)

Definition at line 2603 of file regs.h.

#define FPEC_CLKSTAT   *((volatile int32u *)0x40004030u)

Definition at line 2610 of file regs.h.

#define FPEC_CLKSTAT_ADDR   (0x40004030u)

Definition at line 2612 of file regs.h.

#define FPEC_CLKSTAT_REG   *((volatile int32u *)0x40004030u)

Definition at line 2611 of file regs.h.

#define FPEC_CLKSTAT_RESET   (0x00000000u)

Definition at line 2613 of file regs.h.

#define FPEC_KEY   *((volatile int32u *)0x40008004u)

Definition at line 2965 of file regs.h.

#define FPEC_KEY_ADDR   (0x40008004u)

Definition at line 2967 of file regs.h.

#define FPEC_KEY_FKEYR   (0xFFFFFFFFu)

Definition at line 2970 of file regs.h.

#define FPEC_KEY_FKEYR_BIT   (0)

Definition at line 2972 of file regs.h.

#define FPEC_KEY_FKEYR_BITS   (32)

Definition at line 2973 of file regs.h.

#define FPEC_KEY_FKEYR_MASK   (0xFFFFFFFFu)

Definition at line 2971 of file regs.h.

#define FPEC_KEY_REG   *((volatile int32u *)0x40008004u)

Definition at line 2966 of file regs.h.

#define FPEC_KEY_RESET   (0x00000000u)

Definition at line 2968 of file regs.h.

#define FREQ_MEAS_CTRL1   *((volatile int32u *)0x400010D0u)

Definition at line 1115 of file regs.h.

#define FREQ_MEAS_CTRL1_ADDR   (0x400010D0u)

Definition at line 1117 of file regs.h.

#define FREQ_MEAS_CTRL1_AUTO_TUNE_EN   (0x00008000u)

Definition at line 1120 of file regs.h.

#define FREQ_MEAS_CTRL1_AUTO_TUNE_EN_BIT   (15)

Definition at line 1122 of file regs.h.

#define FREQ_MEAS_CTRL1_AUTO_TUNE_EN_BITS   (1)

Definition at line 1123 of file regs.h.

#define FREQ_MEAS_CTRL1_AUTO_TUNE_EN_MASK   (0x00008000u)

Definition at line 1121 of file regs.h.

#define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB   (0x000001C0u)

Definition at line 1150 of file regs.h.

#define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB_BIT   (6)

Definition at line 1152 of file regs.h.

#define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB_BITS   (3)

Definition at line 1153 of file regs.h.

#define FREQ_MEAS_CTRL1_BIN_SEARCH_MSB_MASK   (0x000001C0u)

Definition at line 1151 of file regs.h.

#define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS   (0x00000200u)

Definition at line 1145 of file regs.h.

#define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS_BIT   (9)

Definition at line 1147 of file regs.h.

#define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS_BITS   (1)

Definition at line 1148 of file regs.h.

#define FREQ_MEAS_CTRL1_DELAY_ALL_MEAS_MASK   (0x00000200u)

Definition at line 1146 of file regs.h.

#define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS   (0x00000400u)

Definition at line 1140 of file regs.h.

#define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS_BIT   (10)

Definition at line 1142 of file regs.h.

#define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS_BITS   (1)

Definition at line 1143 of file regs.h.

#define FREQ_MEAS_CTRL1_DELAY_FIRST_MEAS_MASK   (0x00000400u)

Definition at line 1141 of file regs.h.

#define FREQ_MEAS_CTRL1_FREQ_MEAS_EN   (0x00004000u)

Definition at line 1125 of file regs.h.

#define FREQ_MEAS_CTRL1_FREQ_MEAS_EN_BIT   (14)

Definition at line 1127 of file regs.h.

#define FREQ_MEAS_CTRL1_FREQ_MEAS_EN_BITS   (1)

Definition at line 1128 of file regs.h.

#define FREQ_MEAS_CTRL1_FREQ_MEAS_EN_MASK   (0x00004000u)

Definition at line 1126 of file regs.h.

#define FREQ_MEAS_CTRL1_OPEN_LOOP   (0x00001000u)

Definition at line 1135 of file regs.h.

#define FREQ_MEAS_CTRL1_OPEN_LOOP_BIT   (12)

Definition at line 1137 of file regs.h.

#define FREQ_MEAS_CTRL1_OPEN_LOOP_BITS   (1)

Definition at line 1138 of file regs.h.

#define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL   (0x00002000u)

Definition at line 1130 of file regs.h.

#define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL_BIT   (13)

Definition at line 1132 of file regs.h.

#define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL_BITS   (1)

Definition at line 1133 of file regs.h.

#define FREQ_MEAS_CTRL1_OPEN_LOOP_MANUAL_MASK   (0x00002000u)

Definition at line 1131 of file regs.h.

#define FREQ_MEAS_CTRL1_OPEN_LOOP_MASK   (0x00001000u)

Definition at line 1136 of file regs.h.

#define FREQ_MEAS_CTRL1_REG   *((volatile int32u *)0x400010D0u)

Definition at line 1116 of file regs.h.

#define FREQ_MEAS_CTRL1_RESET   (0x00000160u)

Definition at line 1118 of file regs.h.

#define FREQ_MEAS_CTRL1_TUNE_VCO_INIT   (0x0000003Fu)

Definition at line 1155 of file regs.h.

#define FREQ_MEAS_CTRL1_TUNE_VCO_INIT_BIT   (0)

Definition at line 1157 of file regs.h.

#define FREQ_MEAS_CTRL1_TUNE_VCO_INIT_BITS   (6)

Definition at line 1158 of file regs.h.

#define FREQ_MEAS_CTRL1_TUNE_VCO_INIT_MASK   (0x0000003Fu)

Definition at line 1156 of file regs.h.

#define FREQ_MEAS_CTRL2   *((volatile int32u *)0x400010D4u)

Definition at line 1160 of file regs.h.

#define FREQ_MEAS_CTRL2_ADDR   (0x400010D4u)

Definition at line 1162 of file regs.h.

#define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER   (0x0000FF00u)

Definition at line 1165 of file regs.h.

#define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER_BIT   (8)

Definition at line 1167 of file regs.h.

#define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER_BITS   (8)

Definition at line 1168 of file regs.h.

#define FREQ_MEAS_CTRL2_FREQ_MEAS_TIMER_MASK   (0x0000FF00u)

Definition at line 1166 of file regs.h.

#define FREQ_MEAS_CTRL2_REG   *((volatile int32u *)0x400010D4u)

Definition at line 1161 of file regs.h.

#define FREQ_MEAS_CTRL2_RESET   (0x0000201Eu)

Definition at line 1163 of file regs.h.

#define FREQ_MEAS_CTRL2_TARGET_PERIOD   (0x000000FFu)

Definition at line 1170 of file regs.h.

#define FREQ_MEAS_CTRL2_TARGET_PERIOD_BIT   (0)

Definition at line 1172 of file regs.h.

#define FREQ_MEAS_CTRL2_TARGET_PERIOD_BITS   (8)

Definition at line 1173 of file regs.h.

#define FREQ_MEAS_CTRL2_TARGET_PERIOD_MASK   (0x000000FFu)

Definition at line 1171 of file regs.h.

#define FREQ_MEAS_SHIFT   *((volatile int32u *)0x400010D8u)

Definition at line 1175 of file regs.h.

#define FREQ_MEAS_SHIFT_ADDR   (0x400010D8u)

Definition at line 1177 of file regs.h.

#define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT   (0x000000FFu)

Definition at line 1180 of file regs.h.

#define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_BIT   (0)

Definition at line 1182 of file regs.h.

#define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_BITS   (8)

Definition at line 1183 of file regs.h.

#define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_MASK   (0x000000FFu)

Definition at line 1181 of file regs.h.

#define FREQ_MEAS_SHIFT_REG   *((volatile int32u *)0x400010D8u)

Definition at line 1176 of file regs.h.

#define FREQ_MEAS_SHIFT_RESET   (0x00000035u)

Definition at line 1178 of file regs.h.

#define FREQ_MEAS_STATUS1   *((volatile int32u *)0x400010DCu)

Definition at line 1185 of file regs.h.

#define FREQ_MEAS_STATUS1_ADDR   (0x400010DCu)

Definition at line 1187 of file regs.h.

#define FREQ_MEAS_STATUS1_FREQ_SIGN   (0x00002000u)

Definition at line 1200 of file regs.h.

#define FREQ_MEAS_STATUS1_FREQ_SIGN_BIT   (13)

Definition at line 1202 of file regs.h.

#define FREQ_MEAS_STATUS1_FREQ_SIGN_BITS   (1)

Definition at line 1203 of file regs.h.

#define FREQ_MEAS_STATUS1_FREQ_SIGN_MASK   (0x00002000u)

Definition at line 1201 of file regs.h.

#define FREQ_MEAS_STATUS1_INVALID_EDGE   (0x00008000u)

Definition at line 1190 of file regs.h.

#define FREQ_MEAS_STATUS1_INVALID_EDGE_BIT   (15)

Definition at line 1192 of file regs.h.

#define FREQ_MEAS_STATUS1_INVALID_EDGE_BITS   (1)

Definition at line 1193 of file regs.h.

#define FREQ_MEAS_STATUS1_INVALID_EDGE_MASK   (0x00008000u)

Definition at line 1191 of file regs.h.

#define FREQ_MEAS_STATUS1_NEAREST_DIFF   (0x000003FFu)

Definition at line 1210 of file regs.h.

#define FREQ_MEAS_STATUS1_NEAREST_DIFF_BIT   (0)

Definition at line 1212 of file regs.h.

#define FREQ_MEAS_STATUS1_NEAREST_DIFF_BITS   (10)

Definition at line 1213 of file regs.h.

#define FREQ_MEAS_STATUS1_NEAREST_DIFF_MASK   (0x000003FFu)

Definition at line 1211 of file regs.h.

#define FREQ_MEAS_STATUS1_PERIOD_FOUND   (0x00001000u)

Definition at line 1205 of file regs.h.

#define FREQ_MEAS_STATUS1_PERIOD_FOUND_BIT   (12)

Definition at line 1207 of file regs.h.

#define FREQ_MEAS_STATUS1_PERIOD_FOUND_BITS   (1)

Definition at line 1208 of file regs.h.

#define FREQ_MEAS_STATUS1_PERIOD_FOUND_MASK   (0x00001000u)

Definition at line 1206 of file regs.h.

#define FREQ_MEAS_STATUS1_REG   *((volatile int32u *)0x400010DCu)

Definition at line 1186 of file regs.h.

#define FREQ_MEAS_STATUS1_RESET   (0x00000000u)

Definition at line 1188 of file regs.h.

#define FREQ_MEAS_STATUS1_SIGN_FOUND   (0x00004000u)

Definition at line 1195 of file regs.h.

#define FREQ_MEAS_STATUS1_SIGN_FOUND_BIT   (14)

Definition at line 1197 of file regs.h.

#define FREQ_MEAS_STATUS1_SIGN_FOUND_BITS   (1)

Definition at line 1198 of file regs.h.

#define FREQ_MEAS_STATUS1_SIGN_FOUND_MASK   (0x00004000u)

Definition at line 1196 of file regs.h.

#define FREQ_MEAS_STATUS2   *((volatile int32u *)0x400010E0u)

Definition at line 1215 of file regs.h.

#define FREQ_MEAS_STATUS2_ADDR   (0x400010E0u)

Definition at line 1217 of file regs.h.

#define FREQ_MEAS_STATUS2_BEAT_TIMER   (0x0000FFC0u)

Definition at line 1220 of file regs.h.

#define FREQ_MEAS_STATUS2_BEAT_TIMER_BIT   (6)

Definition at line 1222 of file regs.h.

#define FREQ_MEAS_STATUS2_BEAT_TIMER_BITS   (10)

Definition at line 1223 of file regs.h.

#define FREQ_MEAS_STATUS2_BEAT_TIMER_MASK   (0x0000FFC0u)

Definition at line 1221 of file regs.h.

#define FREQ_MEAS_STATUS2_BEATS   (0x0000003Fu)

Definition at line 1225 of file regs.h.

#define FREQ_MEAS_STATUS2_BEATS_BIT   (0)

Definition at line 1227 of file regs.h.

#define FREQ_MEAS_STATUS2_BEATS_BITS   (6)

Definition at line 1228 of file regs.h.

#define FREQ_MEAS_STATUS2_BEATS_MASK   (0x0000003Fu)

Definition at line 1226 of file regs.h.

#define FREQ_MEAS_STATUS2_REG   *((volatile int32u *)0x400010E0u)

Definition at line 1216 of file regs.h.

#define FREQ_MEAS_STATUS2_RESET   (0x00000000u)

Definition at line 1218 of file regs.h.

#define FREQ_MEAS_STATUS3   *((volatile int32u *)0x400010E4u)

Definition at line 1230 of file regs.h.

#define FREQ_MEAS_STATUS3_ADDR   (0x400010E4u)

Definition at line 1232 of file regs.h.

#define FREQ_MEAS_STATUS3_REG   *((volatile int32u *)0x400010E4u)

Definition at line 1231 of file regs.h.

#define FREQ_MEAS_STATUS3_RESET   (0x00000020u)

Definition at line 1233 of file regs.h.

#define FREQ_MEAS_STATUS3_TUNE_VCO   (0x0000003Fu)

Definition at line 1235 of file regs.h.

#define FREQ_MEAS_STATUS3_TUNE_VCO_BIT   (0)

Definition at line 1237 of file regs.h.

#define FREQ_MEAS_STATUS3_TUNE_VCO_BITS   (6)

Definition at line 1238 of file regs.h.

#define FREQ_MEAS_STATUS3_TUNE_VCO_MASK   (0x0000003Fu)

Definition at line 1236 of file regs.h.

#define GAIN_CTRL_MAX_RF   *((volatile int32u *)0x400010A8u)

Definition at line 1000 of file regs.h.

#define GAIN_CTRL_MAX_RF_ADDR   (0x400010A8u)

Definition at line 1002 of file regs.h.

#define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF   (0x000001FFu)

Definition at line 1005 of file regs.h.

#define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_BIT   (0)

Definition at line 1007 of file regs.h.

#define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_BITS   (9)

Definition at line 1008 of file regs.h.

#define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_MASK   (0x000001FFu)

Definition at line 1006 of file regs.h.

#define GAIN_CTRL_MAX_RF_REG   *((volatile int32u *)0x400010A8u)

Definition at line 1001 of file regs.h.

#define GAIN_CTRL_MAX_RF_RESET   (0x000000FCu)

Definition at line 1003 of file regs.h.

#define GAIN_CTRL_MIN_RF   *((volatile int32u *)0x400010A4u)

Definition at line 990 of file regs.h.

#define GAIN_CTRL_MIN_RF_ADDR   (0x400010A4u)

Definition at line 992 of file regs.h.

#define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF   (0x000001FFu)

Definition at line 995 of file regs.h.

#define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_BIT   (0)

Definition at line 997 of file regs.h.

#define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_BITS   (9)

Definition at line 998 of file regs.h.

#define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_MASK   (0x000001FFu)

Definition at line 996 of file regs.h.

#define GAIN_CTRL_MIN_RF_REG   *((volatile int32u *)0x400010A4u)

Definition at line 991 of file regs.h.

#define GAIN_CTRL_MIN_RF_RESET   (0x000000F0u)

Definition at line 993 of file regs.h.

#define GAIN_SETTING_0   *((volatile int32u *)0x40001074u)

Definition at line 750 of file regs.h.

#define GAIN_SETTING_0_ADDR   (0x40001074u)

Definition at line 752 of file regs.h.

#define GAIN_SETTING_0_REG   *((volatile int32u *)0x40001074u)

Definition at line 751 of file regs.h.

#define GAIN_SETTING_0_RESET   (0x00000000u)

Definition at line 753 of file regs.h.

#define GAIN_SETTING_0_RX_FILTER_GAIN_0   (0x00000030u)

Definition at line 760 of file regs.h.

#define GAIN_SETTING_0_RX_FILTER_GAIN_0_BIT   (4)

Definition at line 762 of file regs.h.

#define GAIN_SETTING_0_RX_FILTER_GAIN_0_BITS   (2)

Definition at line 763 of file regs.h.

#define GAIN_SETTING_0_RX_FILTER_GAIN_0_MASK   (0x00000030u)

Definition at line 761 of file regs.h.

#define GAIN_SETTING_0_RX_IF_GAIN_0   (0x0000000Fu)

Definition at line 765 of file regs.h.

#define GAIN_SETTING_0_RX_IF_GAIN_0_BIT   (0)

Definition at line 767 of file regs.h.

#define GAIN_SETTING_0_RX_IF_GAIN_0_BITS   (4)

Definition at line 768 of file regs.h.

#define GAIN_SETTING_0_RX_IF_GAIN_0_MASK   (0x0000000Fu)

Definition at line 766 of file regs.h.

#define GAIN_SETTING_0_RX_MIXER_GAIN_0   (0x00000040u)

Definition at line 755 of file regs.h.

#define GAIN_SETTING_0_RX_MIXER_GAIN_0_BIT   (6)

Definition at line 757 of file regs.h.

#define GAIN_SETTING_0_RX_MIXER_GAIN_0_BITS   (1)

Definition at line 758 of file regs.h.

#define GAIN_SETTING_0_RX_MIXER_GAIN_0_MASK   (0x00000040u)

Definition at line 756 of file regs.h.

#define GAIN_SETTING_1   *((volatile int32u *)0x40001078u)

Definition at line 770 of file regs.h.

#define GAIN_SETTING_10   *((volatile int32u *)0x4000109Cu)

Definition at line 950 of file regs.h.

#define GAIN_SETTING_10_ADDR   (0x4000109Cu)

Definition at line 952 of file regs.h.

#define GAIN_SETTING_10_REG   *((volatile int32u *)0x4000109Cu)

Definition at line 951 of file regs.h.

#define GAIN_SETTING_10_RESET   (0x00000077u)

Definition at line 953 of file regs.h.

#define GAIN_SETTING_10_RX_FILTER_GAIN_10   (0x00000030u)

Definition at line 960 of file regs.h.

#define GAIN_SETTING_10_RX_FILTER_GAIN_10_BIT   (4)

Definition at line 962 of file regs.h.

#define GAIN_SETTING_10_RX_FILTER_GAIN_10_BITS   (2)

Definition at line 963 of file regs.h.

#define GAIN_SETTING_10_RX_FILTER_GAIN_10_MASK   (0x00000030u)

Definition at line 961 of file regs.h.

#define GAIN_SETTING_10_RX_IF_GAIN_10   (0x0000000Fu)

Definition at line 965 of file regs.h.

#define GAIN_SETTING_10_RX_IF_GAIN_10_BIT   (0)

Definition at line 967 of file regs.h.

#define GAIN_SETTING_10_RX_IF_GAIN_10_BITS   (4)

Definition at line 968 of file regs.h.

#define GAIN_SETTING_10_RX_IF_GAIN_10_MASK   (0x0000000Fu)

Definition at line 966 of file regs.h.

#define GAIN_SETTING_10_RX_MIXER_GAIN_10   (0x00000040u)

Definition at line 955 of file regs.h.

#define GAIN_SETTING_10_RX_MIXER_GAIN_10_BIT   (6)

Definition at line 957 of file regs.h.

#define GAIN_SETTING_10_RX_MIXER_GAIN_10_BITS   (1)

Definition at line 958 of file regs.h.

#define GAIN_SETTING_10_RX_MIXER_GAIN_10_MASK   (0x00000040u)

Definition at line 956 of file regs.h.

#define GAIN_SETTING_11   *((volatile int32u *)0x400010A0u)

Definition at line 970 of file regs.h.

#define GAIN_SETTING_11_ADDR   (0x400010A0u)

Definition at line 972 of file regs.h.

#define GAIN_SETTING_11_REG   *((volatile int32u *)0x400010A0u)

Definition at line 971 of file regs.h.

#define GAIN_SETTING_11_RESET   (0x00000078u)

Definition at line 973 of file regs.h.

#define GAIN_SETTING_11_RX_FILTER_GAIN_11   (0x00000030u)

Definition at line 980 of file regs.h.

#define GAIN_SETTING_11_RX_FILTER_GAIN_11_BIT   (4)

Definition at line 982 of file regs.h.

#define GAIN_SETTING_11_RX_FILTER_GAIN_11_BITS   (2)

Definition at line 983 of file regs.h.

#define GAIN_SETTING_11_RX_FILTER_GAIN_11_MASK   (0x00000030u)

Definition at line 981 of file regs.h.

#define GAIN_SETTING_11_RX_IF_GAIN_11   (0x0000000Fu)

Definition at line 985 of file regs.h.

#define GAIN_SETTING_11_RX_IF_GAIN_11_BIT   (0)

Definition at line 987 of file regs.h.

#define GAIN_SETTING_11_RX_IF_GAIN_11_BITS   (4)

Definition at line 988 of file regs.h.

#define GAIN_SETTING_11_RX_IF_GAIN_11_MASK   (0x0000000Fu)

Definition at line 986 of file regs.h.

#define GAIN_SETTING_11_RX_MIXER_GAIN_11   (0x00000040u)

Definition at line 975 of file regs.h.

#define GAIN_SETTING_11_RX_MIXER_GAIN_11_BIT   (6)

Definition at line 977 of file regs.h.

#define GAIN_SETTING_11_RX_MIXER_GAIN_11_BITS   (1)

Definition at line 978 of file regs.h.

#define GAIN_SETTING_11_RX_MIXER_GAIN_11_MASK   (0x00000040u)

Definition at line 976 of file regs.h.

#define GAIN_SETTING_1_ADDR   (0x40001078u)

Definition at line 772 of file regs.h.

#define GAIN_SETTING_1_REG   *((volatile int32u *)0x40001078u)

Definition at line 771 of file regs.h.

#define GAIN_SETTING_1_RESET   (0x00000010u)

Definition at line 773 of file regs.h.

#define GAIN_SETTING_1_RX_FILTER_GAIN_1   (0x00000030u)

Definition at line 780 of file regs.h.

#define GAIN_SETTING_1_RX_FILTER_GAIN_1_BIT   (4)

Definition at line 782 of file regs.h.

#define GAIN_SETTING_1_RX_FILTER_GAIN_1_BITS   (2)

Definition at line 783 of file regs.h.

#define GAIN_SETTING_1_RX_FILTER_GAIN_1_MASK   (0x00000030u)

Definition at line 781 of file regs.h.

#define GAIN_SETTING_1_RX_IF_GAIN_1   (0x0000000Fu)

Definition at line 785 of file regs.h.

#define GAIN_SETTING_1_RX_IF_GAIN_1_BIT   (0)

Definition at line 787 of file regs.h.

#define GAIN_SETTING_1_RX_IF_GAIN_1_BITS   (4)

Definition at line 788 of file regs.h.

#define GAIN_SETTING_1_RX_IF_GAIN_1_MASK   (0x0000000Fu)

Definition at line 786 of file regs.h.

#define GAIN_SETTING_1_RX_MIXER_GAIN_1   (0x00000040u)

Definition at line 775 of file regs.h.

#define GAIN_SETTING_1_RX_MIXER_GAIN_1_BIT   (6)

Definition at line 777 of file regs.h.

#define GAIN_SETTING_1_RX_MIXER_GAIN_1_BITS   (1)

Definition at line 778 of file regs.h.

#define GAIN_SETTING_1_RX_MIXER_GAIN_1_MASK   (0x00000040u)

Definition at line 776 of file regs.h.

#define GAIN_SETTING_2   *((volatile int32u *)0x4000107Cu)

Definition at line 790 of file regs.h.

#define GAIN_SETTING_2_ADDR   (0x4000107Cu)

Definition at line 792 of file regs.h.

#define GAIN_SETTING_2_REG   *((volatile int32u *)0x4000107Cu)

Definition at line 791 of file regs.h.

#define GAIN_SETTING_2_RESET   (0x00000030u)

Definition at line 793 of file regs.h.

#define GAIN_SETTING_2_RX_FILTER_GAIN_2   (0x00000030u)

Definition at line 800 of file regs.h.

#define GAIN_SETTING_2_RX_FILTER_GAIN_2_BIT   (4)

Definition at line 802 of file regs.h.

#define GAIN_SETTING_2_RX_FILTER_GAIN_2_BITS   (2)

Definition at line 803 of file regs.h.

#define GAIN_SETTING_2_RX_FILTER_GAIN_2_MASK   (0x00000030u)

Definition at line 801 of file regs.h.

#define GAIN_SETTING_2_RX_IF_GAIN_2   (0x0000000Fu)

Definition at line 805 of file regs.h.

#define GAIN_SETTING_2_RX_IF_GAIN_2_BIT   (0)

Definition at line 807 of file regs.h.

#define GAIN_SETTING_2_RX_IF_GAIN_2_BITS   (4)

Definition at line 808 of file regs.h.

#define GAIN_SETTING_2_RX_IF_GAIN_2_MASK   (0x0000000Fu)

Definition at line 806 of file regs.h.

#define GAIN_SETTING_2_RX_MIXER_GAIN_2   (0x00000040u)

Definition at line 795 of file regs.h.

#define GAIN_SETTING_2_RX_MIXER_GAIN_2_BIT   (6)

Definition at line 797 of file regs.h.

#define GAIN_SETTING_2_RX_MIXER_GAIN_2_BITS   (1)

Definition at line 798 of file regs.h.

#define GAIN_SETTING_2_RX_MIXER_GAIN_2_MASK   (0x00000040u)

Definition at line 796 of file regs.h.

#define GAIN_SETTING_3   *((volatile int32u *)0x40001080u)

Definition at line 810 of file regs.h.

#define GAIN_SETTING_3_ADDR   (0x40001080u)

Definition at line 812 of file regs.h.

#define GAIN_SETTING_3_REG   *((volatile int32u *)0x40001080u)

Definition at line 811 of file regs.h.

#define GAIN_SETTING_3_RESET   (0x00000031u)

Definition at line 813 of file regs.h.

#define GAIN_SETTING_3_RX_FILTER_GAIN_3   (0x00000030u)

Definition at line 820 of file regs.h.

#define GAIN_SETTING_3_RX_FILTER_GAIN_3_BIT   (4)

Definition at line 822 of file regs.h.

#define GAIN_SETTING_3_RX_FILTER_GAIN_3_BITS   (2)

Definition at line 823 of file regs.h.

#define GAIN_SETTING_3_RX_FILTER_GAIN_3_MASK   (0x00000030u)

Definition at line 821 of file regs.h.

#define GAIN_SETTING_3_RX_IF_GAIN_3   (0x0000000Fu)

Definition at line 825 of file regs.h.

#define GAIN_SETTING_3_RX_IF_GAIN_3_BIT   (0)

Definition at line 827 of file regs.h.

#define GAIN_SETTING_3_RX_IF_GAIN_3_BITS   (4)

Definition at line 828 of file regs.h.

#define GAIN_SETTING_3_RX_IF_GAIN_3_MASK   (0x0000000Fu)

Definition at line 826 of file regs.h.

#define GAIN_SETTING_3_RX_MIXER_GAIN_3   (0x00000040u)

Definition at line 815 of file regs.h.

#define GAIN_SETTING_3_RX_MIXER_GAIN_3_BIT   (6)

Definition at line 817 of file regs.h.

#define GAIN_SETTING_3_RX_MIXER_GAIN_3_BITS   (1)

Definition at line 818 of file regs.h.

#define GAIN_SETTING_3_RX_MIXER_GAIN_3_MASK   (0x00000040u)

Definition at line 816 of file regs.h.

#define GAIN_SETTING_4   *((volatile int32u *)0x40001084u)

Definition at line 830 of file regs.h.

#define GAIN_SETTING_4_ADDR   (0x40001084u)

Definition at line 832 of file regs.h.

#define GAIN_SETTING_4_REG   *((volatile int32u *)0x40001084u)

Definition at line 831 of file regs.h.

#define GAIN_SETTING_4_RESET   (0x00000032u)

Definition at line 833 of file regs.h.

#define GAIN_SETTING_4_RX_FILTER_GAIN_4   (0x00000030u)

Definition at line 840 of file regs.h.

#define GAIN_SETTING_4_RX_FILTER_GAIN_4_BIT   (4)

Definition at line 842 of file regs.h.

#define GAIN_SETTING_4_RX_FILTER_GAIN_4_BITS   (2)

Definition at line 843 of file regs.h.

#define GAIN_SETTING_4_RX_FILTER_GAIN_4_MASK   (0x00000030u)

Definition at line 841 of file regs.h.

#define GAIN_SETTING_4_RX_IF_GAIN_4   (0x0000000Fu)

Definition at line 845 of file regs.h.

#define GAIN_SETTING_4_RX_IF_GAIN_4_BIT   (0)

Definition at line 847 of file regs.h.

#define GAIN_SETTING_4_RX_IF_GAIN_4_BITS   (4)

Definition at line 848 of file regs.h.

#define GAIN_SETTING_4_RX_IF_GAIN_4_MASK   (0x0000000Fu)

Definition at line 846 of file regs.h.

#define GAIN_SETTING_4_RX_MIXER_GAIN_4   (0x00000040u)

Definition at line 835 of file regs.h.

#define GAIN_SETTING_4_RX_MIXER_GAIN_4_BIT   (6)

Definition at line 837 of file regs.h.

#define GAIN_SETTING_4_RX_MIXER_GAIN_4_BITS   (1)

Definition at line 838 of file regs.h.

#define GAIN_SETTING_4_RX_MIXER_GAIN_4_MASK   (0x00000040u)

Definition at line 836 of file regs.h.

#define GAIN_SETTING_5   *((volatile int32u *)0x40001088u)

Definition at line 850 of file regs.h.

#define GAIN_SETTING_5_ADDR   (0x40001088u)

Definition at line 852 of file regs.h.

#define GAIN_SETTING_5_REG   *((volatile int32u *)0x40001088u)

Definition at line 851 of file regs.h.

#define GAIN_SETTING_5_RESET   (0x00000033u)

Definition at line 853 of file regs.h.

#define GAIN_SETTING_5_RX_FILTER_GAIN_5   (0x00000030u)

Definition at line 860 of file regs.h.

#define GAIN_SETTING_5_RX_FILTER_GAIN_5_BIT   (4)

Definition at line 862 of file regs.h.

#define GAIN_SETTING_5_RX_FILTER_GAIN_5_BITS   (2)

Definition at line 863 of file regs.h.

#define GAIN_SETTING_5_RX_FILTER_GAIN_5_MASK   (0x00000030u)

Definition at line 861 of file regs.h.

#define GAIN_SETTING_5_RX_IF_GAIN_5   (0x0000000Fu)

Definition at line 865 of file regs.h.

#define GAIN_SETTING_5_RX_IF_GAIN_5_BIT   (0)

Definition at line 867 of file regs.h.

#define GAIN_SETTING_5_RX_IF_GAIN_5_BITS   (4)

Definition at line 868 of file regs.h.

#define GAIN_SETTING_5_RX_IF_GAIN_5_MASK   (0x0000000Fu)

Definition at line 866 of file regs.h.

#define GAIN_SETTING_5_RX_MIXER_GAIN_5   (0x00000040u)

Definition at line 855 of file regs.h.

#define GAIN_SETTING_5_RX_MIXER_GAIN_5_BIT   (6)

Definition at line 857 of file regs.h.

#define GAIN_SETTING_5_RX_MIXER_GAIN_5_BITS   (1)

Definition at line 858 of file regs.h.

#define GAIN_SETTING_5_RX_MIXER_GAIN_5_MASK   (0x00000040u)

Definition at line 856 of file regs.h.

#define GAIN_SETTING_6   *((volatile int32u *)0x4000108Cu)

Definition at line 870 of file regs.h.

#define GAIN_SETTING_6_ADDR   (0x4000108Cu)

Definition at line 872 of file regs.h.

#define GAIN_SETTING_6_REG   *((volatile int32u *)0x4000108Cu)

Definition at line 871 of file regs.h.

#define GAIN_SETTING_6_RESET   (0x00000034u)

Definition at line 873 of file regs.h.

#define GAIN_SETTING_6_RX_FILTER_GAIN_6   (0x00000030u)

Definition at line 880 of file regs.h.

#define GAIN_SETTING_6_RX_FILTER_GAIN_6_BIT   (4)

Definition at line 882 of file regs.h.

#define GAIN_SETTING_6_RX_FILTER_GAIN_6_BITS   (2)

Definition at line 883 of file regs.h.

#define GAIN_SETTING_6_RX_FILTER_GAIN_6_MASK   (0x00000030u)

Definition at line 881 of file regs.h.

#define GAIN_SETTING_6_RX_IF_GAIN_6   (0x0000000Fu)

Definition at line 885 of file regs.h.

#define GAIN_SETTING_6_RX_IF_GAIN_6_BIT   (0)

Definition at line 887 of file regs.h.

#define GAIN_SETTING_6_RX_IF_GAIN_6_BITS   (4)

Definition at line 888 of file regs.h.

#define GAIN_SETTING_6_RX_IF_GAIN_6_MASK   (0x0000000Fu)

Definition at line 886 of file regs.h.

#define GAIN_SETTING_6_RX_MIXER_GAIN_6   (0x00000040u)

Definition at line 875 of file regs.h.

#define GAIN_SETTING_6_RX_MIXER_GAIN_6_BIT   (6)

Definition at line 877 of file regs.h.

#define GAIN_SETTING_6_RX_MIXER_GAIN_6_BITS   (1)

Definition at line 878 of file regs.h.

#define GAIN_SETTING_6_RX_MIXER_GAIN_6_MASK   (0x00000040u)

Definition at line 876 of file regs.h.

#define GAIN_SETTING_7   *((volatile int32u *)0x40001090u)

Definition at line 890 of file regs.h.

#define GAIN_SETTING_7_ADDR   (0x40001090u)

Definition at line 892 of file regs.h.

#define GAIN_SETTING_7_REG   *((volatile int32u *)0x40001090u)

Definition at line 891 of file regs.h.

#define GAIN_SETTING_7_RESET   (0x00000035u)

Definition at line 893 of file regs.h.

#define GAIN_SETTING_7_RX_FILTER_GAIN_7   (0x00000030u)

Definition at line 900 of file regs.h.

#define GAIN_SETTING_7_RX_FILTER_GAIN_7_BIT   (4)

Definition at line 902 of file regs.h.

#define GAIN_SETTING_7_RX_FILTER_GAIN_7_BITS   (2)

Definition at line 903 of file regs.h.

#define GAIN_SETTING_7_RX_FILTER_GAIN_7_MASK   (0x00000030u)

Definition at line 901 of file regs.h.

#define GAIN_SETTING_7_RX_IF_GAIN_7   (0x0000000Fu)

Definition at line 905 of file regs.h.

#define GAIN_SETTING_7_RX_IF_GAIN_7_BIT   (0)

Definition at line 907 of file regs.h.

#define GAIN_SETTING_7_RX_IF_GAIN_7_BITS   (4)

Definition at line 908 of file regs.h.

#define GAIN_SETTING_7_RX_IF_GAIN_7_MASK   (0x0000000Fu)

Definition at line 906 of file regs.h.

#define GAIN_SETTING_7_RX_MIXER_GAIN_7   (0x00000040u)

Definition at line 895 of file regs.h.

#define GAIN_SETTING_7_RX_MIXER_GAIN_7_BIT   (6)

Definition at line 897 of file regs.h.

#define GAIN_SETTING_7_RX_MIXER_GAIN_7_BITS   (1)

Definition at line 898 of file regs.h.

#define GAIN_SETTING_7_RX_MIXER_GAIN_7_MASK   (0x00000040u)

Definition at line 896 of file regs.h.

#define GAIN_SETTING_8   *((volatile int32u *)0x40001094u)

Definition at line 910 of file regs.h.

#define GAIN_SETTING_8_ADDR   (0x40001094u)

Definition at line 912 of file regs.h.

#define GAIN_SETTING_8_REG   *((volatile int32u *)0x40001094u)

Definition at line 911 of file regs.h.

#define GAIN_SETTING_8_RESET   (0x00000036u)

Definition at line 913 of file regs.h.

#define GAIN_SETTING_8_RX_FILTER_GAIN_8   (0x00000030u)

Definition at line 920 of file regs.h.

#define GAIN_SETTING_8_RX_FILTER_GAIN_8_BIT   (4)

Definition at line 922 of file regs.h.

#define GAIN_SETTING_8_RX_FILTER_GAIN_8_BITS   (2)

Definition at line 923 of file regs.h.

#define GAIN_SETTING_8_RX_FILTER_GAIN_8_MASK   (0x00000030u)

Definition at line 921 of file regs.h.

#define GAIN_SETTING_8_RX_IF_GAIN_8   (0x0000000Fu)

Definition at line 925 of file regs.h.

#define GAIN_SETTING_8_RX_IF_GAIN_8_BIT   (0)

Definition at line 927 of file regs.h.

#define GAIN_SETTING_8_RX_IF_GAIN_8_BITS   (4)

Definition at line 928 of file regs.h.

#define GAIN_SETTING_8_RX_IF_GAIN_8_MASK   (0x0000000Fu)

Definition at line 926 of file regs.h.

#define GAIN_SETTING_8_RX_MIXER_GAIN_8   (0x00000040u)

Definition at line 915 of file regs.h.

#define GAIN_SETTING_8_RX_MIXER_GAIN_8_BIT   (6)

Definition at line 917 of file regs.h.

#define GAIN_SETTING_8_RX_MIXER_GAIN_8_BITS   (1)

Definition at line 918 of file regs.h.

#define GAIN_SETTING_8_RX_MIXER_GAIN_8_MASK   (0x00000040u)

Definition at line 916 of file regs.h.

#define GAIN_SETTING_9   *((volatile int32u *)0x40001098u)

Definition at line 930 of file regs.h.

#define GAIN_SETTING_9_ADDR   (0x40001098u)

Definition at line 932 of file regs.h.

#define GAIN_SETTING_9_REG   *((volatile int32u *)0x40001098u)

Definition at line 931 of file regs.h.

#define GAIN_SETTING_9_RESET   (0x00000076u)

Definition at line 933 of file regs.h.

#define GAIN_SETTING_9_RX_FILTER_GAIN_9   (0x00000030u)

Definition at line 940 of file regs.h.

#define GAIN_SETTING_9_RX_FILTER_GAIN_9_BIT   (4)

Definition at line 942 of file regs.h.

#define GAIN_SETTING_9_RX_FILTER_GAIN_9_BITS   (2)

Definition at line 943 of file regs.h.

#define GAIN_SETTING_9_RX_FILTER_GAIN_9_MASK   (0x00000030u)

Definition at line 941 of file regs.h.

#define GAIN_SETTING_9_RX_IF_GAIN_9   (0x0000000Fu)

Definition at line 945 of file regs.h.

#define GAIN_SETTING_9_RX_IF_GAIN_9_BIT   (0)

Definition at line 947 of file regs.h.

#define GAIN_SETTING_9_RX_IF_GAIN_9_BITS   (4)

Definition at line 948 of file regs.h.

#define GAIN_SETTING_9_RX_IF_GAIN_9_MASK   (0x0000000Fu)

Definition at line 946 of file regs.h.

#define GAIN_SETTING_9_RX_MIXER_GAIN_9   (0x00000040u)

Definition at line 935 of file regs.h.

#define GAIN_SETTING_9_RX_MIXER_GAIN_9_BIT   (6)

Definition at line 937 of file regs.h.

#define GAIN_SETTING_9_RX_MIXER_GAIN_9_BITS   (1)

Definition at line 938 of file regs.h.

#define GAIN_SETTING_9_RX_MIXER_GAIN_9_MASK   (0x00000040u)

Definition at line 936 of file regs.h.

#define GAIN_THRESH_MAX   *((volatile int32u *)0x40001068u)

Definition at line 720 of file regs.h.

#define GAIN_THRESH_MAX_ADDR   (0x40001068u)

Definition at line 722 of file regs.h.

#define GAIN_THRESH_MAX_GAIN_THRESH_MAX   (0x000000FFu)

Definition at line 725 of file regs.h.

#define GAIN_THRESH_MAX_GAIN_THRESH_MAX_BIT   (0)

Definition at line 727 of file regs.h.

#define GAIN_THRESH_MAX_GAIN_THRESH_MAX_BITS   (8)

Definition at line 728 of file regs.h.

#define GAIN_THRESH_MAX_GAIN_THRESH_MAX_MASK   (0x000000FFu)

Definition at line 726 of file regs.h.

#define GAIN_THRESH_MAX_REG   *((volatile int32u *)0x40001068u)

Definition at line 721 of file regs.h.

#define GAIN_THRESH_MAX_RESET   (0x00000060u)

Definition at line 723 of file regs.h.

#define GAIN_THRESH_MID   *((volatile int32u *)0x4000106Cu)

Definition at line 730 of file regs.h.

#define GAIN_THRESH_MID_ADDR   (0x4000106Cu)

Definition at line 732 of file regs.h.

#define GAIN_THRESH_MID_GAIN_THRESH_MID   (0x000000FFu)

Definition at line 735 of file regs.h.

#define GAIN_THRESH_MID_GAIN_THRESH_MID_BIT   (0)

Definition at line 737 of file regs.h.

#define GAIN_THRESH_MID_GAIN_THRESH_MID_BITS   (8)

Definition at line 738 of file regs.h.

#define GAIN_THRESH_MID_GAIN_THRESH_MID_MASK   (0x000000FFu)

Definition at line 736 of file regs.h.

#define GAIN_THRESH_MID_REG   *((volatile int32u *)0x4000106Cu)

Definition at line 731 of file regs.h.

#define GAIN_THRESH_MID_RESET   (0x00000030u)

Definition at line 733 of file regs.h.

#define GAIN_THRESH_MIN   *((volatile int32u *)0x40001070u)

Definition at line 740 of file regs.h.

#define GAIN_THRESH_MIN_ADDR   (0x40001070u)

Definition at line 742 of file regs.h.

#define GAIN_THRESH_MIN_GAIN_THRESH_MIN   (0x000000FFu)

Definition at line 745 of file regs.h.

#define GAIN_THRESH_MIN_GAIN_THRESH_MIN_BIT   (0)

Definition at line 747 of file regs.h.

#define GAIN_THRESH_MIN_GAIN_THRESH_MIN_BITS   (8)

Definition at line 748 of file regs.h.

#define GAIN_THRESH_MIN_GAIN_THRESH_MIN_MASK   (0x000000FFu)

Definition at line 746 of file regs.h.

#define GAIN_THRESH_MIN_REG   *((volatile int32u *)0x40001070u)

Definition at line 741 of file regs.h.

#define GAIN_THRESH_MIN_RESET   (0x00000018u)

Definition at line 743 of file regs.h.

#define GPIO_BOOTMODE   (0x00000008u)

Definition at line 5301 of file regs.h.

#define GPIO_BOOTMODE_BIT   (3)

Definition at line 5303 of file regs.h.

#define GPIO_BOOTMODE_BITS   (1)

Definition at line 5304 of file regs.h.

#define GPIO_BOOTMODE_MASK   (0x00000008u)

Definition at line 5302 of file regs.h.

#define GPIO_DBGCFG   *((volatile int32u *)0x4000BC00u)

Definition at line 5276 of file regs.h.

#define GPIO_DBGCFG_ADDR   (0x4000BC00u)

Definition at line 5278 of file regs.h.

#define GPIO_DBGCFG_REG   *((volatile int32u *)0x4000BC00u)

Definition at line 5277 of file regs.h.

#define GPIO_DBGCFG_RESET   (0x00000010u)

Definition at line 5279 of file regs.h.

#define GPIO_DBGCFGRSVD   (0x00000008u)

Definition at line 5291 of file regs.h.

#define GPIO_DBGCFGRSVD_BIT   (3)

Definition at line 5293 of file regs.h.

#define GPIO_DBGCFGRSVD_BITS   (1)

Definition at line 5294 of file regs.h.

#define GPIO_DBGCFGRSVD_MASK   (0x00000008u)

Definition at line 5292 of file regs.h.

#define GPIO_DBGSTAT   *((volatile int32u *)0x4000BC04u)

Definition at line 5296 of file regs.h.

#define GPIO_DBGSTAT_ADDR   (0x4000BC04u)

Definition at line 5298 of file regs.h.

#define GPIO_DBGSTAT_REG   *((volatile int32u *)0x4000BC04u)

Definition at line 5297 of file regs.h.

#define GPIO_DBGSTAT_RESET   (0x00000000u)

Definition at line 5299 of file regs.h.

#define GPIO_DEBUGDIS   (0x00000020u)

Definition at line 5281 of file regs.h.

#define GPIO_DEBUGDIS_BIT   (5)

Definition at line 5283 of file regs.h.

#define GPIO_DEBUGDIS_BITS   (1)

Definition at line 5284 of file regs.h.

#define GPIO_DEBUGDIS_MASK   (0x00000020u)

Definition at line 5282 of file regs.h.

#define GPIO_EXTREGEN   (0x00000010u)

Definition at line 5286 of file regs.h.

#define GPIO_EXTREGEN_BIT   (4)

Definition at line 5288 of file regs.h.

#define GPIO_EXTREGEN_BITS   (1)

Definition at line 5289 of file regs.h.

#define GPIO_EXTREGEN_MASK   (0x00000010u)

Definition at line 5287 of file regs.h.

#define GPIO_FORCEDBG   (0x00000002u)

Definition at line 5306 of file regs.h.

#define GPIO_FORCEDBG_BIT   (1)

Definition at line 5308 of file regs.h.

#define GPIO_FORCEDBG_BITS   (1)

Definition at line 5309 of file regs.h.

#define GPIO_FORCEDBG_MASK   (0x00000002u)

Definition at line 5307 of file regs.h.

#define GPIO_INTCFGA   *((volatile int32u *)0x4000A860u)

Definition at line 4495 of file regs.h.

#define GPIO_INTCFGA_ADDR   (0x4000A860u)

Definition at line 4497 of file regs.h.

#define GPIO_INTCFGA_REG   *((volatile int32u *)0x4000A860u)

Definition at line 4496 of file regs.h.

#define GPIO_INTCFGA_RESET   (0x00000000u)

Definition at line 4498 of file regs.h.

#define GPIO_INTCFGB   *((volatile int32u *)0x4000A864u)

Definition at line 4510 of file regs.h.

#define GPIO_INTCFGB_ADDR   (0x4000A864u)

Definition at line 4512 of file regs.h.

#define GPIO_INTCFGB_REG   *((volatile int32u *)0x4000A864u)

Definition at line 4511 of file regs.h.

#define GPIO_INTCFGB_RESET   (0x00000000u)

Definition at line 4513 of file regs.h.

#define GPIO_INTCFGC   *((volatile int32u *)0x4000A868u)

Definition at line 4525 of file regs.h.

#define GPIO_INTCFGC_ADDR   (0x4000A868u)

Definition at line 4527 of file regs.h.

#define GPIO_INTCFGC_REG   *((volatile int32u *)0x4000A868u)

Definition at line 4526 of file regs.h.

#define GPIO_INTCFGC_RESET   (0x00000000u)

Definition at line 4528 of file regs.h.

#define GPIO_INTCFGD   *((volatile int32u *)0x4000A86Cu)

Definition at line 4540 of file regs.h.

#define GPIO_INTCFGD_ADDR   (0x4000A86Cu)

Definition at line 4542 of file regs.h.

#define GPIO_INTCFGD_REG   *((volatile int32u *)0x4000A86Cu)

Definition at line 4541 of file regs.h.

#define GPIO_INTCFGD_RESET   (0x00000000u)

Definition at line 4543 of file regs.h.

#define GPIO_INTFILT   (0x00000100u)

Definition at line 4545 of file regs.h.

#define GPIO_INTFILT   (0x00000100u)

Definition at line 4545 of file regs.h.

#define GPIO_INTFILT   (0x00000100u)

Definition at line 4545 of file regs.h.

#define GPIO_INTFILT   (0x00000100u)

Definition at line 4545 of file regs.h.

#define GPIO_INTFILT_BIT   (8)

Definition at line 4547 of file regs.h.

#define GPIO_INTFILT_BIT   (8)

Definition at line 4547 of file regs.h.

#define GPIO_INTFILT_BIT   (8)

Definition at line 4547 of file regs.h.

#define GPIO_INTFILT_BIT   (8)

Definition at line 4547 of file regs.h.

#define GPIO_INTFILT_BITS   (1)

Definition at line 4548 of file regs.h.

#define GPIO_INTFILT_BITS   (1)

Definition at line 4548 of file regs.h.

#define GPIO_INTFILT_BITS   (1)

Definition at line 4548 of file regs.h.

#define GPIO_INTFILT_BITS   (1)

Definition at line 4548 of file regs.h.

#define GPIO_INTFILT_MASK   (0x00000100u)

Definition at line 4546 of file regs.h.

#define GPIO_INTFILT_MASK   (0x00000100u)

Definition at line 4546 of file regs.h.

#define GPIO_INTFILT_MASK   (0x00000100u)

Definition at line 4546 of file regs.h.

#define GPIO_INTFILT_MASK   (0x00000100u)

Definition at line 4546 of file regs.h.

#define GPIO_INTMOD   (0x000000E0u)

Definition at line 4550 of file regs.h.

#define GPIO_INTMOD   (0x000000E0u)

Definition at line 4550 of file regs.h.

#define GPIO_INTMOD   (0x000000E0u)

Definition at line 4550 of file regs.h.

#define GPIO_INTMOD   (0x000000E0u)

Definition at line 4550 of file regs.h.

#define GPIO_INTMOD_BIT   (5)

Definition at line 4552 of file regs.h.

#define GPIO_INTMOD_BIT   (5)

Definition at line 4552 of file regs.h.

#define GPIO_INTMOD_BIT   (5)

Definition at line 4552 of file regs.h.

#define GPIO_INTMOD_BIT   (5)

Definition at line 4552 of file regs.h.

#define GPIO_INTMOD_BITS   (3)

Definition at line 4553 of file regs.h.

#define GPIO_INTMOD_BITS   (3)

Definition at line 4553 of file regs.h.

#define GPIO_INTMOD_BITS   (3)

Definition at line 4553 of file regs.h.

#define GPIO_INTMOD_BITS   (3)

Definition at line 4553 of file regs.h.

#define GPIO_INTMOD_MASK   (0x000000E0u)

Definition at line 4551 of file regs.h.

#define GPIO_INTMOD_MASK   (0x000000E0u)

Definition at line 4551 of file regs.h.

#define GPIO_INTMOD_MASK   (0x000000E0u)

Definition at line 4551 of file regs.h.

#define GPIO_INTMOD_MASK   (0x000000E0u)

Definition at line 4551 of file regs.h.

#define GPIO_IRQCSEL   *((volatile int32u *)0x4000BC14u)

Definition at line 5451 of file regs.h.

#define GPIO_IRQCSEL_ADDR   (0x4000BC14u)

Definition at line 5453 of file regs.h.

#define GPIO_IRQCSEL_REG   *((volatile int32u *)0x4000BC14u)

Definition at line 5452 of file regs.h.

#define GPIO_IRQCSEL_RESET   (0x0000000Fu)

Definition at line 5454 of file regs.h.

#define GPIO_IRQDSEL   *((volatile int32u *)0x4000BC18u)

Definition at line 5461 of file regs.h.

#define GPIO_IRQDSEL_ADDR   (0x4000BC18u)

Definition at line 5463 of file regs.h.

#define GPIO_IRQDSEL_REG   *((volatile int32u *)0x4000BC18u)

Definition at line 5462 of file regs.h.

#define GPIO_IRQDSEL_RESET   (0x00000010u)

Definition at line 5464 of file regs.h.

#define GPIO_PACFGH   *((volatile int32u *)0x4000B004u)

Definition at line 4593 of file regs.h.

#define GPIO_PACFGH_ADDR   (0x4000B004u)

Definition at line 4595 of file regs.h.

#define GPIO_PACFGH_REG   *((volatile int32u *)0x4000B004u)

Definition at line 4594 of file regs.h.

#define GPIO_PACFGH_RESET   (0x00004444u)

Definition at line 4596 of file regs.h.

#define GPIO_PACFGL   *((volatile int32u *)0x4000B000u)

Definition at line 4560 of file regs.h.

#define GPIO_PACFGL_ADDR   (0x4000B000u)

Definition at line 4562 of file regs.h.

#define GPIO_PACFGL_REG   *((volatile int32u *)0x4000B000u)

Definition at line 4561 of file regs.h.

#define GPIO_PACFGL_RESET   (0x00004444u)

Definition at line 4563 of file regs.h.

#define GPIO_PACLR   *((volatile int32u *)0x4000B014u)

Definition at line 4761 of file regs.h.

#define GPIO_PACLR_ADDR   (0x4000B014u)

Definition at line 4763 of file regs.h.

#define GPIO_PACLR_REG   *((volatile int32u *)0x4000B014u)

Definition at line 4762 of file regs.h.

#define GPIO_PACLR_RESET   (0x00000000u)

Definition at line 4764 of file regs.h.

#define GPIO_PAIN   *((volatile int32u *)0x4000B008u)

Definition at line 4618 of file regs.h.

#define GPIO_PAIN_ADDR   (0x4000B008u)

Definition at line 4620 of file regs.h.

#define GPIO_PAIN_REG   *((volatile int32u *)0x4000B008u)

Definition at line 4619 of file regs.h.

#define GPIO_PAIN_RESET   (0x00000000u)

Definition at line 4621 of file regs.h.

#define GPIO_PAOUT   *((volatile int32u *)0x4000B00Cu)

Definition at line 4663 of file regs.h.

#define GPIO_PAOUT_ADDR   (0x4000B00Cu)

Definition at line 4665 of file regs.h.

#define GPIO_PAOUT_REG   *((volatile int32u *)0x4000B00Cu)

Definition at line 4664 of file regs.h.

#define GPIO_PAOUT_RESET   (0x00000000u)

Definition at line 4666 of file regs.h.

#define GPIO_PASET   *((volatile int32u *)0x4000B010u)

Definition at line 4711 of file regs.h.

#define GPIO_PASET_ADDR   (0x4000B010u)

Definition at line 4713 of file regs.h.

#define GPIO_PASET_REG   *((volatile int32u *)0x4000B010u)

Definition at line 4712 of file regs.h.

#define GPIO_PASET_RESET   (0x00000000u)

Definition at line 4714 of file regs.h.

#define GPIO_PAWAKE   *((volatile int32u *)0x4000BC08u)

Definition at line 5316 of file regs.h.

#define GPIO_PAWAKE_ADDR   (0x4000BC08u)

Definition at line 5318 of file regs.h.

#define GPIO_PAWAKE_REG   *((volatile int32u *)0x4000BC08u)

Definition at line 5317 of file regs.h.

#define GPIO_PAWAKE_RESET   (0x00000000u)

Definition at line 5319 of file regs.h.

#define GPIO_PBCFGH   *((volatile int32u *)0x4000B404u)

Definition at line 4831 of file regs.h.

#define GPIO_PBCFGH_ADDR   (0x4000B404u)

Definition at line 4833 of file regs.h.

#define GPIO_PBCFGH_REG   *((volatile int32u *)0x4000B404u)

Definition at line 4832 of file regs.h.

#define GPIO_PBCFGH_RESET   (0x00004444u)

Definition at line 4834 of file regs.h.

#define GPIO_PBCFGL   *((volatile int32u *)0x4000B400u)

Definition at line 4806 of file regs.h.

#define GPIO_PBCFGL_ADDR   (0x4000B400u)

Definition at line 4808 of file regs.h.

#define GPIO_PBCFGL_REG   *((volatile int32u *)0x4000B400u)

Definition at line 4807 of file regs.h.

#define GPIO_PBCFGL_RESET   (0x00004444u)

Definition at line 4809 of file regs.h.

#define GPIO_PBCLR   *((volatile int32u *)0x4000B414u)

Definition at line 4996 of file regs.h.

#define GPIO_PBCLR_ADDR   (0x4000B414u)

Definition at line 4998 of file regs.h.

#define GPIO_PBCLR_REG   *((volatile int32u *)0x4000B414u)

Definition at line 4997 of file regs.h.

#define GPIO_PBCLR_RESET   (0x00000000u)

Definition at line 4999 of file regs.h.

#define GPIO_PBIN   *((volatile int32u *)0x4000B408u)

Definition at line 4856 of file regs.h.

#define GPIO_PBIN_ADDR   (0x4000B408u)

Definition at line 4858 of file regs.h.

#define GPIO_PBIN_REG   *((volatile int32u *)0x4000B408u)

Definition at line 4857 of file regs.h.

#define GPIO_PBIN_RESET   (0x00000000u)

Definition at line 4859 of file regs.h.

#define GPIO_PBOUT   *((volatile int32u *)0x4000B40Cu)

Definition at line 4901 of file regs.h.

#define GPIO_PBOUT_ADDR   (0x4000B40Cu)

Definition at line 4903 of file regs.h.

#define GPIO_PBOUT_REG   *((volatile int32u *)0x4000B40Cu)

Definition at line 4902 of file regs.h.

#define GPIO_PBOUT_RESET   (0x00000000u)

Definition at line 4904 of file regs.h.

#define GPIO_PBSET   *((volatile int32u *)0x4000B410u)

Definition at line 4946 of file regs.h.

#define GPIO_PBSET_ADDR   (0x4000B410u)

Definition at line 4948 of file regs.h.

#define GPIO_PBSET_REG   *((volatile int32u *)0x4000B410u)

Definition at line 4947 of file regs.h.

#define GPIO_PBSET_RESET   (0x00000000u)

Definition at line 4949 of file regs.h.

#define GPIO_PBWAKE   *((volatile int32u *)0x4000BC0Cu)

Definition at line 5361 of file regs.h.

#define GPIO_PBWAKE_ADDR   (0x4000BC0Cu)

Definition at line 5363 of file regs.h.

#define GPIO_PBWAKE_REG   *((volatile int32u *)0x4000BC0Cu)

Definition at line 5362 of file regs.h.

#define GPIO_PBWAKE_RESET   (0x00000000u)

Definition at line 5364 of file regs.h.

#define GPIO_PCCFGH   *((volatile int32u *)0x4000B804u)

Definition at line 5066 of file regs.h.

#define GPIO_PCCFGH_ADDR   (0x4000B804u)

Definition at line 5068 of file regs.h.

#define GPIO_PCCFGH_REG   *((volatile int32u *)0x4000B804u)

Definition at line 5067 of file regs.h.

#define GPIO_PCCFGH_RESET   (0x00004444u)

Definition at line 5069 of file regs.h.

#define GPIO_PCCFGL   *((volatile int32u *)0x4000B800u)

Definition at line 5041 of file regs.h.

#define GPIO_PCCFGL_ADDR   (0x4000B800u)

Definition at line 5043 of file regs.h.

#define GPIO_PCCFGL_REG   *((volatile int32u *)0x4000B800u)

Definition at line 5042 of file regs.h.

#define GPIO_PCCFGL_RESET   (0x00004444u)

Definition at line 5044 of file regs.h.

#define GPIO_PCCLR   *((volatile int32u *)0x4000B814u)

Definition at line 5231 of file regs.h.

#define GPIO_PCCLR_ADDR   (0x4000B814u)

Definition at line 5233 of file regs.h.

#define GPIO_PCCLR_REG   *((volatile int32u *)0x4000B814u)

Definition at line 5232 of file regs.h.

#define GPIO_PCCLR_RESET   (0x00000000u)

Definition at line 5234 of file regs.h.

#define GPIO_PCIN   *((volatile int32u *)0x4000B808u)

Definition at line 5091 of file regs.h.

#define GPIO_PCIN_ADDR   (0x4000B808u)

Definition at line 5093 of file regs.h.

#define GPIO_PCIN_REG   *((volatile int32u *)0x4000B808u)

Definition at line 5092 of file regs.h.

#define GPIO_PCIN_RESET   (0x00000000u)

Definition at line 5094 of file regs.h.

#define GPIO_PCOUT   *((volatile int32u *)0x4000B80Cu)

Definition at line 5136 of file regs.h.

#define GPIO_PCOUT_ADDR   (0x4000B80Cu)

Definition at line 5138 of file regs.h.

#define GPIO_PCOUT_REG   *((volatile int32u *)0x4000B80Cu)

Definition at line 5137 of file regs.h.

#define GPIO_PCOUT_RESET   (0x00000000u)

Definition at line 5139 of file regs.h.

#define GPIO_PCSET   *((volatile int32u *)0x4000B810u)

Definition at line 5181 of file regs.h.

#define GPIO_PCSET_ADDR   (0x4000B810u)

Definition at line 5183 of file regs.h.

#define GPIO_PCSET_REG   *((volatile int32u *)0x4000B810u)

Definition at line 5182 of file regs.h.

#define GPIO_PCSET_RESET   (0x00000000u)

Definition at line 5184 of file regs.h.

#define GPIO_PCWAKE   *((volatile int32u *)0x4000BC10u)

Definition at line 5406 of file regs.h.

#define GPIO_PCWAKE_ADDR   (0x4000BC10u)

Definition at line 5408 of file regs.h.

#define GPIO_PCWAKE_REG   *((volatile int32u *)0x4000BC10u)

Definition at line 5407 of file regs.h.

#define GPIO_PCWAKE_RESET   (0x00000000u)

Definition at line 5409 of file regs.h.

#define GPIO_PXSETRSVD   (0x0000FF00u)

Definition at line 5186 of file regs.h.

#define GPIO_PXSETRSVD   (0x0000FF00u)

Definition at line 5186 of file regs.h.

#define GPIO_PXSETRSVD   (0x0000FF00u)

Definition at line 5186 of file regs.h.

#define GPIO_PXSETRSVD_BIT   (8)

Definition at line 5188 of file regs.h.

#define GPIO_PXSETRSVD_BIT   (8)

Definition at line 5188 of file regs.h.

#define GPIO_PXSETRSVD_BIT   (8)

Definition at line 5188 of file regs.h.

#define GPIO_PXSETRSVD_BITS   (8)

Definition at line 5189 of file regs.h.

#define GPIO_PXSETRSVD_BITS   (8)

Definition at line 5189 of file regs.h.

#define GPIO_PXSETRSVD_BITS   (8)

Definition at line 5189 of file regs.h.

#define GPIO_PXSETRSVD_MASK   (0x0000FF00u)

Definition at line 5187 of file regs.h.

#define GPIO_PXSETRSVD_MASK   (0x0000FF00u)

Definition at line 5187 of file regs.h.

#define GPIO_PXSETRSVD_MASK   (0x0000FF00u)

Definition at line 5187 of file regs.h.

#define GPIO_SWEN   (0x00000001u)

Definition at line 5311 of file regs.h.

#define GPIO_SWEN_BIT   (0)

Definition at line 5313 of file regs.h.

#define GPIO_SWEN_BITS   (1)

Definition at line 5314 of file regs.h.

#define GPIO_SWEN_MASK   (0x00000001u)

Definition at line 5312 of file regs.h.

#define GPIO_WAKE   (0x00000001u)

Definition at line 205 of file regs.h.

#define GPIO_WAKE_BIT   (0)

Definition at line 207 of file regs.h.

#define GPIO_WAKE_BITS   (1)

Definition at line 208 of file regs.h.

#define GPIO_WAKE_FILTER   (0x00000001u)

Definition at line 5491 of file regs.h.

#define GPIO_WAKE_FILTER_BIT   (0)

Definition at line 5493 of file regs.h.

#define GPIO_WAKE_FILTER_BITS   (1)

Definition at line 5494 of file regs.h.

#define GPIO_WAKE_FILTER_MASK   (0x00000001u)

Definition at line 5492 of file regs.h.

#define GPIO_WAKE_MASK   (0x00000001u)

Definition at line 206 of file regs.h.

#define GPIO_WAKEFILT   *((volatile int32u *)0x4000BC1Cu)

Definition at line 5471 of file regs.h.

#define GPIO_WAKEFILT_ADDR   (0x4000BC1Cu)

Definition at line 5473 of file regs.h.

#define GPIO_WAKEFILT_REG   *((volatile int32u *)0x4000BC1Cu)

Definition at line 5472 of file regs.h.

#define GPIO_WAKEFILT_RESET   (0x00000000u)

Definition at line 5474 of file regs.h.

#define GPIOCFG_ANALOG   (0x0u)

Definition at line 4589 of file regs.h.

#define GPIOCFG_IN   (0x4u)

Definition at line 4590 of file regs.h.

#define GPIOCFG_IN_PUD   (0x8u)

Definition at line 4591 of file regs.h.

#define GPIOCFG_OUT   (0x1u)

Definition at line 4585 of file regs.h.

#define GPIOCFG_OUT_ALT   (0x9u)

Definition at line 4587 of file regs.h.

#define GPIOCFG_OUT_ALT_OD   (0xDu)

Definition at line 4588 of file regs.h.

#define GPIOCFG_OUT_OD   (0x5u)

Definition at line 4586 of file regs.h.

#define GPIOOUT_PULLDOWN   (0x0u)

Definition at line 4709 of file regs.h.

#define GPIOOUT_PULLUP   (0x1u)

Definition at line 4708 of file regs.h.

#define HV_SPARE   *((volatile int32u *)0x40000000u)

Definition at line 40 of file regs.h.

#define HV_SPARE_ADDR   (0x40000000u)

Definition at line 42 of file regs.h.

#define HV_SPARE_HV_SPARE   (0x000000FFu)

Definition at line 45 of file regs.h.

#define HV_SPARE_HV_SPARE_BIT   (0)

Definition at line 47 of file regs.h.

#define HV_SPARE_HV_SPARE_BITS   (8)

Definition at line 48 of file regs.h.

#define HV_SPARE_HV_SPARE_MASK   (0x000000FFu)

Definition at line 46 of file regs.h.

#define HV_SPARE_REG   *((volatile int32u *)0x40000000u)

Definition at line 41 of file regs.h.

#define HV_SPARE_RESET   (0x00000000u)

Definition at line 43 of file regs.h.

#define I_AM_AN_EMULATOR   *((volatile int32u *)0x40009000u)

Definition at line 3215 of file regs.h.

#define I_AM_AN_EMULATOR_ADDR   (0x40009000u)

Definition at line 3217 of file regs.h.

#define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR   (0x00000001u)

Definition at line 3220 of file regs.h.

#define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_BIT   (0)

Definition at line 3222 of file regs.h.

#define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_BITS   (1)

Definition at line 3223 of file regs.h.

#define I_AM_AN_EMULATOR_I_AM_AN_EMULATOR_MASK   (0x00000001u)

Definition at line 3221 of file regs.h.

#define I_AM_AN_EMULATOR_REG   *((volatile int32u *)0x40009000u)

Definition at line 3216 of file regs.h.

#define I_AM_AN_EMULATOR_RESET   (0x00000000u)

Definition at line 3218 of file regs.h.

#define IF_FREQ   *((volatile int32u *)0x40001024u)

Definition at line 500 of file regs.h.

#define IF_FREQ_ADDR   (0x40001024u)

Definition at line 502 of file regs.h.

#define IF_FREQ_IF_FREQ   (0x000001FFu)

Definition at line 510 of file regs.h.

#define IF_FREQ_IF_FREQ_BIT   (0)

Definition at line 512 of file regs.h.

#define IF_FREQ_IF_FREQ_BITS   (9)

Definition at line 513 of file regs.h.

#define IF_FREQ_IF_FREQ_MASK   (0x000001FFu)

Definition at line 511 of file regs.h.

#define IF_FREQ_REG   *((volatile int32u *)0x40001024u)

Definition at line 501 of file regs.h.

#define IF_FREQ_RESET   (0x00000155u)

Definition at line 503 of file regs.h.

#define IF_FREQ_TIMING_CORR_EN   (0x00008000u)

Definition at line 505 of file regs.h.

#define IF_FREQ_TIMING_CORR_EN_BIT   (15)

Definition at line 507 of file regs.h.

#define IF_FREQ_TIMING_CORR_EN_BITS   (1)

Definition at line 508 of file regs.h.

#define IF_FREQ_TIMING_CORR_EN_MASK   (0x00008000u)

Definition at line 506 of file regs.h.

#define IN_LOCK_EN   *((volatile int32u *)0x4000105Cu)

Definition at line 690 of file regs.h.

#define IN_LOCK_EN_ADDR   (0x4000105Cu)

Definition at line 692 of file regs.h.

#define IN_LOCK_EN_IN_LOCK_EN   (0x00000001u)

Definition at line 695 of file regs.h.

#define IN_LOCK_EN_IN_LOCK_EN_BIT   (0)

Definition at line 697 of file regs.h.

#define IN_LOCK_EN_IN_LOCK_EN_BITS   (1)

Definition at line 698 of file regs.h.

#define IN_LOCK_EN_IN_LOCK_EN_MASK   (0x00000001u)

Definition at line 696 of file regs.h.

#define IN_LOCK_EN_REG   *((volatile int32u *)0x4000105Cu)

Definition at line 691 of file regs.h.

#define IN_LOCK_EN_RESET   (0x00000001u)

Definition at line 693 of file regs.h.

#define INT_ACTIVE   *((volatile int32u *)0xE000E300u)

Definition at line 9630 of file regs.h.

#define INT_ACTIVE_ADDR   (0xE000E300u)

Definition at line 9632 of file regs.h.

#define INT_ACTIVE_REG   *((volatile int32u *)0xE000E300u)

Definition at line 9631 of file regs.h.

#define INT_ACTIVE_RESET   (0x00000000u)

Definition at line 9633 of file regs.h.

#define INT_ADC   (0x00000800u)

Definition at line 9660 of file regs.h.

#define INT_ADC   (0x00000800u)

Definition at line 9660 of file regs.h.

#define INT_ADC   (0x00000800u)

Definition at line 9660 of file regs.h.

#define INT_ADC   (0x00000800u)

Definition at line 9660 of file regs.h.

#define INT_ADC   (0x00000800u)

Definition at line 9660 of file regs.h.

#define INT_ADC_BIT   (11)

Definition at line 9662 of file regs.h.

#define INT_ADC_BIT   (11)

Definition at line 9662 of file regs.h.

#define INT_ADC_BIT   (11)

Definition at line 9662 of file regs.h.

#define INT_ADC_BIT   (11)

Definition at line 9662 of file regs.h.

#define INT_ADC_BIT   (11)

Definition at line 9662 of file regs.h.

#define INT_ADC_BITS   (1)

Definition at line 9663 of file regs.h.

#define INT_ADC_BITS   (1)

Definition at line 9663 of file regs.h.

#define INT_ADC_BITS   (1)

Definition at line 9663 of file regs.h.

#define INT_ADC_BITS   (1)

Definition at line 9663 of file regs.h.

#define INT_ADC_BITS   (1)

Definition at line 9663 of file regs.h.

#define INT_ADC_MASK   (0x00000800u)

Definition at line 9661 of file regs.h.

#define INT_ADC_MASK   (0x00000800u)

Definition at line 9661 of file regs.h.

#define INT_ADC_MASK   (0x00000800u)

Definition at line 9661 of file regs.h.

#define INT_ADC_MASK   (0x00000800u)

Definition at line 9661 of file regs.h.

#define INT_ADC_MASK   (0x00000800u)

Definition at line 9661 of file regs.h.

#define INT_ADCCFG   *((volatile int32u *)0x4000A850u)

Definition at line 4425 of file regs.h.

#define INT_ADCCFG_ADDR   (0x4000A850u)

Definition at line 4427 of file regs.h.

#define INT_ADCCFG_REG   *((volatile int32u *)0x4000A850u)

Definition at line 4426 of file regs.h.

#define INT_ADCCFG_RESET   (0x00000000u)

Definition at line 4428 of file regs.h.

#define INT_ADCCFGRSVD   (0x00000001u)

Definition at line 4450 of file regs.h.

#define INT_ADCCFGRSVD_BIT   (0)

Definition at line 4452 of file regs.h.

#define INT_ADCCFGRSVD_BITS   (1)

Definition at line 4453 of file regs.h.

#define INT_ADCCFGRSVD_MASK   (0x00000001u)

Definition at line 4451 of file regs.h.

#define INT_ADCFLAG   *((volatile int32u *)0x4000A810u)

Definition at line 4015 of file regs.h.

#define INT_ADCFLAG_ADDR   (0x4000A810u)

Definition at line 4017 of file regs.h.

#define INT_ADCFLAG_REG   *((volatile int32u *)0x4000A810u)

Definition at line 4016 of file regs.h.

#define INT_ADCFLAG_RESET   (0x00000000u)

Definition at line 4018 of file regs.h.

#define INT_ADCFLAGRSVD   (0x00000001u)

Definition at line 4040 of file regs.h.

#define INT_ADCFLAGRSVD_BIT   (0)

Definition at line 4042 of file regs.h.

#define INT_ADCFLAGRSVD_BITS   (1)

Definition at line 4043 of file regs.h.

#define INT_ADCFLAGRSVD_MASK   (0x00000001u)

Definition at line 4041 of file regs.h.

#define INT_ADCOVF   (0x00000010u)

Definition at line 4430 of file regs.h.

#define INT_ADCOVF   (0x00000010u)

Definition at line 4430 of file regs.h.

#define INT_ADCOVF_BIT   (4)

Definition at line 4432 of file regs.h.

#define INT_ADCOVF_BIT   (4)

Definition at line 4432 of file regs.h.

#define INT_ADCOVF_BITS   (1)

Definition at line 4433 of file regs.h.

#define INT_ADCOVF_BITS   (1)

Definition at line 4433 of file regs.h.

#define INT_ADCOVF_MASK   (0x00000010u)

Definition at line 4431 of file regs.h.

#define INT_ADCOVF_MASK   (0x00000010u)

Definition at line 4431 of file regs.h.

#define INT_ADCSAT   (0x00000008u)

Definition at line 4435 of file regs.h.

#define INT_ADCSAT   (0x00000008u)

Definition at line 4435 of file regs.h.

#define INT_ADCSAT_BIT   (3)

Definition at line 4437 of file regs.h.

#define INT_ADCSAT_BIT   (3)

Definition at line 4437 of file regs.h.

#define INT_ADCSAT_BITS   (1)

Definition at line 4438 of file regs.h.

#define INT_ADCSAT_BITS   (1)

Definition at line 4438 of file regs.h.

#define INT_ADCSAT_MASK   (0x00000008u)

Definition at line 4436 of file regs.h.

#define INT_ADCSAT_MASK   (0x00000008u)

Definition at line 4436 of file regs.h.

#define INT_ADCULDFULL   (0x00000004u)

Definition at line 4440 of file regs.h.

#define INT_ADCULDFULL   (0x00000004u)

Definition at line 4440 of file regs.h.

#define INT_ADCULDFULL_BIT   (2)

Definition at line 4442 of file regs.h.

#define INT_ADCULDFULL_BIT   (2)

Definition at line 4442 of file regs.h.

#define INT_ADCULDFULL_BITS   (1)

Definition at line 4443 of file regs.h.

#define INT_ADCULDFULL_BITS   (1)

Definition at line 4443 of file regs.h.

#define INT_ADCULDFULL_MASK   (0x00000004u)

Definition at line 4441 of file regs.h.

#define INT_ADCULDFULL_MASK   (0x00000004u)

Definition at line 4441 of file regs.h.

#define INT_ADCULDHALF   (0x00000002u)

Definition at line 4445 of file regs.h.

#define INT_ADCULDHALF   (0x00000002u)

Definition at line 4445 of file regs.h.

#define INT_ADCULDHALF_BIT   (1)

Definition at line 4447 of file regs.h.

#define INT_ADCULDHALF_BIT   (1)

Definition at line 4447 of file regs.h.

#define INT_ADCULDHALF_BITS   (1)

Definition at line 4448 of file regs.h.

#define INT_ADCULDHALF_BITS   (1)

Definition at line 4448 of file regs.h.

#define INT_ADCULDHALF_MASK   (0x00000002u)

Definition at line 4446 of file regs.h.

#define INT_ADCULDHALF_MASK   (0x00000002u)

Definition at line 4446 of file regs.h.

#define INT_BB   (0x00000008u)

Definition at line 9700 of file regs.h.

#define INT_BB   (0x00000008u)

Definition at line 9700 of file regs.h.

#define INT_BB   (0x00000008u)

Definition at line 9700 of file regs.h.

#define INT_BB   (0x00000008u)

Definition at line 9700 of file regs.h.

#define INT_BB   (0x00000008u)

Definition at line 9700 of file regs.h.

#define INT_BB_BIT   (3)

Definition at line 9702 of file regs.h.

#define INT_BB_BIT   (3)

Definition at line 9702 of file regs.h.

#define INT_BB_BIT   (3)

Definition at line 9702 of file regs.h.

#define INT_BB_BIT   (3)

Definition at line 9702 of file regs.h.

#define INT_BB_BIT   (3)

Definition at line 9702 of file regs.h.

#define INT_BB_BITS   (1)

Definition at line 9703 of file regs.h.

#define INT_BB_BITS   (1)

Definition at line 9703 of file regs.h.

#define INT_BB_BITS   (1)

Definition at line 9703 of file regs.h.

#define INT_BB_BITS   (1)

Definition at line 9703 of file regs.h.

#define INT_BB_BITS   (1)

Definition at line 9703 of file regs.h.

#define INT_BB_MASK   (0x00000008u)

Definition at line 9701 of file regs.h.

#define INT_BB_MASK   (0x00000008u)

Definition at line 9701 of file regs.h.

#define INT_BB_MASK   (0x00000008u)

Definition at line 9701 of file regs.h.

#define INT_BB_MASK   (0x00000008u)

Definition at line 9701 of file regs.h.

#define INT_BB_MASK   (0x00000008u)

Definition at line 9701 of file regs.h.

#define INT_CFGCLR   *((volatile int32u *)0xE000E180u)

Definition at line 9360 of file regs.h.

#define INT_CFGCLR_ADDR   (0xE000E180u)

Definition at line 9362 of file regs.h.

#define INT_CFGCLR_REG   *((volatile int32u *)0xE000E180u)

Definition at line 9361 of file regs.h.

#define INT_CFGCLR_RESET   (0x00000000u)

Definition at line 9363 of file regs.h.

#define INT_CFGSET   *((volatile int32u *)0xE000E100u)

Definition at line 9270 of file regs.h.

#define INT_CFGSET_ADDR   (0xE000E100u)

Definition at line 9272 of file regs.h.

#define INT_CFGSET_REG   *((volatile int32u *)0xE000E100u)

Definition at line 9271 of file regs.h.

#define INT_CFGSET_RESET   (0x00000000u)

Definition at line 9273 of file regs.h.

#define INT_DEBUG   (0x00010000u)

Definition at line 9635 of file regs.h.

#define INT_DEBUG   (0x00010000u)

Definition at line 9635 of file regs.h.

#define INT_DEBUG   (0x00010000u)

Definition at line 9635 of file regs.h.

#define INT_DEBUG   (0x00010000u)

Definition at line 9635 of file regs.h.

#define INT_DEBUG   (0x00010000u)

Definition at line 9635 of file regs.h.

#define INT_DEBUG_BIT   (16)

Definition at line 9637 of file regs.h.

#define INT_DEBUG_BIT   (16)

Definition at line 9637 of file regs.h.

#define INT_DEBUG_BIT   (16)

Definition at line 9637 of file regs.h.

#define INT_DEBUG_BIT   (16)

Definition at line 9637 of file regs.h.

#define INT_DEBUG_BIT   (16)

Definition at line 9637 of file regs.h.

#define INT_DEBUG_BITS   (1)

Definition at line 9638 of file regs.h.

#define INT_DEBUG_BITS   (1)

Definition at line 9638 of file regs.h.

#define INT_DEBUG_BITS   (1)

Definition at line 9638 of file regs.h.

#define INT_DEBUG_BITS   (1)

Definition at line 9638 of file regs.h.

#define INT_DEBUG_BITS   (1)

Definition at line 9638 of file regs.h.

#define INT_DEBUG_MASK   (0x00010000u)

Definition at line 9636 of file regs.h.

#define INT_DEBUG_MASK   (0x00010000u)

Definition at line 9636 of file regs.h.

#define INT_DEBUG_MASK   (0x00010000u)

Definition at line 9636 of file regs.h.

#define INT_DEBUG_MASK   (0x00010000u)

Definition at line 9636 of file regs.h.

#define INT_DEBUG_MASK   (0x00010000u)

Definition at line 9636 of file regs.h.

#define INT_GPIOFLAG   *((volatile int32u *)0x4000A814u)

Definition at line 4045 of file regs.h.

#define INT_GPIOFLAG_ADDR   (0x4000A814u)

Definition at line 4047 of file regs.h.

#define INT_GPIOFLAG_REG   *((volatile int32u *)0x4000A814u)

Definition at line 4046 of file regs.h.

#define INT_GPIOFLAG_RESET   (0x00000000u)

Definition at line 4048 of file regs.h.

#define INT_IRQA   (0x00001000u)

Definition at line 9655 of file regs.h.

#define INT_IRQA   (0x00001000u)

Definition at line 9655 of file regs.h.

#define INT_IRQA   (0x00001000u)

Definition at line 9655 of file regs.h.

#define INT_IRQA   (0x00001000u)

Definition at line 9655 of file regs.h.

#define INT_IRQA   (0x00001000u)

Definition at line 9655 of file regs.h.

#define INT_IRQA_BIT   (12)

Definition at line 9657 of file regs.h.

#define INT_IRQA_BIT   (12)

Definition at line 9657 of file regs.h.

#define INT_IRQA_BIT   (12)

Definition at line 9657 of file regs.h.

#define INT_IRQA_BIT   (12)

Definition at line 9657 of file regs.h.

#define INT_IRQA_BIT   (12)

Definition at line 9657 of file regs.h.

#define INT_IRQA_BITS   (1)

Definition at line 9658 of file regs.h.

#define INT_IRQA_BITS   (1)

Definition at line 9658 of file regs.h.

#define INT_IRQA_BITS   (1)

Definition at line 9658 of file regs.h.

#define INT_IRQA_BITS   (1)

Definition at line 9658 of file regs.h.

#define INT_IRQA_BITS   (1)

Definition at line 9658 of file regs.h.

#define INT_IRQA_MASK   (0x00001000u)

Definition at line 9656 of file regs.h.

#define INT_IRQA_MASK   (0x00001000u)

Definition at line 9656 of file regs.h.

#define INT_IRQA_MASK   (0x00001000u)

Definition at line 9656 of file regs.h.

#define INT_IRQA_MASK   (0x00001000u)

Definition at line 9656 of file regs.h.

#define INT_IRQA_MASK   (0x00001000u)

Definition at line 9656 of file regs.h.

#define INT_IRQAFLAG   (0x00000001u)

Definition at line 4065 of file regs.h.

#define INT_IRQAFLAG_BIT   (0)

Definition at line 4067 of file regs.h.

#define INT_IRQAFLAG_BITS   (1)

Definition at line 4068 of file regs.h.

#define INT_IRQAFLAG_MASK   (0x00000001u)

Definition at line 4066 of file regs.h.

#define INT_IRQB   (0x00002000u)

Definition at line 9650 of file regs.h.

#define INT_IRQB   (0x00002000u)

Definition at line 9650 of file regs.h.

#define INT_IRQB   (0x00002000u)

Definition at line 9650 of file regs.h.

#define INT_IRQB   (0x00002000u)

Definition at line 9650 of file regs.h.

#define INT_IRQB   (0x00002000u)

Definition at line 9650 of file regs.h.

#define INT_IRQB_BIT   (13)

Definition at line 9652 of file regs.h.

#define INT_IRQB_BIT   (13)

Definition at line 9652 of file regs.h.

#define INT_IRQB_BIT   (13)

Definition at line 9652 of file regs.h.

#define INT_IRQB_BIT   (13)

Definition at line 9652 of file regs.h.

#define INT_IRQB_BIT   (13)

Definition at line 9652 of file regs.h.

#define INT_IRQB_BITS   (1)

Definition at line 9653 of file regs.h.

#define INT_IRQB_BITS   (1)

Definition at line 9653 of file regs.h.

#define INT_IRQB_BITS   (1)

Definition at line 9653 of file regs.h.

#define INT_IRQB_BITS   (1)

Definition at line 9653 of file regs.h.

#define INT_IRQB_BITS   (1)

Definition at line 9653 of file regs.h.

#define INT_IRQB_MASK   (0x00002000u)

Definition at line 9651 of file regs.h.

#define INT_IRQB_MASK   (0x00002000u)

Definition at line 9651 of file regs.h.

#define INT_IRQB_MASK   (0x00002000u)

Definition at line 9651 of file regs.h.

#define INT_IRQB_MASK   (0x00002000u)

Definition at line 9651 of file regs.h.

#define INT_IRQB_MASK   (0x00002000u)

Definition at line 9651 of file regs.h.

#define INT_IRQBFLAG   (0x00000002u)

Definition at line 4060 of file regs.h.

#define INT_IRQBFLAG_BIT   (1)

Definition at line 4062 of file regs.h.

#define INT_IRQBFLAG_BITS   (1)

Definition at line 4063 of file regs.h.

#define INT_IRQBFLAG_MASK   (0x00000002u)

Definition at line 4061 of file regs.h.

#define INT_IRQC   (0x00004000u)

Definition at line 9645 of file regs.h.

#define INT_IRQC   (0x00004000u)

Definition at line 9645 of file regs.h.

#define INT_IRQC   (0x00004000u)

Definition at line 9645 of file regs.h.

#define INT_IRQC   (0x00004000u)

Definition at line 9645 of file regs.h.

#define INT_IRQC   (0x00004000u)

Definition at line 9645 of file regs.h.

#define INT_IRQC_BIT   (14)

Definition at line 9647 of file regs.h.

#define INT_IRQC_BIT   (14)

Definition at line 9647 of file regs.h.

#define INT_IRQC_BIT   (14)

Definition at line 9647 of file regs.h.

#define INT_IRQC_BIT   (14)

Definition at line 9647 of file regs.h.

#define INT_IRQC_BIT   (14)

Definition at line 9647 of file regs.h.

#define INT_IRQC_BITS   (1)

Definition at line 9648 of file regs.h.

#define INT_IRQC_BITS   (1)

Definition at line 9648 of file regs.h.

#define INT_IRQC_BITS   (1)

Definition at line 9648 of file regs.h.

#define INT_IRQC_BITS   (1)

Definition at line 9648 of file regs.h.

#define INT_IRQC_BITS   (1)

Definition at line 9648 of file regs.h.

#define INT_IRQC_MASK   (0x00004000u)

Definition at line 9646 of file regs.h.

#define INT_IRQC_MASK   (0x00004000u)

Definition at line 9646 of file regs.h.

#define INT_IRQC_MASK   (0x00004000u)

Definition at line 9646 of file regs.h.

#define INT_IRQC_MASK   (0x00004000u)

Definition at line 9646 of file regs.h.

#define INT_IRQC_MASK   (0x00004000u)

Definition at line 9646 of file regs.h.

#define INT_IRQCFLAG   (0x00000004u)

Definition at line 4055 of file regs.h.

#define INT_IRQCFLAG_BIT   (2)

Definition at line 4057 of file regs.h.

#define INT_IRQCFLAG_BITS   (1)

Definition at line 4058 of file regs.h.

#define INT_IRQCFLAG_MASK   (0x00000004u)

Definition at line 4056 of file regs.h.

#define INT_IRQD   (0x00008000u)

Definition at line 9640 of file regs.h.

#define INT_IRQD   (0x00008000u)

Definition at line 9640 of file regs.h.

#define INT_IRQD   (0x00008000u)

Definition at line 9640 of file regs.h.

#define INT_IRQD   (0x00008000u)

Definition at line 9640 of file regs.h.

#define INT_IRQD   (0x00008000u)

Definition at line 9640 of file regs.h.

#define INT_IRQD_BIT   (15)

Definition at line 9642 of file regs.h.

#define INT_IRQD_BIT   (15)

Definition at line 9642 of file regs.h.

#define INT_IRQD_BIT   (15)

Definition at line 9642 of file regs.h.

#define INT_IRQD_BIT   (15)

Definition at line 9642 of file regs.h.

#define INT_IRQD_BIT   (15)

Definition at line 9642 of file regs.h.

#define INT_IRQD_BITS   (1)

Definition at line 9643 of file regs.h.

#define INT_IRQD_BITS   (1)

Definition at line 9643 of file regs.h.

#define INT_IRQD_BITS   (1)

Definition at line 9643 of file regs.h.

#define INT_IRQD_BITS   (1)

Definition at line 9643 of file regs.h.

#define INT_IRQD_BITS   (1)

Definition at line 9643 of file regs.h.

#define INT_IRQD_MASK   (0x00008000u)

Definition at line 9641 of file regs.h.

#define INT_IRQD_MASK   (0x00008000u)

Definition at line 9641 of file regs.h.

#define INT_IRQD_MASK   (0x00008000u)

Definition at line 9641 of file regs.h.

#define INT_IRQD_MASK   (0x00008000u)

Definition at line 9641 of file regs.h.

#define INT_IRQD_MASK   (0x00008000u)

Definition at line 9641 of file regs.h.

#define INT_IRQDFLAG   (0x00000008u)

Definition at line 4050 of file regs.h.

#define INT_IRQDFLAG_BIT   (3)

Definition at line 4052 of file regs.h.

#define INT_IRQDFLAG_BITS   (1)

Definition at line 4053 of file regs.h.

#define INT_IRQDFLAG_MASK   (0x00000008u)

Definition at line 4051 of file regs.h.

#define INT_MACRX   (0x00000400u)

Definition at line 9665 of file regs.h.

#define INT_MACRX   (0x00000400u)

Definition at line 9665 of file regs.h.

#define INT_MACRX   (0x00000400u)

Definition at line 9665 of file regs.h.

#define INT_MACRX   (0x00000400u)

Definition at line 9665 of file regs.h.

#define INT_MACRX   (0x00000400u)

Definition at line 9665 of file regs.h.

#define INT_MACRX_BIT   (10)

Definition at line 9667 of file regs.h.

#define INT_MACRX_BIT   (10)

Definition at line 9667 of file regs.h.

#define INT_MACRX_BIT   (10)

Definition at line 9667 of file regs.h.

#define INT_MACRX_BIT   (10)

Definition at line 9667 of file regs.h.

#define INT_MACRX_BIT   (10)

Definition at line 9667 of file regs.h.

#define INT_MACRX_BITS   (1)

Definition at line 9668 of file regs.h.

#define INT_MACRX_BITS   (1)

Definition at line 9668 of file regs.h.

#define INT_MACRX_BITS   (1)

Definition at line 9668 of file regs.h.

#define INT_MACRX_BITS   (1)

Definition at line 9668 of file regs.h.

#define INT_MACRX_BITS   (1)

Definition at line 9668 of file regs.h.

#define INT_MACRX_MASK   (0x00000400u)

Definition at line 9666 of file regs.h.

#define INT_MACRX_MASK   (0x00000400u)

Definition at line 9666 of file regs.h.

#define INT_MACRX_MASK   (0x00000400u)

Definition at line 9666 of file regs.h.

#define INT_MACRX_MASK   (0x00000400u)

Definition at line 9666 of file regs.h.

#define INT_MACRX_MASK   (0x00000400u)

Definition at line 9666 of file regs.h.

#define INT_MACTMR   (0x00000100u)

Definition at line 9675 of file regs.h.

#define INT_MACTMR   (0x00000100u)

Definition at line 9675 of file regs.h.

#define INT_MACTMR   (0x00000100u)

Definition at line 9675 of file regs.h.

#define INT_MACTMR   (0x00000100u)

Definition at line 9675 of file regs.h.

#define INT_MACTMR   (0x00000100u)

Definition at line 9675 of file regs.h.

#define INT_MACTMR_BIT   (8)

Definition at line 9677 of file regs.h.

#define INT_MACTMR_BIT   (8)

Definition at line 9677 of file regs.h.

#define INT_MACTMR_BIT   (8)

Definition at line 9677 of file regs.h.

#define INT_MACTMR_BIT   (8)

Definition at line 9677 of file regs.h.

#define INT_MACTMR_BIT   (8)

Definition at line 9677 of file regs.h.

#define INT_MACTMR_BITS   (1)

Definition at line 9678 of file regs.h.

#define INT_MACTMR_BITS   (1)

Definition at line 9678 of file regs.h.

#define INT_MACTMR_BITS   (1)

Definition at line 9678 of file regs.h.

#define INT_MACTMR_BITS   (1)

Definition at line 9678 of file regs.h.

#define INT_MACTMR_BITS   (1)

Definition at line 9678 of file regs.h.

#define INT_MACTMR_MASK   (0x00000100u)

Definition at line 9676 of file regs.h.

#define INT_MACTMR_MASK   (0x00000100u)

Definition at line 9676 of file regs.h.

#define INT_MACTMR_MASK   (0x00000100u)

Definition at line 9676 of file regs.h.

#define INT_MACTMR_MASK   (0x00000100u)

Definition at line 9676 of file regs.h.

#define INT_MACTMR_MASK   (0x00000100u)

Definition at line 9676 of file regs.h.

#define INT_MACTX   (0x00000200u)

Definition at line 9670 of file regs.h.

#define INT_MACTX   (0x00000200u)

Definition at line 9670 of file regs.h.

#define INT_MACTX   (0x00000200u)

Definition at line 9670 of file regs.h.

#define INT_MACTX   (0x00000200u)

Definition at line 9670 of file regs.h.

#define INT_MACTX   (0x00000200u)

Definition at line 9670 of file regs.h.

#define INT_MACTX_BIT   (9)

Definition at line 9672 of file regs.h.

#define INT_MACTX_BIT   (9)

Definition at line 9672 of file regs.h.

#define INT_MACTX_BIT   (9)

Definition at line 9672 of file regs.h.

#define INT_MACTX_BIT   (9)

Definition at line 9672 of file regs.h.

#define INT_MACTX_BIT   (9)

Definition at line 9672 of file regs.h.

#define INT_MACTX_BITS   (1)

Definition at line 9673 of file regs.h.

#define INT_MACTX_BITS   (1)

Definition at line 9673 of file regs.h.

#define INT_MACTX_BITS   (1)

Definition at line 9673 of file regs.h.

#define INT_MACTX_BITS   (1)

Definition at line 9673 of file regs.h.

#define INT_MACTX_BITS   (1)

Definition at line 9673 of file regs.h.

#define INT_MACTX_MASK   (0x00000200u)

Definition at line 9671 of file regs.h.

#define INT_MACTX_MASK   (0x00000200u)

Definition at line 9671 of file regs.h.

#define INT_MACTX_MASK   (0x00000200u)

Definition at line 9671 of file regs.h.

#define INT_MACTX_MASK   (0x00000200u)

Definition at line 9671 of file regs.h.

#define INT_MACTX_MASK   (0x00000200u)

Definition at line 9671 of file regs.h.

#define INT_MGMT   (0x00000004u)

Definition at line 9705 of file regs.h.

#define INT_MGMT   (0x00000004u)

Definition at line 9705 of file regs.h.

#define INT_MGMT   (0x00000004u)

Definition at line 9705 of file regs.h.

#define INT_MGMT   (0x00000004u)

Definition at line 9705 of file regs.h.

#define INT_MGMT   (0x00000004u)

Definition at line 9705 of file regs.h.

#define INT_MGMT_BIT   (2)

Definition at line 9707 of file regs.h.

#define INT_MGMT_BIT   (2)

Definition at line 9707 of file regs.h.

#define INT_MGMT_BIT   (2)

Definition at line 9707 of file regs.h.

#define INT_MGMT_BIT   (2)

Definition at line 9707 of file regs.h.

#define INT_MGMT_BIT   (2)

Definition at line 9707 of file regs.h.

#define INT_MGMT_BITS   (1)

Definition at line 9708 of file regs.h.

#define INT_MGMT_BITS   (1)

Definition at line 9708 of file regs.h.

#define INT_MGMT_BITS   (1)

Definition at line 9708 of file regs.h.

#define INT_MGMT_BITS   (1)

Definition at line 9708 of file regs.h.

#define INT_MGMT_BITS   (1)

Definition at line 9708 of file regs.h.

#define INT_MGMT_MASK   (0x00000004u)

Definition at line 9706 of file regs.h.

#define INT_MGMT_MASK   (0x00000004u)

Definition at line 9706 of file regs.h.

#define INT_MGMT_MASK   (0x00000004u)

Definition at line 9706 of file regs.h.

#define INT_MGMT_MASK   (0x00000004u)

Definition at line 9706 of file regs.h.

#define INT_MGMT_MASK   (0x00000004u)

Definition at line 9706 of file regs.h.

#define INT_MGMTCALADC   (0x00000008u)

Definition at line 3765 of file regs.h.

#define INT_MGMTCALADC   (0x00000008u)

Definition at line 3765 of file regs.h.

#define INT_MGMTCALADC_BIT   (3)

Definition at line 3767 of file regs.h.

#define INT_MGMTCALADC_BIT   (3)

Definition at line 3767 of file regs.h.

#define INT_MGMTCALADC_BITS   (1)

Definition at line 3768 of file regs.h.

#define INT_MGMTCALADC_BITS   (1)

Definition at line 3768 of file regs.h.

#define INT_MGMTCALADC_MASK   (0x00000008u)

Definition at line 3766 of file regs.h.

#define INT_MGMTCALADC_MASK   (0x00000008u)

Definition at line 3766 of file regs.h.

#define INT_MGMTCFG   *((volatile int32u *)0x4000A058u)

Definition at line 3755 of file regs.h.

#define INT_MGMTCFG_ADDR   (0x4000A058u)

Definition at line 3757 of file regs.h.

#define INT_MGMTCFG_REG   *((volatile int32u *)0x4000A058u)

Definition at line 3756 of file regs.h.

#define INT_MGMTCFG_RESET   (0x00000000u)

Definition at line 3758 of file regs.h.

#define INT_MGMTDMAPROT   (0x00000010u)

Definition at line 3760 of file regs.h.

#define INT_MGMTDMAPROT   (0x00000010u)

Definition at line 3760 of file regs.h.

#define INT_MGMTDMAPROT_BIT   (4)

Definition at line 3762 of file regs.h.

#define INT_MGMTDMAPROT_BIT   (4)

Definition at line 3762 of file regs.h.

#define INT_MGMTDMAPROT_BITS   (1)

Definition at line 3763 of file regs.h.

#define INT_MGMTDMAPROT_BITS   (1)

Definition at line 3763 of file regs.h.

#define INT_MGMTDMAPROT_MASK   (0x00000010u)

Definition at line 3761 of file regs.h.

#define INT_MGMTDMAPROT_MASK   (0x00000010u)

Definition at line 3761 of file regs.h.

#define INT_MGMTFLAG   *((volatile int32u *)0x4000A018u)

Definition at line 3455 of file regs.h.

#define INT_MGMTFLAG_ADDR   (0x4000A018u)

Definition at line 3457 of file regs.h.

#define INT_MGMTFLAG_REG   *((volatile int32u *)0x4000A018u)

Definition at line 3456 of file regs.h.

#define INT_MGMTFLAG_RESET   (0x00000000u)

Definition at line 3458 of file regs.h.

#define INT_MGMTFPEC   (0x00000004u)

Definition at line 3770 of file regs.h.

#define INT_MGMTFPEC   (0x00000004u)

Definition at line 3770 of file regs.h.

#define INT_MGMTFPEC_BIT   (2)

Definition at line 3772 of file regs.h.

#define INT_MGMTFPEC_BIT   (2)

Definition at line 3772 of file regs.h.

#define INT_MGMTFPEC_BITS   (1)

Definition at line 3773 of file regs.h.

#define INT_MGMTFPEC_BITS   (1)

Definition at line 3773 of file regs.h.

#define INT_MGMTFPEC_MASK   (0x00000004u)

Definition at line 3771 of file regs.h.

#define INT_MGMTFPEC_MASK   (0x00000004u)

Definition at line 3771 of file regs.h.

#define INT_MGMTOSC24MHI   (0x00000002u)

Definition at line 3775 of file regs.h.

#define INT_MGMTOSC24MHI   (0x00000002u)

Definition at line 3775 of file regs.h.

#define INT_MGMTOSC24MHI_BIT   (1)

Definition at line 3777 of file regs.h.

#define INT_MGMTOSC24MHI_BIT   (1)

Definition at line 3777 of file regs.h.

#define INT_MGMTOSC24MHI_BITS   (1)

Definition at line 3778 of file regs.h.

#define INT_MGMTOSC24MHI_BITS   (1)

Definition at line 3778 of file regs.h.

#define INT_MGMTOSC24MHI_MASK   (0x00000002u)

Definition at line 3776 of file regs.h.

#define INT_MGMTOSC24MHI_MASK   (0x00000002u)

Definition at line 3776 of file regs.h.

#define INT_MGMTOSC24MLO   (0x00000001u)

Definition at line 3780 of file regs.h.

#define INT_MGMTOSC24MLO   (0x00000001u)

Definition at line 3780 of file regs.h.

#define INT_MGMTOSC24MLO_BIT   (0)

Definition at line 3782 of file regs.h.

#define INT_MGMTOSC24MLO_BIT   (0)

Definition at line 3782 of file regs.h.

#define INT_MGMTOSC24MLO_BITS   (1)

Definition at line 3783 of file regs.h.

#define INT_MGMTOSC24MLO_BITS   (1)

Definition at line 3783 of file regs.h.

#define INT_MGMTOSC24MLO_MASK   (0x00000001u)

Definition at line 3781 of file regs.h.

#define INT_MGMTOSC24MLO_MASK   (0x00000001u)

Definition at line 3781 of file regs.h.

#define INT_MISS   *((volatile int32u *)0x4000A820u)

Definition at line 4130 of file regs.h.

#define INT_MISS_ADDR   (0x4000A820u)

Definition at line 4132 of file regs.h.

#define INT_MISS_REG   *((volatile int32u *)0x4000A820u)

Definition at line 4131 of file regs.h.

#define INT_MISS_RESET   (0x00000000u)

Definition at line 4133 of file regs.h.

#define INT_MISSADC   (0x00000800u)

Definition at line 4155 of file regs.h.

#define INT_MISSADC_BIT   (11)

Definition at line 4157 of file regs.h.

#define INT_MISSADC_BITS   (1)

Definition at line 4158 of file regs.h.

#define INT_MISSADC_MASK   (0x00000800u)

Definition at line 4156 of file regs.h.

#define INT_MISSBB   (0x00000008u)

Definition at line 4195 of file regs.h.

#define INT_MISSBB_BIT   (3)

Definition at line 4197 of file regs.h.

#define INT_MISSBB_BITS   (1)

Definition at line 4198 of file regs.h.

#define INT_MISSBB_MASK   (0x00000008u)

Definition at line 4196 of file regs.h.

#define INT_MISSIRQA   (0x00001000u)

Definition at line 4150 of file regs.h.

#define INT_MISSIRQA_BIT   (12)

Definition at line 4152 of file regs.h.

#define INT_MISSIRQA_BITS   (1)

Definition at line 4153 of file regs.h.

#define INT_MISSIRQA_MASK   (0x00001000u)

Definition at line 4151 of file regs.h.

#define INT_MISSIRQB   (0x00002000u)

Definition at line 4145 of file regs.h.

#define INT_MISSIRQB_BIT   (13)

Definition at line 4147 of file regs.h.

#define INT_MISSIRQB_BITS   (1)

Definition at line 4148 of file regs.h.

#define INT_MISSIRQB_MASK   (0x00002000u)

Definition at line 4146 of file regs.h.

#define INT_MISSIRQC   (0x00004000u)

Definition at line 4140 of file regs.h.

#define INT_MISSIRQC_BIT   (14)

Definition at line 4142 of file regs.h.

#define INT_MISSIRQC_BITS   (1)

Definition at line 4143 of file regs.h.

#define INT_MISSIRQC_MASK   (0x00004000u)

Definition at line 4141 of file regs.h.

#define INT_MISSIRQD   (0x00008000u)

Definition at line 4135 of file regs.h.

#define INT_MISSIRQD_BIT   (15)

Definition at line 4137 of file regs.h.

#define INT_MISSIRQD_BITS   (1)

Definition at line 4138 of file regs.h.

#define INT_MISSIRQD_MASK   (0x00008000u)

Definition at line 4136 of file regs.h.

#define INT_MISSMACRX   (0x00000400u)

Definition at line 4160 of file regs.h.

#define INT_MISSMACRX_BIT   (10)

Definition at line 4162 of file regs.h.

#define INT_MISSMACRX_BITS   (1)

Definition at line 4163 of file regs.h.

#define INT_MISSMACRX_MASK   (0x00000400u)

Definition at line 4161 of file regs.h.

#define INT_MISSMACTMR   (0x00000100u)

Definition at line 4170 of file regs.h.

#define INT_MISSMACTMR_BIT   (8)

Definition at line 4172 of file regs.h.

#define INT_MISSMACTMR_BITS   (1)

Definition at line 4173 of file regs.h.

#define INT_MISSMACTMR_MASK   (0x00000100u)

Definition at line 4171 of file regs.h.

#define INT_MISSMACTX   (0x00000200u)

Definition at line 4165 of file regs.h.

#define INT_MISSMACTX_BIT   (9)

Definition at line 4167 of file regs.h.

#define INT_MISSMACTX_BITS   (1)

Definition at line 4168 of file regs.h.

#define INT_MISSMACTX_MASK   (0x00000200u)

Definition at line 4166 of file regs.h.

#define INT_MISSMGMT   (0x00000004u)

Definition at line 4200 of file regs.h.

#define INT_MISSMGMT_BIT   (2)

Definition at line 4202 of file regs.h.

#define INT_MISSMGMT_BITS   (1)

Definition at line 4203 of file regs.h.

#define INT_MISSMGMT_MASK   (0x00000004u)

Definition at line 4201 of file regs.h.

#define INT_MISSSC1   (0x00000020u)

Definition at line 4185 of file regs.h.

#define INT_MISSSC1_BIT   (5)

Definition at line 4187 of file regs.h.

#define INT_MISSSC1_BITS   (1)

Definition at line 4188 of file regs.h.

#define INT_MISSSC1_MASK   (0x00000020u)

Definition at line 4186 of file regs.h.

#define INT_MISSSC2   (0x00000040u)

Definition at line 4180 of file regs.h.

#define INT_MISSSC2_BIT   (6)

Definition at line 4182 of file regs.h.

#define INT_MISSSC2_BITS   (1)

Definition at line 4183 of file regs.h.

#define INT_MISSSC2_MASK   (0x00000040u)

Definition at line 4181 of file regs.h.

#define INT_MISSSEC   (0x00000080u)

Definition at line 4175 of file regs.h.

#define INT_MISSSEC_BIT   (7)

Definition at line 4177 of file regs.h.

#define INT_MISSSEC_BITS   (1)

Definition at line 4178 of file regs.h.

#define INT_MISSSEC_MASK   (0x00000080u)

Definition at line 4176 of file regs.h.

#define INT_MISSSLEEP   (0x00000010u)

Definition at line 4190 of file regs.h.

#define INT_MISSSLEEP_BIT   (4)

Definition at line 4192 of file regs.h.

#define INT_MISSSLEEP_BITS   (1)

Definition at line 4193 of file regs.h.

#define INT_MISSSLEEP_MASK   (0x00000010u)

Definition at line 4191 of file regs.h.

#define INT_NMICLK24M   (0x00000002u)

Definition at line 3490 of file regs.h.

#define INT_NMICLK24M_BIT   (1)

Definition at line 3492 of file regs.h.

#define INT_NMICLK24M_BITS   (1)

Definition at line 3493 of file regs.h.

#define INT_NMICLK24M_MASK   (0x00000002u)

Definition at line 3491 of file regs.h.

#define INT_NMIFLAG   *((volatile int32u *)0x4000A01Cu)

Definition at line 3485 of file regs.h.

#define INT_NMIFLAG_ADDR   (0x4000A01Cu)

Definition at line 3487 of file regs.h.

#define INT_NMIFLAG_REG   *((volatile int32u *)0x4000A01Cu)

Definition at line 3486 of file regs.h.

#define INT_NMIFLAG_RESET   (0x00000000u)

Definition at line 3488 of file regs.h.

#define INT_NMIWDOG   (0x00000001u)

Definition at line 3495 of file regs.h.

#define INT_NMIWDOG_BIT   (0)

Definition at line 3497 of file regs.h.

#define INT_NMIWDOG_BITS   (1)

Definition at line 3498 of file regs.h.

#define INT_NMIWDOG_MASK   (0x00000001u)

Definition at line 3496 of file regs.h.

#define INT_PENDCLR   *((volatile int32u *)0xE000E280u)

Definition at line 9540 of file regs.h.

#define INT_PENDCLR_ADDR   (0xE000E280u)

Definition at line 9542 of file regs.h.

#define INT_PENDCLR_REG   *((volatile int32u *)0xE000E280u)

Definition at line 9541 of file regs.h.

#define INT_PENDCLR_RESET   (0x00000000u)

Definition at line 9543 of file regs.h.

#define INT_PENDSET   *((volatile int32u *)0xE000E200u)

Definition at line 9450 of file regs.h.

#define INT_PENDSET_ADDR   (0xE000E200u)

Definition at line 9452 of file regs.h.

#define INT_PENDSET_REG   *((volatile int32u *)0xE000E200u)

Definition at line 9451 of file regs.h.

#define INT_PENDSET_RESET   (0x00000000u)

Definition at line 9453 of file regs.h.

#define INT_SC1   (0x00000020u)

Definition at line 9690 of file regs.h.

#define INT_SC1   (0x00000020u)

Definition at line 9690 of file regs.h.

#define INT_SC1   (0x00000020u)

Definition at line 9690 of file regs.h.

#define INT_SC1   (0x00000020u)

Definition at line 9690 of file regs.h.

#define INT_SC1   (0x00000020u)

Definition at line 9690 of file regs.h.

#define INT_SC1_BIT   (5)

Definition at line 9692 of file regs.h.

#define INT_SC1_BIT   (5)

Definition at line 9692 of file regs.h.

#define INT_SC1_BIT   (5)

Definition at line 9692 of file regs.h.

#define INT_SC1_BIT   (5)

Definition at line 9692 of file regs.h.

#define INT_SC1_BIT   (5)

Definition at line 9692 of file regs.h.

#define INT_SC1_BITS   (1)

Definition at line 9693 of file regs.h.

#define INT_SC1_BITS   (1)

Definition at line 9693 of file regs.h.

#define INT_SC1_BITS   (1)

Definition at line 9693 of file regs.h.

#define INT_SC1_BITS   (1)

Definition at line 9693 of file regs.h.

#define INT_SC1_BITS   (1)

Definition at line 9693 of file regs.h.

#define INT_SC1_MASK   (0x00000020u)

Definition at line 9691 of file regs.h.

#define INT_SC1_MASK   (0x00000020u)

Definition at line 9691 of file regs.h.

#define INT_SC1_MASK   (0x00000020u)

Definition at line 9691 of file regs.h.

#define INT_SC1_MASK   (0x00000020u)

Definition at line 9691 of file regs.h.

#define INT_SC1_MASK   (0x00000020u)

Definition at line 9691 of file regs.h.

#define INT_SC1CFG   *((volatile int32u *)0x4000A848u)

Definition at line 4275 of file regs.h.

#define INT_SC1CFG_ADDR   (0x4000A848u)

Definition at line 4277 of file regs.h.

#define INT_SC1CFG_REG   *((volatile int32u *)0x4000A848u)

Definition at line 4276 of file regs.h.

#define INT_SC1CFG_RESET   (0x00000000u)

Definition at line 4278 of file regs.h.

#define INT_SC1FLAG   *((volatile int32u *)0x4000A808u)

Definition at line 3865 of file regs.h.

#define INT_SC1FLAG_ADDR   (0x4000A808u)

Definition at line 3867 of file regs.h.

#define INT_SC1FLAG_REG   *((volatile int32u *)0x4000A808u)

Definition at line 3866 of file regs.h.

#define INT_SC1FLAG_RESET   (0x00000000u)

Definition at line 3868 of file regs.h.

#define INT_SC1FRMERR   (0x00002000u)

Definition at line 4285 of file regs.h.

#define INT_SC1FRMERR   (0x00002000u)

Definition at line 4285 of file regs.h.

#define INT_SC1FRMERR_BIT   (13)

Definition at line 4287 of file regs.h.

#define INT_SC1FRMERR_BIT   (13)

Definition at line 4287 of file regs.h.

#define INT_SC1FRMERR_BITS   (1)

Definition at line 4288 of file regs.h.

#define INT_SC1FRMERR_BITS   (1)

Definition at line 4288 of file regs.h.

#define INT_SC1FRMERR_MASK   (0x00002000u)

Definition at line 4286 of file regs.h.

#define INT_SC1FRMERR_MASK   (0x00002000u)

Definition at line 4286 of file regs.h.

#define INT_SC1PARERR   (0x00004000u)

Definition at line 4280 of file regs.h.

#define INT_SC1PARERR   (0x00004000u)

Definition at line 4280 of file regs.h.

#define INT_SC1PARERR_BIT   (14)

Definition at line 4282 of file regs.h.

#define INT_SC1PARERR_BIT   (14)

Definition at line 4282 of file regs.h.

#define INT_SC1PARERR_BITS   (1)

Definition at line 4283 of file regs.h.

#define INT_SC1PARERR_BITS   (1)

Definition at line 4283 of file regs.h.

#define INT_SC1PARERR_MASK   (0x00004000u)

Definition at line 4281 of file regs.h.

#define INT_SC1PARERR_MASK   (0x00004000u)

Definition at line 4281 of file regs.h.

#define INT_SC2   (0x00000040u)

Definition at line 9685 of file regs.h.

#define INT_SC2   (0x00000040u)

Definition at line 9685 of file regs.h.

#define INT_SC2   (0x00000040u)

Definition at line 9685 of file regs.h.

#define INT_SC2   (0x00000040u)

Definition at line 9685 of file regs.h.

#define INT_SC2   (0x00000040u)

Definition at line 9685 of file regs.h.

#define INT_SC2_BIT   (6)

Definition at line 9687 of file regs.h.

#define INT_SC2_BIT   (6)

Definition at line 9687 of file regs.h.

#define INT_SC2_BIT   (6)

Definition at line 9687 of file regs.h.

#define INT_SC2_BIT   (6)

Definition at line 9687 of file regs.h.

#define INT_SC2_BIT   (6)

Definition at line 9687 of file regs.h.

#define INT_SC2_BITS   (1)

Definition at line 9688 of file regs.h.

#define INT_SC2_BITS   (1)

Definition at line 9688 of file regs.h.

#define INT_SC2_BITS   (1)

Definition at line 9688 of file regs.h.

#define INT_SC2_BITS   (1)

Definition at line 9688 of file regs.h.

#define INT_SC2_BITS   (1)

Definition at line 9688 of file regs.h.

#define INT_SC2_MASK   (0x00000040u)

Definition at line 9686 of file regs.h.

#define INT_SC2_MASK   (0x00000040u)

Definition at line 9686 of file regs.h.

#define INT_SC2_MASK   (0x00000040u)

Definition at line 9686 of file regs.h.

#define INT_SC2_MASK   (0x00000040u)

Definition at line 9686 of file regs.h.

#define INT_SC2_MASK   (0x00000040u)

Definition at line 9686 of file regs.h.

#define INT_SC2CFG   *((volatile int32u *)0x4000A84Cu)

Definition at line 4355 of file regs.h.

#define INT_SC2CFG_ADDR   (0x4000A84Cu)

Definition at line 4357 of file regs.h.

#define INT_SC2CFG_REG   *((volatile int32u *)0x4000A84Cu)

Definition at line 4356 of file regs.h.

#define INT_SC2CFG_RESET   (0x00000000u)

Definition at line 4358 of file regs.h.

#define INT_SC2FLAG   *((volatile int32u *)0x4000A80Cu)

Definition at line 3945 of file regs.h.

#define INT_SC2FLAG_ADDR   (0x4000A80Cu)

Definition at line 3947 of file regs.h.

#define INT_SC2FLAG_REG   *((volatile int32u *)0x4000A80Cu)

Definition at line 3946 of file regs.h.

#define INT_SC2FLAG_RESET   (0x00000000u)

Definition at line 3948 of file regs.h.

#define INT_SCCMDFIN   (0x00000080u)

Definition at line 4385 of file regs.h.

#define INT_SCCMDFIN   (0x00000080u)

Definition at line 4385 of file regs.h.

#define INT_SCCMDFIN   (0x00000080u)

Definition at line 4385 of file regs.h.

#define INT_SCCMDFIN   (0x00000080u)

Definition at line 4385 of file regs.h.

#define INT_SCCMDFIN_BIT   (7)

Definition at line 4387 of file regs.h.

#define INT_SCCMDFIN_BIT   (7)

Definition at line 4387 of file regs.h.

#define INT_SCCMDFIN_BIT   (7)

Definition at line 4387 of file regs.h.

#define INT_SCCMDFIN_BIT   (7)

Definition at line 4387 of file regs.h.

#define INT_SCCMDFIN_BITS   (1)

Definition at line 4388 of file regs.h.

#define INT_SCCMDFIN_BITS   (1)

Definition at line 4388 of file regs.h.

#define INT_SCCMDFIN_BITS   (1)

Definition at line 4388 of file regs.h.

#define INT_SCCMDFIN_BITS   (1)

Definition at line 4388 of file regs.h.

#define INT_SCCMDFIN_MASK   (0x00000080u)

Definition at line 4386 of file regs.h.

#define INT_SCCMDFIN_MASK   (0x00000080u)

Definition at line 4386 of file regs.h.

#define INT_SCCMDFIN_MASK   (0x00000080u)

Definition at line 4386 of file regs.h.

#define INT_SCCMDFIN_MASK   (0x00000080u)

Definition at line 4386 of file regs.h.

#define INT_SCNAK   (0x00000100u)

Definition at line 4380 of file regs.h.

#define INT_SCNAK   (0x00000100u)

Definition at line 4380 of file regs.h.

#define INT_SCNAK   (0x00000100u)

Definition at line 4380 of file regs.h.

#define INT_SCNAK   (0x00000100u)

Definition at line 4380 of file regs.h.

#define INT_SCNAK_BIT   (8)

Definition at line 4382 of file regs.h.

#define INT_SCNAK_BIT   (8)

Definition at line 4382 of file regs.h.

#define INT_SCNAK_BIT   (8)

Definition at line 4382 of file regs.h.

#define INT_SCNAK_BIT   (8)

Definition at line 4382 of file regs.h.

#define INT_SCNAK_BITS   (1)

Definition at line 4383 of file regs.h.

#define INT_SCNAK_BITS   (1)

Definition at line 4383 of file regs.h.

#define INT_SCNAK_BITS   (1)

Definition at line 4383 of file regs.h.

#define INT_SCNAK_BITS   (1)

Definition at line 4383 of file regs.h.

#define INT_SCNAK_MASK   (0x00000100u)

Definition at line 4381 of file regs.h.

#define INT_SCNAK_MASK   (0x00000100u)

Definition at line 4381 of file regs.h.

#define INT_SCNAK_MASK   (0x00000100u)

Definition at line 4381 of file regs.h.

#define INT_SCNAK_MASK   (0x00000100u)

Definition at line 4381 of file regs.h.

#define INT_SCRXFIN   (0x00000020u)

Definition at line 4395 of file regs.h.

#define INT_SCRXFIN   (0x00000020u)

Definition at line 4395 of file regs.h.

#define INT_SCRXFIN   (0x00000020u)

Definition at line 4395 of file regs.h.

#define INT_SCRXFIN   (0x00000020u)

Definition at line 4395 of file regs.h.

#define INT_SCRXFIN_BIT   (5)

Definition at line 4397 of file regs.h.

#define INT_SCRXFIN_BIT   (5)

Definition at line 4397 of file regs.h.

#define INT_SCRXFIN_BIT   (5)

Definition at line 4397 of file regs.h.

#define INT_SCRXFIN_BIT   (5)

Definition at line 4397 of file regs.h.

#define INT_SCRXFIN_BITS   (1)

Definition at line 4398 of file regs.h.

#define INT_SCRXFIN_BITS   (1)

Definition at line 4398 of file regs.h.

#define INT_SCRXFIN_BITS   (1)

Definition at line 4398 of file regs.h.

#define INT_SCRXFIN_BITS   (1)

Definition at line 4398 of file regs.h.

#define INT_SCRXFIN_MASK   (0x00000020u)

Definition at line 4396 of file regs.h.

#define INT_SCRXFIN_MASK   (0x00000020u)

Definition at line 4396 of file regs.h.

#define INT_SCRXFIN_MASK   (0x00000020u)

Definition at line 4396 of file regs.h.

#define INT_SCRXFIN_MASK   (0x00000020u)

Definition at line 4396 of file regs.h.

#define INT_SCRXOVF   (0x00000008u)

Definition at line 4405 of file regs.h.

#define INT_SCRXOVF   (0x00000008u)

Definition at line 4405 of file regs.h.

#define INT_SCRXOVF   (0x00000008u)

Definition at line 4405 of file regs.h.

#define INT_SCRXOVF   (0x00000008u)

Definition at line 4405 of file regs.h.

#define INT_SCRXOVF_BIT   (3)

Definition at line 4407 of file regs.h.

#define INT_SCRXOVF_BIT   (3)

Definition at line 4407 of file regs.h.

#define INT_SCRXOVF_BIT   (3)

Definition at line 4407 of file regs.h.

#define INT_SCRXOVF_BIT   (3)

Definition at line 4407 of file regs.h.

#define INT_SCRXOVF_BITS   (1)

Definition at line 4408 of file regs.h.

#define INT_SCRXOVF_BITS   (1)

Definition at line 4408 of file regs.h.

#define INT_SCRXOVF_BITS   (1)

Definition at line 4408 of file regs.h.

#define INT_SCRXOVF_BITS   (1)

Definition at line 4408 of file regs.h.

#define INT_SCRXOVF_MASK   (0x00000008u)

Definition at line 4406 of file regs.h.

#define INT_SCRXOVF_MASK   (0x00000008u)

Definition at line 4406 of file regs.h.

#define INT_SCRXOVF_MASK   (0x00000008u)

Definition at line 4406 of file regs.h.

#define INT_SCRXOVF_MASK   (0x00000008u)

Definition at line 4406 of file regs.h.

#define INT_SCRXULDA   (0x00000200u)

Definition at line 4375 of file regs.h.

#define INT_SCRXULDA   (0x00000200u)

Definition at line 4375 of file regs.h.

#define INT_SCRXULDA   (0x00000200u)

Definition at line 4375 of file regs.h.

#define INT_SCRXULDA   (0x00000200u)

Definition at line 4375 of file regs.h.

#define INT_SCRXULDA_BIT   (9)

Definition at line 4377 of file regs.h.

#define INT_SCRXULDA_BIT   (9)

Definition at line 4377 of file regs.h.

#define INT_SCRXULDA_BIT   (9)

Definition at line 4377 of file regs.h.

#define INT_SCRXULDA_BIT   (9)

Definition at line 4377 of file regs.h.

#define INT_SCRXULDA_BITS   (1)

Definition at line 4378 of file regs.h.

#define INT_SCRXULDA_BITS   (1)

Definition at line 4378 of file regs.h.

#define INT_SCRXULDA_BITS   (1)

Definition at line 4378 of file regs.h.

#define INT_SCRXULDA_BITS   (1)

Definition at line 4378 of file regs.h.

#define INT_SCRXULDA_MASK   (0x00000200u)

Definition at line 4376 of file regs.h.

#define INT_SCRXULDA_MASK   (0x00000200u)

Definition at line 4376 of file regs.h.

#define INT_SCRXULDA_MASK   (0x00000200u)

Definition at line 4376 of file regs.h.

#define INT_SCRXULDA_MASK   (0x00000200u)

Definition at line 4376 of file regs.h.

#define INT_SCRXULDB   (0x00000400u)

Definition at line 4370 of file regs.h.

#define INT_SCRXULDB   (0x00000400u)

Definition at line 4370 of file regs.h.

#define INT_SCRXULDB   (0x00000400u)

Definition at line 4370 of file regs.h.

#define INT_SCRXULDB   (0x00000400u)

Definition at line 4370 of file regs.h.

#define INT_SCRXULDB_BIT   (10)

Definition at line 4372 of file regs.h.

#define INT_SCRXULDB_BIT   (10)

Definition at line 4372 of file regs.h.

#define INT_SCRXULDB_BIT   (10)

Definition at line 4372 of file regs.h.

#define INT_SCRXULDB_BIT   (10)

Definition at line 4372 of file regs.h.

#define INT_SCRXULDB_BITS   (1)

Definition at line 4373 of file regs.h.

#define INT_SCRXULDB_BITS   (1)

Definition at line 4373 of file regs.h.

#define INT_SCRXULDB_BITS   (1)

Definition at line 4373 of file regs.h.

#define INT_SCRXULDB_BITS   (1)

Definition at line 4373 of file regs.h.

#define INT_SCRXULDB_MASK   (0x00000400u)

Definition at line 4371 of file regs.h.

#define INT_SCRXULDB_MASK   (0x00000400u)

Definition at line 4371 of file regs.h.

#define INT_SCRXULDB_MASK   (0x00000400u)

Definition at line 4371 of file regs.h.

#define INT_SCRXULDB_MASK   (0x00000400u)

Definition at line 4371 of file regs.h.

#define INT_SCRXVAL   (0x00000001u)

Definition at line 4420 of file regs.h.

#define INT_SCRXVAL   (0x00000001u)

Definition at line 4420 of file regs.h.

#define INT_SCRXVAL   (0x00000001u)

Definition at line 4420 of file regs.h.

#define INT_SCRXVAL   (0x00000001u)

Definition at line 4420 of file regs.h.

#define INT_SCRXVAL_BIT   (0)

Definition at line 4422 of file regs.h.

#define INT_SCRXVAL_BIT   (0)

Definition at line 4422 of file regs.h.

#define INT_SCRXVAL_BIT   (0)

Definition at line 4422 of file regs.h.

#define INT_SCRXVAL_BIT   (0)

Definition at line 4422 of file regs.h.

#define INT_SCRXVAL_BITS   (1)

Definition at line 4423 of file regs.h.

#define INT_SCRXVAL_BITS   (1)

Definition at line 4423 of file regs.h.

#define INT_SCRXVAL_BITS   (1)

Definition at line 4423 of file regs.h.

#define INT_SCRXVAL_BITS   (1)

Definition at line 4423 of file regs.h.

#define INT_SCRXVAL_MASK   (0x00000001u)

Definition at line 4421 of file regs.h.

#define INT_SCRXVAL_MASK   (0x00000001u)

Definition at line 4421 of file regs.h.

#define INT_SCRXVAL_MASK   (0x00000001u)

Definition at line 4421 of file regs.h.

#define INT_SCRXVAL_MASK   (0x00000001u)

Definition at line 4421 of file regs.h.

#define INT_SCTXFIN   (0x00000040u)

Definition at line 4390 of file regs.h.

#define INT_SCTXFIN   (0x00000040u)

Definition at line 4390 of file regs.h.

#define INT_SCTXFIN   (0x00000040u)

Definition at line 4390 of file regs.h.

#define INT_SCTXFIN   (0x00000040u)

Definition at line 4390 of file regs.h.

#define INT_SCTXFIN_BIT   (6)

Definition at line 4392 of file regs.h.

#define INT_SCTXFIN_BIT   (6)

Definition at line 4392 of file regs.h.

#define INT_SCTXFIN_BIT   (6)

Definition at line 4392 of file regs.h.

#define INT_SCTXFIN_BIT   (6)

Definition at line 4392 of file regs.h.

#define INT_SCTXFIN_BITS   (1)

Definition at line 4393 of file regs.h.

#define INT_SCTXFIN_BITS   (1)

Definition at line 4393 of file regs.h.

#define INT_SCTXFIN_BITS   (1)

Definition at line 4393 of file regs.h.

#define INT_SCTXFIN_BITS   (1)

Definition at line 4393 of file regs.h.

#define INT_SCTXFIN_MASK   (0x00000040u)

Definition at line 4391 of file regs.h.

#define INT_SCTXFIN_MASK   (0x00000040u)

Definition at line 4391 of file regs.h.

#define INT_SCTXFIN_MASK   (0x00000040u)

Definition at line 4391 of file regs.h.

#define INT_SCTXFIN_MASK   (0x00000040u)

Definition at line 4391 of file regs.h.

#define INT_SCTXFREE   (0x00000002u)

Definition at line 4415 of file regs.h.

#define INT_SCTXFREE   (0x00000002u)

Definition at line 4415 of file regs.h.

#define INT_SCTXFREE   (0x00000002u)

Definition at line 4415 of file regs.h.

#define INT_SCTXFREE   (0x00000002u)

Definition at line 4415 of file regs.h.

#define INT_SCTXFREE_BIT   (1)

Definition at line 4417 of file regs.h.

#define INT_SCTXFREE_BIT   (1)

Definition at line 4417 of file regs.h.

#define INT_SCTXFREE_BIT   (1)

Definition at line 4417 of file regs.h.

#define INT_SCTXFREE_BIT   (1)

Definition at line 4417 of file regs.h.

#define INT_SCTXFREE_BITS   (1)

Definition at line 4418 of file regs.h.

#define INT_SCTXFREE_BITS   (1)

Definition at line 4418 of file regs.h.

#define INT_SCTXFREE_BITS   (1)

Definition at line 4418 of file regs.h.

#define INT_SCTXFREE_BITS   (1)

Definition at line 4418 of file regs.h.

#define INT_SCTXFREE_MASK   (0x00000002u)

Definition at line 4416 of file regs.h.

#define INT_SCTXFREE_MASK   (0x00000002u)

Definition at line 4416 of file regs.h.

#define INT_SCTXFREE_MASK   (0x00000002u)

Definition at line 4416 of file regs.h.

#define INT_SCTXFREE_MASK   (0x00000002u)

Definition at line 4416 of file regs.h.

#define INT_SCTXIDLE   (0x00000004u)

Definition at line 4410 of file regs.h.

#define INT_SCTXIDLE   (0x00000004u)

Definition at line 4410 of file regs.h.

#define INT_SCTXIDLE   (0x00000004u)

Definition at line 4410 of file regs.h.

#define INT_SCTXIDLE   (0x00000004u)

Definition at line 4410 of file regs.h.

#define INT_SCTXIDLE_BIT   (2)

Definition at line 4412 of file regs.h.

#define INT_SCTXIDLE_BIT   (2)

Definition at line 4412 of file regs.h.

#define INT_SCTXIDLE_BIT   (2)

Definition at line 4412 of file regs.h.

#define INT_SCTXIDLE_BIT   (2)

Definition at line 4412 of file regs.h.

#define INT_SCTXIDLE_BITS   (1)

Definition at line 4413 of file regs.h.

#define INT_SCTXIDLE_BITS   (1)

Definition at line 4413 of file regs.h.

#define INT_SCTXIDLE_BITS   (1)

Definition at line 4413 of file regs.h.

#define INT_SCTXIDLE_BITS   (1)

Definition at line 4413 of file regs.h.

#define INT_SCTXIDLE_MASK   (0x00000004u)

Definition at line 4411 of file regs.h.

#define INT_SCTXIDLE_MASK   (0x00000004u)

Definition at line 4411 of file regs.h.

#define INT_SCTXIDLE_MASK   (0x00000004u)

Definition at line 4411 of file regs.h.

#define INT_SCTXIDLE_MASK   (0x00000004u)

Definition at line 4411 of file regs.h.

#define INT_SCTXULDA   (0x00000800u)

Definition at line 4365 of file regs.h.

#define INT_SCTXULDA   (0x00000800u)

Definition at line 4365 of file regs.h.

#define INT_SCTXULDA   (0x00000800u)

Definition at line 4365 of file regs.h.

#define INT_SCTXULDA   (0x00000800u)

Definition at line 4365 of file regs.h.

#define INT_SCTXULDA_BIT   (11)

Definition at line 4367 of file regs.h.

#define INT_SCTXULDA_BIT   (11)

Definition at line 4367 of file regs.h.

#define INT_SCTXULDA_BIT   (11)

Definition at line 4367 of file regs.h.

#define INT_SCTXULDA_BIT   (11)

Definition at line 4367 of file regs.h.

#define INT_SCTXULDA_BITS   (1)

Definition at line 4368 of file regs.h.

#define INT_SCTXULDA_BITS   (1)

Definition at line 4368 of file regs.h.

#define INT_SCTXULDA_BITS   (1)

Definition at line 4368 of file regs.h.

#define INT_SCTXULDA_BITS   (1)

Definition at line 4368 of file regs.h.

#define INT_SCTXULDA_MASK   (0x00000800u)

Definition at line 4366 of file regs.h.

#define INT_SCTXULDA_MASK   (0x00000800u)

Definition at line 4366 of file regs.h.

#define INT_SCTXULDA_MASK   (0x00000800u)

Definition at line 4366 of file regs.h.

#define INT_SCTXULDA_MASK   (0x00000800u)

Definition at line 4366 of file regs.h.

#define INT_SCTXULDB   (0x00001000u)

Definition at line 4360 of file regs.h.

#define INT_SCTXULDB   (0x00001000u)

Definition at line 4360 of file regs.h.

#define INT_SCTXULDB   (0x00001000u)

Definition at line 4360 of file regs.h.

#define INT_SCTXULDB   (0x00001000u)

Definition at line 4360 of file regs.h.

#define INT_SCTXULDB_BIT   (12)

Definition at line 4362 of file regs.h.

#define INT_SCTXULDB_BIT   (12)

Definition at line 4362 of file regs.h.

#define INT_SCTXULDB_BIT   (12)

Definition at line 4362 of file regs.h.

#define INT_SCTXULDB_BIT   (12)

Definition at line 4362 of file regs.h.

#define INT_SCTXULDB_BITS   (1)

Definition at line 4363 of file regs.h.

#define INT_SCTXULDB_BITS   (1)

Definition at line 4363 of file regs.h.

#define INT_SCTXULDB_BITS   (1)

Definition at line 4363 of file regs.h.

#define INT_SCTXULDB_BITS   (1)

Definition at line 4363 of file regs.h.

#define INT_SCTXULDB_MASK   (0x00001000u)

Definition at line 4361 of file regs.h.

#define INT_SCTXULDB_MASK   (0x00001000u)

Definition at line 4361 of file regs.h.

#define INT_SCTXULDB_MASK   (0x00001000u)

Definition at line 4361 of file regs.h.

#define INT_SCTXULDB_MASK   (0x00001000u)

Definition at line 4361 of file regs.h.

#define INT_SCTXUND   (0x00000010u)

Definition at line 4400 of file regs.h.

#define INT_SCTXUND   (0x00000010u)

Definition at line 4400 of file regs.h.

#define INT_SCTXUND   (0x00000010u)

Definition at line 4400 of file regs.h.

#define INT_SCTXUND   (0x00000010u)

Definition at line 4400 of file regs.h.

#define INT_SCTXUND_BIT   (4)

Definition at line 4402 of file regs.h.

#define INT_SCTXUND_BIT   (4)

Definition at line 4402 of file regs.h.

#define INT_SCTXUND_BIT   (4)

Definition at line 4402 of file regs.h.

#define INT_SCTXUND_BIT   (4)

Definition at line 4402 of file regs.h.

#define INT_SCTXUND_BITS   (1)

Definition at line 4403 of file regs.h.

#define INT_SCTXUND_BITS   (1)

Definition at line 4403 of file regs.h.

#define INT_SCTXUND_BITS   (1)

Definition at line 4403 of file regs.h.

#define INT_SCTXUND_BITS   (1)

Definition at line 4403 of file regs.h.

#define INT_SCTXUND_MASK   (0x00000010u)

Definition at line 4401 of file regs.h.

#define INT_SCTXUND_MASK   (0x00000010u)

Definition at line 4401 of file regs.h.

#define INT_SCTXUND_MASK   (0x00000010u)

Definition at line 4401 of file regs.h.

#define INT_SCTXUND_MASK   (0x00000010u)

Definition at line 4401 of file regs.h.

#define INT_SEC   (0x00000080u)

Definition at line 9680 of file regs.h.

#define INT_SEC   (0x00000080u)

Definition at line 9680 of file regs.h.

#define INT_SEC   (0x00000080u)

Definition at line 9680 of file regs.h.

#define INT_SEC   (0x00000080u)

Definition at line 9680 of file regs.h.

#define INT_SEC   (0x00000080u)

Definition at line 9680 of file regs.h.

#define INT_SEC_BIT   (7)

Definition at line 9682 of file regs.h.

#define INT_SEC_BIT   (7)

Definition at line 9682 of file regs.h.

#define INT_SEC_BIT   (7)

Definition at line 9682 of file regs.h.

#define INT_SEC_BIT   (7)

Definition at line 9682 of file regs.h.

#define INT_SEC_BIT   (7)

Definition at line 9682 of file regs.h.

#define INT_SEC_BITS   (1)

Definition at line 9683 of file regs.h.

#define INT_SEC_BITS   (1)

Definition at line 9683 of file regs.h.

#define INT_SEC_BITS   (1)

Definition at line 9683 of file regs.h.

#define INT_SEC_BITS   (1)

Definition at line 9683 of file regs.h.

#define INT_SEC_BITS   (1)

Definition at line 9683 of file regs.h.

#define INT_SEC_MASK   (0x00000080u)

Definition at line 9681 of file regs.h.

#define INT_SEC_MASK   (0x00000080u)

Definition at line 9681 of file regs.h.

#define INT_SEC_MASK   (0x00000080u)

Definition at line 9681 of file regs.h.

#define INT_SEC_MASK   (0x00000080u)

Definition at line 9681 of file regs.h.

#define INT_SEC_MASK   (0x00000080u)

Definition at line 9681 of file regs.h.

#define INT_SLEEPTMR   (0x00000010u)

Definition at line 9695 of file regs.h.

#define INT_SLEEPTMR   (0x00000010u)

Definition at line 9695 of file regs.h.

#define INT_SLEEPTMR   (0x00000010u)

Definition at line 9695 of file regs.h.

#define INT_SLEEPTMR   (0x00000010u)

Definition at line 9695 of file regs.h.

#define INT_SLEEPTMR   (0x00000010u)

Definition at line 9695 of file regs.h.

#define INT_SLEEPTMR_BIT   (4)

Definition at line 9697 of file regs.h.

#define INT_SLEEPTMR_BIT   (4)

Definition at line 9697 of file regs.h.

#define INT_SLEEPTMR_BIT   (4)

Definition at line 9697 of file regs.h.

#define INT_SLEEPTMR_BIT   (4)

Definition at line 9697 of file regs.h.

#define INT_SLEEPTMR_BIT   (4)

Definition at line 9697 of file regs.h.

#define INT_SLEEPTMR_BITS   (1)

Definition at line 9698 of file regs.h.

#define INT_SLEEPTMR_BITS   (1)

Definition at line 9698 of file regs.h.

#define INT_SLEEPTMR_BITS   (1)

Definition at line 9698 of file regs.h.

#define INT_SLEEPTMR_BITS   (1)

Definition at line 9698 of file regs.h.

#define INT_SLEEPTMR_BITS   (1)

Definition at line 9698 of file regs.h.

#define INT_SLEEPTMR_MASK   (0x00000010u)

Definition at line 9696 of file regs.h.

#define INT_SLEEPTMR_MASK   (0x00000010u)

Definition at line 9696 of file regs.h.

#define INT_SLEEPTMR_MASK   (0x00000010u)

Definition at line 9696 of file regs.h.

#define INT_SLEEPTMR_MASK   (0x00000010u)

Definition at line 9696 of file regs.h.

#define INT_SLEEPTMR_MASK   (0x00000010u)

Definition at line 9696 of file regs.h.

#define INT_SLEEPTMRCFG   *((volatile int32u *)0x4000A054u)

Definition at line 3735 of file regs.h.

#define INT_SLEEPTMRCFG_ADDR   (0x4000A054u)

Definition at line 3737 of file regs.h.

#define INT_SLEEPTMRCFG_REG   *((volatile int32u *)0x4000A054u)

Definition at line 3736 of file regs.h.

#define INT_SLEEPTMRCFG_RESET   (0x00000000u)

Definition at line 3738 of file regs.h.

#define INT_SLEEPTMRCMPA   (0x00000002u)

Definition at line 3745 of file regs.h.

#define INT_SLEEPTMRCMPA   (0x00000002u)

Definition at line 3745 of file regs.h.

#define INT_SLEEPTMRCMPA   (0x00000002u)

Definition at line 3745 of file regs.h.

#define INT_SLEEPTMRCMPA_BIT   (1)

Definition at line 3747 of file regs.h.

#define INT_SLEEPTMRCMPA_BIT   (1)

Definition at line 3747 of file regs.h.

#define INT_SLEEPTMRCMPA_BIT   (1)

Definition at line 3747 of file regs.h.

#define INT_SLEEPTMRCMPA_BITS   (1)

Definition at line 3748 of file regs.h.

#define INT_SLEEPTMRCMPA_BITS   (1)

Definition at line 3748 of file regs.h.

#define INT_SLEEPTMRCMPA_BITS   (1)

Definition at line 3748 of file regs.h.

#define INT_SLEEPTMRCMPA_MASK   (0x00000002u)

Definition at line 3746 of file regs.h.

#define INT_SLEEPTMRCMPA_MASK   (0x00000002u)

Definition at line 3746 of file regs.h.

#define INT_SLEEPTMRCMPA_MASK   (0x00000002u)

Definition at line 3746 of file regs.h.

#define INT_SLEEPTMRCMPB   (0x00000004u)

Definition at line 3740 of file regs.h.

#define INT_SLEEPTMRCMPB   (0x00000004u)

Definition at line 3740 of file regs.h.

#define INT_SLEEPTMRCMPB   (0x00000004u)

Definition at line 3740 of file regs.h.

#define INT_SLEEPTMRCMPB_BIT   (2)

Definition at line 3742 of file regs.h.

#define INT_SLEEPTMRCMPB_BIT   (2)

Definition at line 3742 of file regs.h.

#define INT_SLEEPTMRCMPB_BIT   (2)

Definition at line 3742 of file regs.h.

#define INT_SLEEPTMRCMPB_BITS   (1)

Definition at line 3743 of file regs.h.

#define INT_SLEEPTMRCMPB_BITS   (1)

Definition at line 3743 of file regs.h.

#define INT_SLEEPTMRCMPB_BITS   (1)

Definition at line 3743 of file regs.h.

#define INT_SLEEPTMRCMPB_MASK   (0x00000004u)

Definition at line 3741 of file regs.h.

#define INT_SLEEPTMRCMPB_MASK   (0x00000004u)

Definition at line 3741 of file regs.h.

#define INT_SLEEPTMRCMPB_MASK   (0x00000004u)

Definition at line 3741 of file regs.h.

#define INT_SLEEPTMRFLAG   *((volatile int32u *)0x4000A014u)

Definition at line 3435 of file regs.h.

#define INT_SLEEPTMRFLAG_ADDR   (0x4000A014u)

Definition at line 3437 of file regs.h.

#define INT_SLEEPTMRFLAG_REG   *((volatile int32u *)0x4000A014u)

Definition at line 3436 of file regs.h.

#define INT_SLEEPTMRFLAG_RESET   (0x00000000u)

Definition at line 3438 of file regs.h.

#define INT_SLEEPTMRFORCE   *((volatile int32u *)0x4000A020u)

Definition at line 3500 of file regs.h.

#define INT_SLEEPTMRFORCE_ADDR   (0x4000A020u)

Definition at line 3502 of file regs.h.

#define INT_SLEEPTMRFORCE_REG   *((volatile int32u *)0x4000A020u)

Definition at line 3501 of file regs.h.

#define INT_SLEEPTMRFORCE_RESET   (0x00000000u)

Definition at line 3503 of file regs.h.

#define INT_SLEEPTMRWRAP   (0x00000001u)

Definition at line 3750 of file regs.h.

#define INT_SLEEPTMRWRAP   (0x00000001u)

Definition at line 3750 of file regs.h.

#define INT_SLEEPTMRWRAP   (0x00000001u)

Definition at line 3750 of file regs.h.

#define INT_SLEEPTMRWRAP_BIT   (0)

Definition at line 3752 of file regs.h.

#define INT_SLEEPTMRWRAP_BIT   (0)

Definition at line 3752 of file regs.h.

#define INT_SLEEPTMRWRAP_BIT   (0)

Definition at line 3752 of file regs.h.

#define INT_SLEEPTMRWRAP_BITS   (1)

Definition at line 3753 of file regs.h.

#define INT_SLEEPTMRWRAP_BITS   (1)

Definition at line 3753 of file regs.h.

#define INT_SLEEPTMRWRAP_BITS   (1)

Definition at line 3753 of file regs.h.

#define INT_SLEEPTMRWRAP_MASK   (0x00000001u)

Definition at line 3751 of file regs.h.

#define INT_SLEEPTMRWRAP_MASK   (0x00000001u)

Definition at line 3751 of file regs.h.

#define INT_SLEEPTMRWRAP_MASK   (0x00000001u)

Definition at line 3751 of file regs.h.

#define INT_TIM1   (0x00000001u)

Definition at line 9715 of file regs.h.

#define INT_TIM1   (0x00000001u)

Definition at line 9715 of file regs.h.

#define INT_TIM1   (0x00000001u)

Definition at line 9715 of file regs.h.

#define INT_TIM1   (0x00000001u)

Definition at line 9715 of file regs.h.

#define INT_TIM1   (0x00000001u)

Definition at line 9715 of file regs.h.

#define INT_TIM1_BIT   (0)

Definition at line 9717 of file regs.h.

#define INT_TIM1_BIT   (0)

Definition at line 9717 of file regs.h.

#define INT_TIM1_BIT   (0)

Definition at line 9717 of file regs.h.

#define INT_TIM1_BIT   (0)

Definition at line 9717 of file regs.h.

#define INT_TIM1_BIT   (0)

Definition at line 9717 of file regs.h.

#define INT_TIM1_BITS   (1)

Definition at line 9718 of file regs.h.

#define INT_TIM1_BITS   (1)

Definition at line 9718 of file regs.h.

#define INT_TIM1_BITS   (1)

Definition at line 9718 of file regs.h.

#define INT_TIM1_BITS   (1)

Definition at line 9718 of file regs.h.

#define INT_TIM1_BITS   (1)

Definition at line 9718 of file regs.h.

#define INT_TIM1_MASK   (0x00000001u)

Definition at line 9716 of file regs.h.

#define INT_TIM1_MASK   (0x00000001u)

Definition at line 9716 of file regs.h.

#define INT_TIM1_MASK   (0x00000001u)

Definition at line 9716 of file regs.h.

#define INT_TIM1_MASK   (0x00000001u)

Definition at line 9716 of file regs.h.

#define INT_TIM1_MASK   (0x00000001u)

Definition at line 9716 of file regs.h.

#define INT_TIM1CFG   *((volatile int32u *)0x4000A840u)

Definition at line 4205 of file regs.h.

#define INT_TIM1CFG_ADDR   (0x4000A840u)

Definition at line 4207 of file regs.h.

#define INT_TIM1CFG_REG   *((volatile int32u *)0x4000A840u)

Definition at line 4206 of file regs.h.

#define INT_TIM1CFG_RESET   (0x00000000u)

Definition at line 4208 of file regs.h.

#define INT_TIM1FLAG   *((volatile int32u *)0x4000A800u)

Definition at line 3785 of file regs.h.

#define INT_TIM1FLAG_ADDR   (0x4000A800u)

Definition at line 3787 of file regs.h.

#define INT_TIM1FLAG_REG   *((volatile int32u *)0x4000A800u)

Definition at line 3786 of file regs.h.

#define INT_TIM1FLAG_RESET   (0x00000000u)

Definition at line 3788 of file regs.h.

#define INT_TIM1MISS   *((volatile int32u *)0x4000A818u)

Definition at line 4070 of file regs.h.

#define INT_TIM1MISS_ADDR   (0x4000A818u)

Definition at line 4072 of file regs.h.

#define INT_TIM1MISS_REG   *((volatile int32u *)0x4000A818u)

Definition at line 4071 of file regs.h.

#define INT_TIM1MISS_RESET   (0x00000000u)

Definition at line 4073 of file regs.h.

#define INT_TIM2   (0x00000002u)

Definition at line 9710 of file regs.h.

#define INT_TIM2   (0x00000002u)

Definition at line 9710 of file regs.h.

#define INT_TIM2   (0x00000002u)

Definition at line 9710 of file regs.h.

#define INT_TIM2   (0x00000002u)

Definition at line 9710 of file regs.h.

#define INT_TIM2   (0x00000002u)

Definition at line 9710 of file regs.h.

#define INT_TIM2_BIT   (1)

Definition at line 9712 of file regs.h.

#define INT_TIM2_BIT   (1)

Definition at line 9712 of file regs.h.

#define INT_TIM2_BIT   (1)

Definition at line 9712 of file regs.h.

#define INT_TIM2_BIT   (1)

Definition at line 9712 of file regs.h.

#define INT_TIM2_BIT   (1)

Definition at line 9712 of file regs.h.

#define INT_TIM2_BITS   (1)

Definition at line 9713 of file regs.h.

#define INT_TIM2_BITS   (1)

Definition at line 9713 of file regs.h.

#define INT_TIM2_BITS   (1)

Definition at line 9713 of file regs.h.

#define INT_TIM2_BITS   (1)

Definition at line 9713 of file regs.h.

#define INT_TIM2_BITS   (1)

Definition at line 9713 of file regs.h.

#define INT_TIM2_MASK   (0x00000002u)

Definition at line 9711 of file regs.h.

#define INT_TIM2_MASK   (0x00000002u)

Definition at line 9711 of file regs.h.

#define INT_TIM2_MASK   (0x00000002u)

Definition at line 9711 of file regs.h.

#define INT_TIM2_MASK   (0x00000002u)

Definition at line 9711 of file regs.h.

#define INT_TIM2_MASK   (0x00000002u)

Definition at line 9711 of file regs.h.

#define INT_TIM2CFG   *((volatile int32u *)0x4000A844u)

Definition at line 4240 of file regs.h.

#define INT_TIM2CFG_ADDR   (0x4000A844u)

Definition at line 4242 of file regs.h.

#define INT_TIM2CFG_REG   *((volatile int32u *)0x4000A844u)

Definition at line 4241 of file regs.h.

#define INT_TIM2CFG_RESET   (0x00000000u)

Definition at line 4243 of file regs.h.

#define INT_TIM2FLAG   *((volatile int32u *)0x4000A804u)

Definition at line 3825 of file regs.h.

#define INT_TIM2FLAG_ADDR   (0x4000A804u)

Definition at line 3827 of file regs.h.

#define INT_TIM2FLAG_REG   *((volatile int32u *)0x4000A804u)

Definition at line 3826 of file regs.h.

#define INT_TIM2FLAG_RESET   (0x00000000u)

Definition at line 3828 of file regs.h.

#define INT_TIM2MISS   *((volatile int32u *)0x4000A81Cu)

Definition at line 4100 of file regs.h.

#define INT_TIM2MISS_ADDR   (0x4000A81Cu)

Definition at line 4102 of file regs.h.

#define INT_TIM2MISS_REG   *((volatile int32u *)0x4000A81Cu)

Definition at line 4101 of file regs.h.

#define INT_TIM2MISS_RESET   (0x00000000u)

Definition at line 4103 of file regs.h.

#define INT_TIMCC1IF   (0x00000002u)

Definition at line 4265 of file regs.h.

#define INT_TIMCC1IF   (0x00000002u)

Definition at line 4265 of file regs.h.

#define INT_TIMCC1IF   (0x00000002u)

Definition at line 4265 of file regs.h.

#define INT_TIMCC1IF   (0x00000002u)

Definition at line 4265 of file regs.h.

#define INT_TIMCC1IF_BIT   (1)

Definition at line 4267 of file regs.h.

#define INT_TIMCC1IF_BIT   (1)

Definition at line 4267 of file regs.h.

#define INT_TIMCC1IF_BIT   (1)

Definition at line 4267 of file regs.h.

#define INT_TIMCC1IF_BIT   (1)

Definition at line 4267 of file regs.h.

#define INT_TIMCC1IF_BITS   (1)

Definition at line 4268 of file regs.h.

#define INT_TIMCC1IF_BITS   (1)

Definition at line 4268 of file regs.h.

#define INT_TIMCC1IF_BITS   (1)

Definition at line 4268 of file regs.h.

#define INT_TIMCC1IF_BITS   (1)

Definition at line 4268 of file regs.h.

#define INT_TIMCC1IF_MASK   (0x00000002u)

Definition at line 4266 of file regs.h.

#define INT_TIMCC1IF_MASK   (0x00000002u)

Definition at line 4266 of file regs.h.

#define INT_TIMCC1IF_MASK   (0x00000002u)

Definition at line 4266 of file regs.h.

#define INT_TIMCC1IF_MASK   (0x00000002u)

Definition at line 4266 of file regs.h.

#define INT_TIMCC2IF   (0x00000004u)

Definition at line 4260 of file regs.h.

#define INT_TIMCC2IF   (0x00000004u)

Definition at line 4260 of file regs.h.

#define INT_TIMCC2IF   (0x00000004u)

Definition at line 4260 of file regs.h.

#define INT_TIMCC2IF   (0x00000004u)

Definition at line 4260 of file regs.h.

#define INT_TIMCC2IF_BIT   (2)

Definition at line 4262 of file regs.h.

#define INT_TIMCC2IF_BIT   (2)

Definition at line 4262 of file regs.h.

#define INT_TIMCC2IF_BIT   (2)

Definition at line 4262 of file regs.h.

#define INT_TIMCC2IF_BIT   (2)

Definition at line 4262 of file regs.h.

#define INT_TIMCC2IF_BITS   (1)

Definition at line 4263 of file regs.h.

#define INT_TIMCC2IF_BITS   (1)

Definition at line 4263 of file regs.h.

#define INT_TIMCC2IF_BITS   (1)

Definition at line 4263 of file regs.h.

#define INT_TIMCC2IF_BITS   (1)

Definition at line 4263 of file regs.h.

#define INT_TIMCC2IF_MASK   (0x00000004u)

Definition at line 4261 of file regs.h.

#define INT_TIMCC2IF_MASK   (0x00000004u)

Definition at line 4261 of file regs.h.

#define INT_TIMCC2IF_MASK   (0x00000004u)

Definition at line 4261 of file regs.h.

#define INT_TIMCC2IF_MASK   (0x00000004u)

Definition at line 4261 of file regs.h.

#define INT_TIMCC3IF   (0x00000008u)

Definition at line 4255 of file regs.h.

#define INT_TIMCC3IF   (0x00000008u)

Definition at line 4255 of file regs.h.

#define INT_TIMCC3IF   (0x00000008u)

Definition at line 4255 of file regs.h.

#define INT_TIMCC3IF   (0x00000008u)

Definition at line 4255 of file regs.h.

#define INT_TIMCC3IF_BIT   (3)

Definition at line 4257 of file regs.h.

#define INT_TIMCC3IF_BIT   (3)

Definition at line 4257 of file regs.h.

#define INT_TIMCC3IF_BIT   (3)

Definition at line 4257 of file regs.h.

#define INT_TIMCC3IF_BIT   (3)

Definition at line 4257 of file regs.h.

#define INT_TIMCC3IF_BITS   (1)

Definition at line 4258 of file regs.h.

#define INT_TIMCC3IF_BITS   (1)

Definition at line 4258 of file regs.h.

#define INT_TIMCC3IF_BITS   (1)

Definition at line 4258 of file regs.h.

#define INT_TIMCC3IF_BITS   (1)

Definition at line 4258 of file regs.h.

#define INT_TIMCC3IF_MASK   (0x00000008u)

Definition at line 4256 of file regs.h.

#define INT_TIMCC3IF_MASK   (0x00000008u)

Definition at line 4256 of file regs.h.

#define INT_TIMCC3IF_MASK   (0x00000008u)

Definition at line 4256 of file regs.h.

#define INT_TIMCC3IF_MASK   (0x00000008u)

Definition at line 4256 of file regs.h.

#define INT_TIMCC4IF   (0x00000010u)

Definition at line 4250 of file regs.h.

#define INT_TIMCC4IF   (0x00000010u)

Definition at line 4250 of file regs.h.

#define INT_TIMCC4IF   (0x00000010u)

Definition at line 4250 of file regs.h.

#define INT_TIMCC4IF   (0x00000010u)

Definition at line 4250 of file regs.h.

#define INT_TIMCC4IF_BIT   (4)

Definition at line 4252 of file regs.h.

#define INT_TIMCC4IF_BIT   (4)

Definition at line 4252 of file regs.h.

#define INT_TIMCC4IF_BIT   (4)

Definition at line 4252 of file regs.h.

#define INT_TIMCC4IF_BIT   (4)

Definition at line 4252 of file regs.h.

#define INT_TIMCC4IF_BITS   (1)

Definition at line 4253 of file regs.h.

#define INT_TIMCC4IF_BITS   (1)

Definition at line 4253 of file regs.h.

#define INT_TIMCC4IF_BITS   (1)

Definition at line 4253 of file regs.h.

#define INT_TIMCC4IF_BITS   (1)

Definition at line 4253 of file regs.h.

#define INT_TIMCC4IF_MASK   (0x00000010u)

Definition at line 4251 of file regs.h.

#define INT_TIMCC4IF_MASK   (0x00000010u)

Definition at line 4251 of file regs.h.

#define INT_TIMCC4IF_MASK   (0x00000010u)

Definition at line 4251 of file regs.h.

#define INT_TIMCC4IF_MASK   (0x00000010u)

Definition at line 4251 of file regs.h.

#define INT_TIMMISSCC1IF   (0x00000200u)

Definition at line 4120 of file regs.h.

#define INT_TIMMISSCC1IF   (0x00000200u)

Definition at line 4120 of file regs.h.

#define INT_TIMMISSCC1IF_BIT   (9)

Definition at line 4122 of file regs.h.

#define INT_TIMMISSCC1IF_BIT   (9)

Definition at line 4122 of file regs.h.

#define INT_TIMMISSCC1IF_BITS   (1)

Definition at line 4123 of file regs.h.

#define INT_TIMMISSCC1IF_BITS   (1)

Definition at line 4123 of file regs.h.

#define INT_TIMMISSCC1IF_MASK   (0x00000200u)

Definition at line 4121 of file regs.h.

#define INT_TIMMISSCC1IF_MASK   (0x00000200u)

Definition at line 4121 of file regs.h.

#define INT_TIMMISSCC2IF   (0x00000400u)

Definition at line 4115 of file regs.h.

#define INT_TIMMISSCC2IF   (0x00000400u)

Definition at line 4115 of file regs.h.

#define INT_TIMMISSCC2IF_BIT   (10)

Definition at line 4117 of file regs.h.

#define INT_TIMMISSCC2IF_BIT   (10)

Definition at line 4117 of file regs.h.

#define INT_TIMMISSCC2IF_BITS   (1)

Definition at line 4118 of file regs.h.

#define INT_TIMMISSCC2IF_BITS   (1)

Definition at line 4118 of file regs.h.

#define INT_TIMMISSCC2IF_MASK   (0x00000400u)

Definition at line 4116 of file regs.h.

#define INT_TIMMISSCC2IF_MASK   (0x00000400u)

Definition at line 4116 of file regs.h.

#define INT_TIMMISSCC3IF   (0x00000800u)

Definition at line 4110 of file regs.h.

#define INT_TIMMISSCC3IF   (0x00000800u)

Definition at line 4110 of file regs.h.

#define INT_TIMMISSCC3IF_BIT   (11)

Definition at line 4112 of file regs.h.

#define INT_TIMMISSCC3IF_BIT   (11)

Definition at line 4112 of file regs.h.

#define INT_TIMMISSCC3IF_BITS   (1)

Definition at line 4113 of file regs.h.

#define INT_TIMMISSCC3IF_BITS   (1)

Definition at line 4113 of file regs.h.

#define INT_TIMMISSCC3IF_MASK   (0x00000800u)

Definition at line 4111 of file regs.h.

#define INT_TIMMISSCC3IF_MASK   (0x00000800u)

Definition at line 4111 of file regs.h.

#define INT_TIMMISSCC4IF   (0x00001000u)

Definition at line 4105 of file regs.h.

#define INT_TIMMISSCC4IF   (0x00001000u)

Definition at line 4105 of file regs.h.

#define INT_TIMMISSCC4IF_BIT   (12)

Definition at line 4107 of file regs.h.

#define INT_TIMMISSCC4IF_BIT   (12)

Definition at line 4107 of file regs.h.

#define INT_TIMMISSCC4IF_BITS   (1)

Definition at line 4108 of file regs.h.

#define INT_TIMMISSCC4IF_BITS   (1)

Definition at line 4108 of file regs.h.

#define INT_TIMMISSCC4IF_MASK   (0x00001000u)

Definition at line 4106 of file regs.h.

#define INT_TIMMISSCC4IF_MASK   (0x00001000u)

Definition at line 4106 of file regs.h.

#define INT_TIMMISSRSVD   (0x0000007Fu)

Definition at line 4125 of file regs.h.

#define INT_TIMMISSRSVD   (0x0000007Fu)

Definition at line 4125 of file regs.h.

#define INT_TIMMISSRSVD_BIT   (0)

Definition at line 4127 of file regs.h.

#define INT_TIMMISSRSVD_BIT   (0)

Definition at line 4127 of file regs.h.

#define INT_TIMMISSRSVD_BITS   (7)

Definition at line 4128 of file regs.h.

#define INT_TIMMISSRSVD_BITS   (7)

Definition at line 4128 of file regs.h.

#define INT_TIMMISSRSVD_MASK   (0x0000007Fu)

Definition at line 4126 of file regs.h.

#define INT_TIMMISSRSVD_MASK   (0x0000007Fu)

Definition at line 4126 of file regs.h.

#define INT_TIMRSVD   (0x00001E00u)

Definition at line 3830 of file regs.h.

#define INT_TIMRSVD   (0x00001E00u)

Definition at line 3830 of file regs.h.

#define INT_TIMRSVD_BIT   (9)

Definition at line 3832 of file regs.h.

#define INT_TIMRSVD_BIT   (9)

Definition at line 3832 of file regs.h.

#define INT_TIMRSVD_BITS   (4)

Definition at line 3833 of file regs.h.

#define INT_TIMRSVD_BITS   (4)

Definition at line 3833 of file regs.h.

#define INT_TIMRSVD_MASK   (0x00001E00u)

Definition at line 3831 of file regs.h.

#define INT_TIMRSVD_MASK   (0x00001E00u)

Definition at line 3831 of file regs.h.

#define INT_TIMTIF   (0x00000040u)

Definition at line 4245 of file regs.h.

#define INT_TIMTIF   (0x00000040u)

Definition at line 4245 of file regs.h.

#define INT_TIMTIF   (0x00000040u)

Definition at line 4245 of file regs.h.

#define INT_TIMTIF   (0x00000040u)

Definition at line 4245 of file regs.h.

#define INT_TIMTIF_BIT   (6)

Definition at line 4247 of file regs.h.

#define INT_TIMTIF_BIT   (6)

Definition at line 4247 of file regs.h.

#define INT_TIMTIF_BIT   (6)

Definition at line 4247 of file regs.h.

#define INT_TIMTIF_BIT   (6)

Definition at line 4247 of file regs.h.

#define INT_TIMTIF_BITS   (1)

Definition at line 4248 of file regs.h.

#define INT_TIMTIF_BITS   (1)

Definition at line 4248 of file regs.h.

#define INT_TIMTIF_BITS   (1)

Definition at line 4248 of file regs.h.

#define INT_TIMTIF_BITS   (1)

Definition at line 4248 of file regs.h.

#define INT_TIMTIF_MASK   (0x00000040u)

Definition at line 4246 of file regs.h.

#define INT_TIMTIF_MASK   (0x00000040u)

Definition at line 4246 of file regs.h.

#define INT_TIMTIF_MASK   (0x00000040u)

Definition at line 4246 of file regs.h.

#define INT_TIMTIF_MASK   (0x00000040u)

Definition at line 4246 of file regs.h.

#define INT_TIMUIF   (0x00000001u)

Definition at line 4270 of file regs.h.

#define INT_TIMUIF   (0x00000001u)

Definition at line 4270 of file regs.h.

#define INT_TIMUIF   (0x00000001u)

Definition at line 4270 of file regs.h.

#define INT_TIMUIF   (0x00000001u)

Definition at line 4270 of file regs.h.

#define INT_TIMUIF_BIT   (0)

Definition at line 4272 of file regs.h.

#define INT_TIMUIF_BIT   (0)

Definition at line 4272 of file regs.h.

#define INT_TIMUIF_BIT   (0)

Definition at line 4272 of file regs.h.

#define INT_TIMUIF_BIT   (0)

Definition at line 4272 of file regs.h.

#define INT_TIMUIF_BITS   (1)

Definition at line 4273 of file regs.h.

#define INT_TIMUIF_BITS   (1)

Definition at line 4273 of file regs.h.

#define INT_TIMUIF_BITS   (1)

Definition at line 4273 of file regs.h.

#define INT_TIMUIF_BITS   (1)

Definition at line 4273 of file regs.h.

#define INT_TIMUIF_MASK   (0x00000001u)

Definition at line 4271 of file regs.h.

#define INT_TIMUIF_MASK   (0x00000001u)

Definition at line 4271 of file regs.h.

#define INT_TIMUIF_MASK   (0x00000001u)

Definition at line 4271 of file regs.h.

#define INT_TIMUIF_MASK   (0x00000001u)

Definition at line 4271 of file regs.h.

#define IRQD_WAKE_FILTER   (0x00000008u)

Definition at line 5476 of file regs.h.

#define IRQD_WAKE_FILTER_BIT   (3)

Definition at line 5478 of file regs.h.

#define IRQD_WAKE_FILTER_BITS   (1)

Definition at line 5479 of file regs.h.

#define IRQD_WAKE_FILTER_MASK   (0x00000008u)

Definition at line 5477 of file regs.h.

#define ITM_CELLID0   *((volatile int32u *)0xE0000FF0u)

Definition at line 8365 of file regs.h.

#define ITM_CELLID0_ADDR   (0xE0000FF0u)

Definition at line 8367 of file regs.h.

#define ITM_CELLID0_PERIPHID   (0xFFFFFFFFu)

Definition at line 8370 of file regs.h.

#define ITM_CELLID0_PERIPHID_BIT   (0)

Definition at line 8372 of file regs.h.

#define ITM_CELLID0_PERIPHID_BITS   (32)

Definition at line 8373 of file regs.h.

#define ITM_CELLID0_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 8371 of file regs.h.

#define ITM_CELLID0_REG   *((volatile int32u *)0xE0000FF0u)

Definition at line 8366 of file regs.h.

#define ITM_CELLID0_RESET   (0x0000000Du)

Definition at line 8368 of file regs.h.

#define ITM_CELLID1   *((volatile int32u *)0xE0000FF4u)

Definition at line 8375 of file regs.h.

#define ITM_CELLID1_ADDR   (0xE0000FF4u)

Definition at line 8377 of file regs.h.

#define ITM_CELLID1_PERIPHID   (0xFFFFFFFFu)

Definition at line 8380 of file regs.h.

#define ITM_CELLID1_PERIPHID_BIT   (0)

Definition at line 8382 of file regs.h.

#define ITM_CELLID1_PERIPHID_BITS   (32)

Definition at line 8383 of file regs.h.

#define ITM_CELLID1_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 8381 of file regs.h.

#define ITM_CELLID1_REG   *((volatile int32u *)0xE0000FF4u)

Definition at line 8376 of file regs.h.

#define ITM_CELLID1_RESET   (0x000000E0u)

Definition at line 8378 of file regs.h.

#define ITM_CELLID2   *((volatile int32u *)0xE0000FF8u)

Definition at line 8385 of file regs.h.

#define ITM_CELLID2_ADDR   (0xE0000FF8u)

Definition at line 8387 of file regs.h.

#define ITM_CELLID2_PERIPHID   (0xFFFFFFFFu)

Definition at line 8390 of file regs.h.

#define ITM_CELLID2_PERIPHID_BIT   (0)

Definition at line 8392 of file regs.h.

#define ITM_CELLID2_PERIPHID_BITS   (32)

Definition at line 8393 of file regs.h.

#define ITM_CELLID2_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 8391 of file regs.h.

#define ITM_CELLID2_REG   *((volatile int32u *)0xE0000FF8u)

Definition at line 8386 of file regs.h.

#define ITM_CELLID2_RESET   (0x00000005u)

Definition at line 8388 of file regs.h.

#define ITM_CELLID3   *((volatile int32u *)0xE0000FFCu)

Definition at line 8395 of file regs.h.

#define ITM_CELLID3_ADDR   (0xE0000FFCu)

Definition at line 8397 of file regs.h.

#define ITM_CELLID3_PERIPHID   (0xFFFFFFFFu)

Definition at line 8400 of file regs.h.

#define ITM_CELLID3_PERIPHID_BIT   (0)

Definition at line 8402 of file regs.h.

#define ITM_CELLID3_PERIPHID_BITS   (32)

Definition at line 8403 of file regs.h.

#define ITM_CELLID3_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 8401 of file regs.h.

#define ITM_CELLID3_REG   *((volatile int32u *)0xE0000FFCu)

Definition at line 8396 of file regs.h.

#define ITM_CELLID3_RESET   (0x000000B1u)

Definition at line 8398 of file regs.h.

#define ITM_IMC   *((volatile int32u *)0xE0000F00u)

Definition at line 8245 of file regs.h.

#define ITM_IMC_ADDR   (0xE0000F00u)

Definition at line 8247 of file regs.h.

#define ITM_IMC_INTEGRATION   (0x00000001u)

Definition at line 8250 of file regs.h.

#define ITM_IMC_INTEGRATION_BIT   (0)

Definition at line 8252 of file regs.h.

#define ITM_IMC_INTEGRATION_BITS   (1)

Definition at line 8253 of file regs.h.

#define ITM_IMC_INTEGRATION_MASK   (0x00000001u)

Definition at line 8251 of file regs.h.

#define ITM_IMC_REG   *((volatile int32u *)0xE0000F00u)

Definition at line 8246 of file regs.h.

#define ITM_IMC_RESET   (0x00000000u)

Definition at line 8248 of file regs.h.

#define ITM_IR   *((volatile int32u *)0xE0000EFCu)

Definition at line 8235 of file regs.h.

#define ITM_IR_ADDR   (0xE0000EFCu)

Definition at line 8237 of file regs.h.

#define ITM_IR_ATREADYM   (0x00000001u)

Definition at line 8240 of file regs.h.

#define ITM_IR_ATREADYM_BIT   (0)

Definition at line 8242 of file regs.h.

#define ITM_IR_ATREADYM_BITS   (1)

Definition at line 8243 of file regs.h.

#define ITM_IR_ATREADYM_MASK   (0x00000001u)

Definition at line 8241 of file regs.h.

#define ITM_IR_REG   *((volatile int32u *)0xE0000EFCu)

Definition at line 8236 of file regs.h.

#define ITM_IR_RESET   (0x00000000u)

Definition at line 8238 of file regs.h.

#define ITM_IW   *((volatile int32u *)0xE0000EF8u)

Definition at line 8225 of file regs.h.

#define ITM_IW_ADDR   (0xE0000EF8u)

Definition at line 8227 of file regs.h.

#define ITM_IW_ATVALIDM   (0x00000001u)

Definition at line 8230 of file regs.h.

#define ITM_IW_ATVALIDM_BIT   (0)

Definition at line 8232 of file regs.h.

#define ITM_IW_ATVALIDM_BITS   (1)

Definition at line 8233 of file regs.h.

#define ITM_IW_ATVALIDM_MASK   (0x00000001u)

Definition at line 8231 of file regs.h.

#define ITM_IW_REG   *((volatile int32u *)0xE0000EF8u)

Definition at line 8226 of file regs.h.

#define ITM_IW_RESET   (0x00000000u)

Definition at line 8228 of file regs.h.

#define ITM_LA   *((volatile int32u *)0xE0000FB0u)

Definition at line 8255 of file regs.h.

#define ITM_LA_ADDR   (0xE0000FB0u)

Definition at line 8257 of file regs.h.

#define ITM_LA_LOCKACC   (0xFFFFFFFFu)

Definition at line 8260 of file regs.h.

#define ITM_LA_LOCKACC_BIT   (0)

Definition at line 8262 of file regs.h.

#define ITM_LA_LOCKACC_BITS   (32)

Definition at line 8263 of file regs.h.

#define ITM_LA_LOCKACC_MASK   (0xFFFFFFFFu)

Definition at line 8261 of file regs.h.

#define ITM_LA_REG   *((volatile int32u *)0xE0000FB0u)

Definition at line 8256 of file regs.h.

#define ITM_LA_RESET   (0x00000000u)

Definition at line 8258 of file regs.h.

#define ITM_LS   *((volatile int32u *)0xE0000FB4u)

Definition at line 8265 of file regs.h.

#define ITM_LS_ACCESS   (0x00000002u)

Definition at line 8275 of file regs.h.

#define ITM_LS_ACCESS_BIT   (1)

Definition at line 8277 of file regs.h.

#define ITM_LS_ACCESS_BITS   (1)

Definition at line 8278 of file regs.h.

#define ITM_LS_ACCESS_MASK   (0x00000002u)

Definition at line 8276 of file regs.h.

#define ITM_LS_ADDR   (0xE0000FB4u)

Definition at line 8267 of file regs.h.

#define ITM_LS_BYTEACC   (0x00000004u)

Definition at line 8270 of file regs.h.

#define ITM_LS_BYTEACC_BIT   (2)

Definition at line 8272 of file regs.h.

#define ITM_LS_BYTEACC_BITS   (1)

Definition at line 8273 of file regs.h.

#define ITM_LS_BYTEACC_MASK   (0x00000004u)

Definition at line 8271 of file regs.h.

#define ITM_LS_PRESENT   (0x00000001u)

Definition at line 8280 of file regs.h.

#define ITM_LS_PRESENT_BIT   (0)

Definition at line 8282 of file regs.h.

#define ITM_LS_PRESENT_BITS   (1)

Definition at line 8283 of file regs.h.

#define ITM_LS_PRESENT_MASK   (0x00000001u)

Definition at line 8281 of file regs.h.

#define ITM_LS_REG   *((volatile int32u *)0xE0000FB4u)

Definition at line 8266 of file regs.h.

#define ITM_LS_RESET   (0x00000000u)

Definition at line 8268 of file regs.h.

#define ITM_PERIPHID0   *((volatile int32u *)0xE0000FE0u)

Definition at line 8325 of file regs.h.

#define ITM_PERIPHID0_ADDR   (0xE0000FE0u)

Definition at line 8327 of file regs.h.

#define ITM_PERIPHID0_PERIPHID   (0xFFFFFFFFu)

Definition at line 8330 of file regs.h.

#define ITM_PERIPHID0_PERIPHID_BIT   (0)

Definition at line 8332 of file regs.h.

#define ITM_PERIPHID0_PERIPHID_BITS   (32)

Definition at line 8333 of file regs.h.

#define ITM_PERIPHID0_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 8331 of file regs.h.

#define ITM_PERIPHID0_REG   *((volatile int32u *)0xE0000FE0u)

Definition at line 8326 of file regs.h.

#define ITM_PERIPHID0_RESET   (0x00000001u)

Definition at line 8328 of file regs.h.

#define ITM_PERIPHID1   *((volatile int32u *)0xE0000FE4u)

Definition at line 8335 of file regs.h.

#define ITM_PERIPHID1_ADDR   (0xE0000FE4u)

Definition at line 8337 of file regs.h.

#define ITM_PERIPHID1_PERIPHID   (0xFFFFFFFFu)

Definition at line 8340 of file regs.h.

#define ITM_PERIPHID1_PERIPHID_BIT   (0)

Definition at line 8342 of file regs.h.

#define ITM_PERIPHID1_PERIPHID_BITS   (32)

Definition at line 8343 of file regs.h.

#define ITM_PERIPHID1_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 8341 of file regs.h.

#define ITM_PERIPHID1_REG   *((volatile int32u *)0xE0000FE4u)

Definition at line 8336 of file regs.h.

#define ITM_PERIPHID1_RESET   (0x000000B0u)

Definition at line 8338 of file regs.h.

#define ITM_PERIPHID2   *((volatile int32u *)0xE0000FE8u)

Definition at line 8345 of file regs.h.

#define ITM_PERIPHID2_ADDR   (0xE0000FE8u)

Definition at line 8347 of file regs.h.

#define ITM_PERIPHID2_PERIPHID   (0xFFFFFFFFu)

Definition at line 8350 of file regs.h.

#define ITM_PERIPHID2_PERIPHID_BIT   (0)

Definition at line 8352 of file regs.h.

#define ITM_PERIPHID2_PERIPHID_BITS   (32)

Definition at line 8353 of file regs.h.

#define ITM_PERIPHID2_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 8351 of file regs.h.

#define ITM_PERIPHID2_REG   *((volatile int32u *)0xE0000FE8u)

Definition at line 8346 of file regs.h.

#define ITM_PERIPHID2_RESET   (0x0000001Bu)

Definition at line 8348 of file regs.h.

#define ITM_PERIPHID3   *((volatile int32u *)0xE0000FECu)

Definition at line 8355 of file regs.h.

#define ITM_PERIPHID3_ADDR   (0xE0000FECu)

Definition at line 8357 of file regs.h.

#define ITM_PERIPHID3_PERIPHID   (0xFFFFFFFFu)

Definition at line 8360 of file regs.h.

#define ITM_PERIPHID3_PERIPHID_BIT   (0)

Definition at line 8362 of file regs.h.

#define ITM_PERIPHID3_PERIPHID_BITS   (32)

Definition at line 8363 of file regs.h.

#define ITM_PERIPHID3_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 8361 of file regs.h.

#define ITM_PERIPHID3_REG   *((volatile int32u *)0xE0000FECu)

Definition at line 8356 of file regs.h.

#define ITM_PERIPHID3_RESET   (0x00000000u)

Definition at line 8358 of file regs.h.

#define ITM_PERIPHID4   *((volatile int32u *)0xE0000FD0u)

Definition at line 8285 of file regs.h.

#define ITM_PERIPHID4_ADDR   (0xE0000FD0u)

Definition at line 8287 of file regs.h.

#define ITM_PERIPHID4_PERIPHID   (0xFFFFFFFFu)

Definition at line 8290 of file regs.h.

#define ITM_PERIPHID4_PERIPHID_BIT   (0)

Definition at line 8292 of file regs.h.

#define ITM_PERIPHID4_PERIPHID_BITS   (32)

Definition at line 8293 of file regs.h.

#define ITM_PERIPHID4_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 8291 of file regs.h.

#define ITM_PERIPHID4_REG   *((volatile int32u *)0xE0000FD0u)

Definition at line 8286 of file regs.h.

#define ITM_PERIPHID4_RESET   (0x00000004u)

Definition at line 8288 of file regs.h.

#define ITM_PERIPHID5   *((volatile int32u *)0xE0000FD4u)

Definition at line 8295 of file regs.h.

#define ITM_PERIPHID5_ADDR   (0xE0000FD4u)

Definition at line 8297 of file regs.h.

#define ITM_PERIPHID5_PERIPHID   (0xFFFFFFFFu)

Definition at line 8300 of file regs.h.

#define ITM_PERIPHID5_PERIPHID_BIT   (0)

Definition at line 8302 of file regs.h.

#define ITM_PERIPHID5_PERIPHID_BITS   (32)

Definition at line 8303 of file regs.h.

#define ITM_PERIPHID5_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 8301 of file regs.h.

#define ITM_PERIPHID5_REG   *((volatile int32u *)0xE0000FD4u)

Definition at line 8296 of file regs.h.

#define ITM_PERIPHID5_RESET   (0x00000000u)

Definition at line 8298 of file regs.h.

#define ITM_PERIPHID6   *((volatile int32u *)0xE0000FD8u)

Definition at line 8305 of file regs.h.

#define ITM_PERIPHID6_ADDR   (0xE0000FD8u)

Definition at line 8307 of file regs.h.

#define ITM_PERIPHID6_PERIPHID   (0xFFFFFFFFu)

Definition at line 8310 of file regs.h.

#define ITM_PERIPHID6_PERIPHID_BIT   (0)

Definition at line 8312 of file regs.h.

#define ITM_PERIPHID6_PERIPHID_BITS   (32)

Definition at line 8313 of file regs.h.

#define ITM_PERIPHID6_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 8311 of file regs.h.

#define ITM_PERIPHID6_REG   *((volatile int32u *)0xE0000FD8u)

Definition at line 8306 of file regs.h.

#define ITM_PERIPHID6_RESET   (0x00000000u)

Definition at line 8308 of file regs.h.

#define ITM_PERIPHID7   *((volatile int32u *)0xE0000FDCu)

Definition at line 8315 of file regs.h.

#define ITM_PERIPHID7_ADDR   (0xE0000FDCu)

Definition at line 8317 of file regs.h.

#define ITM_PERIPHID7_PERIPHID   (0xFFFFFFFFu)

Definition at line 8320 of file regs.h.

#define ITM_PERIPHID7_PERIPHID_BIT   (0)

Definition at line 8322 of file regs.h.

#define ITM_PERIPHID7_PERIPHID_BITS   (32)

Definition at line 8323 of file regs.h.

#define ITM_PERIPHID7_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 8321 of file regs.h.

#define ITM_PERIPHID7_REG   *((volatile int32u *)0xE0000FDCu)

Definition at line 8316 of file regs.h.

#define ITM_PERIPHID7_RESET   (0x00000000u)

Definition at line 8318 of file regs.h.

#define ITM_SP0   *((volatile int32u *)0xE0000000u)

Definition at line 7680 of file regs.h.

#define ITM_SP0_ADDR   (0xE0000000u)

Definition at line 7682 of file regs.h.

#define ITM_SP0_FIFOREADY   (0x00000001u)

Definition at line 7685 of file regs.h.

#define ITM_SP0_FIFOREADY_BIT   (0)

Definition at line 7687 of file regs.h.

#define ITM_SP0_FIFOREADY_BITS   (1)

Definition at line 7688 of file regs.h.

#define ITM_SP0_FIFOREADY_MASK   (0x00000001u)

Definition at line 7686 of file regs.h.

#define ITM_SP0_REG   *((volatile int32u *)0xE0000000u)

Definition at line 7681 of file regs.h.

#define ITM_SP0_RESET   (0x00000000u)

Definition at line 7683 of file regs.h.

#define ITM_SP0_STIMULUS   (0xFFFFFFFFu)

Definition at line 7690 of file regs.h.

#define ITM_SP0_STIMULUS_BIT   (0)

Definition at line 7692 of file regs.h.

#define ITM_SP0_STIMULUS_BITS   (32)

Definition at line 7693 of file regs.h.

#define ITM_SP0_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 7691 of file regs.h.

#define ITM_SP1   *((volatile int32u *)0xE0000004u)

Definition at line 7695 of file regs.h.

#define ITM_SP10   *((volatile int32u *)0xE0000028u)

Definition at line 7830 of file regs.h.

#define ITM_SP10_ADDR   (0xE0000028u)

Definition at line 7832 of file regs.h.

#define ITM_SP10_FIFOREADY   (0x00000001u)

Definition at line 7835 of file regs.h.

#define ITM_SP10_FIFOREADY_BIT   (0)

Definition at line 7837 of file regs.h.

#define ITM_SP10_FIFOREADY_BITS   (1)

Definition at line 7838 of file regs.h.

#define ITM_SP10_FIFOREADY_MASK   (0x00000001u)

Definition at line 7836 of file regs.h.

#define ITM_SP10_REG   *((volatile int32u *)0xE0000028u)

Definition at line 7831 of file regs.h.

#define ITM_SP10_RESET   (0x00000000u)

Definition at line 7833 of file regs.h.

#define ITM_SP10_STIMULUS   (0xFFFFFFFFu)

Definition at line 7840 of file regs.h.

#define ITM_SP10_STIMULUS_BIT   (0)

Definition at line 7842 of file regs.h.

#define ITM_SP10_STIMULUS_BITS   (32)

Definition at line 7843 of file regs.h.

#define ITM_SP10_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 7841 of file regs.h.

#define ITM_SP11   *((volatile int32u *)0xE000002Cu)

Definition at line 7845 of file regs.h.

#define ITM_SP11_ADDR   (0xE000002Cu)

Definition at line 7847 of file regs.h.

#define ITM_SP11_FIFOREADY   (0x00000001u)

Definition at line 7850 of file regs.h.

#define ITM_SP11_FIFOREADY_BIT   (0)

Definition at line 7852 of file regs.h.

#define ITM_SP11_FIFOREADY_BITS   (1)

Definition at line 7853 of file regs.h.

#define ITM_SP11_FIFOREADY_MASK   (0x00000001u)

Definition at line 7851 of file regs.h.

#define ITM_SP11_REG   *((volatile int32u *)0xE000002Cu)

Definition at line 7846 of file regs.h.

#define ITM_SP11_RESET   (0x00000000u)

Definition at line 7848 of file regs.h.

#define ITM_SP11_STIMULUS   (0xFFFFFFFFu)

Definition at line 7855 of file regs.h.

#define ITM_SP11_STIMULUS_BIT   (0)

Definition at line 7857 of file regs.h.

#define ITM_SP11_STIMULUS_BITS   (32)

Definition at line 7858 of file regs.h.

#define ITM_SP11_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 7856 of file regs.h.

#define ITM_SP12   *((volatile int32u *)0xE0000030u)

Definition at line 7860 of file regs.h.

#define ITM_SP12_ADDR   (0xE0000030u)

Definition at line 7862 of file regs.h.

#define ITM_SP12_FIFOREADY   (0x00000001u)

Definition at line 7865 of file regs.h.

#define ITM_SP12_FIFOREADY_BIT   (0)

Definition at line 7867 of file regs.h.

#define ITM_SP12_FIFOREADY_BITS   (1)

Definition at line 7868 of file regs.h.

#define ITM_SP12_FIFOREADY_MASK   (0x00000001u)

Definition at line 7866 of file regs.h.

#define ITM_SP12_REG   *((volatile int32u *)0xE0000030u)

Definition at line 7861 of file regs.h.

#define ITM_SP12_RESET   (0x00000000u)

Definition at line 7863 of file regs.h.

#define ITM_SP12_STIMULUS   (0xFFFFFFFFu)

Definition at line 7870 of file regs.h.

#define ITM_SP12_STIMULUS_BIT   (0)

Definition at line 7872 of file regs.h.

#define ITM_SP12_STIMULUS_BITS   (32)

Definition at line 7873 of file regs.h.

#define ITM_SP12_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 7871 of file regs.h.

#define ITM_SP13   *((volatile int32u *)0xE0000034u)

Definition at line 7875 of file regs.h.

#define ITM_SP13_ADDR   (0xE0000034u)

Definition at line 7877 of file regs.h.

#define ITM_SP13_FIFOREADY   (0x00000001u)

Definition at line 7880 of file regs.h.

#define ITM_SP13_FIFOREADY_BIT   (0)

Definition at line 7882 of file regs.h.

#define ITM_SP13_FIFOREADY_BITS   (1)

Definition at line 7883 of file regs.h.

#define ITM_SP13_FIFOREADY_MASK   (0x00000001u)

Definition at line 7881 of file regs.h.

#define ITM_SP13_REG   *((volatile int32u *)0xE0000034u)

Definition at line 7876 of file regs.h.

#define ITM_SP13_RESET   (0x00000000u)

Definition at line 7878 of file regs.h.

#define ITM_SP13_STIMULUS   (0xFFFFFFFFu)

Definition at line 7885 of file regs.h.

#define ITM_SP13_STIMULUS_BIT   (0)

Definition at line 7887 of file regs.h.

#define ITM_SP13_STIMULUS_BITS   (32)

Definition at line 7888 of file regs.h.

#define ITM_SP13_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 7886 of file regs.h.

#define ITM_SP14   *((volatile int32u *)0xE0000038u)

Definition at line 7890 of file regs.h.

#define ITM_SP14_ADDR   (0xE0000038u)

Definition at line 7892 of file regs.h.

#define ITM_SP14_FIFOREADY   (0x00000001u)

Definition at line 7895 of file regs.h.

#define ITM_SP14_FIFOREADY_BIT   (0)

Definition at line 7897 of file regs.h.

#define ITM_SP14_FIFOREADY_BITS   (1)

Definition at line 7898 of file regs.h.

#define ITM_SP14_FIFOREADY_MASK   (0x00000001u)

Definition at line 7896 of file regs.h.

#define ITM_SP14_REG   *((volatile int32u *)0xE0000038u)

Definition at line 7891 of file regs.h.

#define ITM_SP14_RESET   (0x00000000u)

Definition at line 7893 of file regs.h.

#define ITM_SP14_STIMULUS   (0xFFFFFFFFu)

Definition at line 7900 of file regs.h.

#define ITM_SP14_STIMULUS_BIT   (0)

Definition at line 7902 of file regs.h.

#define ITM_SP14_STIMULUS_BITS   (32)

Definition at line 7903 of file regs.h.

#define ITM_SP14_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 7901 of file regs.h.

#define ITM_SP15   *((volatile int32u *)0xE000003Cu)

Definition at line 7905 of file regs.h.

#define ITM_SP15_ADDR   (0xE000003Cu)

Definition at line 7907 of file regs.h.

#define ITM_SP15_FIFOREADY   (0x00000001u)

Definition at line 7910 of file regs.h.

#define ITM_SP15_FIFOREADY_BIT   (0)

Definition at line 7912 of file regs.h.

#define ITM_SP15_FIFOREADY_BITS   (1)

Definition at line 7913 of file regs.h.

#define ITM_SP15_FIFOREADY_MASK   (0x00000001u)

Definition at line 7911 of file regs.h.

#define ITM_SP15_REG   *((volatile int32u *)0xE000003Cu)

Definition at line 7906 of file regs.h.

#define ITM_SP15_RESET   (0x00000000u)

Definition at line 7908 of file regs.h.

#define ITM_SP15_STIMULUS   (0xFFFFFFFFu)

Definition at line 7915 of file regs.h.

#define ITM_SP15_STIMULUS_BIT   (0)

Definition at line 7917 of file regs.h.

#define ITM_SP15_STIMULUS_BITS   (32)

Definition at line 7918 of file regs.h.

#define ITM_SP15_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 7916 of file regs.h.

#define ITM_SP16   *((volatile int32u *)0xE0000040u)

Definition at line 7920 of file regs.h.

#define ITM_SP16_ADDR   (0xE0000040u)

Definition at line 7922 of file regs.h.

#define ITM_SP16_FIFOREADY   (0x00000001u)

Definition at line 7925 of file regs.h.

#define ITM_SP16_FIFOREADY_BIT   (0)

Definition at line 7927 of file regs.h.

#define ITM_SP16_FIFOREADY_BITS   (1)

Definition at line 7928 of file regs.h.

#define ITM_SP16_FIFOREADY_MASK   (0x00000001u)

Definition at line 7926 of file regs.h.

#define ITM_SP16_REG   *((volatile int32u *)0xE0000040u)

Definition at line 7921 of file regs.h.

#define ITM_SP16_RESET   (0x00000000u)

Definition at line 7923 of file regs.h.

#define ITM_SP16_STIMULUS   (0xFFFFFFFFu)

Definition at line 7930 of file regs.h.

#define ITM_SP16_STIMULUS_BIT   (0)

Definition at line 7932 of file regs.h.

#define ITM_SP16_STIMULUS_BITS   (32)

Definition at line 7933 of file regs.h.

#define ITM_SP16_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 7931 of file regs.h.

#define ITM_SP17   *((volatile int32u *)0xE0000044u)

Definition at line 7935 of file regs.h.

#define ITM_SP17_ADDR   (0xE0000044u)

Definition at line 7937 of file regs.h.

#define ITM_SP17_FIFOREADY   (0x00000001u)

Definition at line 7940 of file regs.h.

#define ITM_SP17_FIFOREADY_BIT   (0)

Definition at line 7942 of file regs.h.

#define ITM_SP17_FIFOREADY_BITS   (1)

Definition at line 7943 of file regs.h.

#define ITM_SP17_FIFOREADY_MASK   (0x00000001u)

Definition at line 7941 of file regs.h.

#define ITM_SP17_REG   *((volatile int32u *)0xE0000044u)

Definition at line 7936 of file regs.h.

#define ITM_SP17_RESET   (0x00000000u)

Definition at line 7938 of file regs.h.

#define ITM_SP17_STIMULUS   (0xFFFFFFFFu)

Definition at line 7945 of file regs.h.

#define ITM_SP17_STIMULUS_BIT   (0)

Definition at line 7947 of file regs.h.

#define ITM_SP17_STIMULUS_BITS   (32)

Definition at line 7948 of file regs.h.

#define ITM_SP17_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 7946 of file regs.h.

#define ITM_SP18   *((volatile int32u *)0xE0000048u)

Definition at line 7950 of file regs.h.

#define ITM_SP18_ADDR   (0xE0000048u)

Definition at line 7952 of file regs.h.

#define ITM_SP18_FIFOREADY   (0x00000001u)

Definition at line 7955 of file regs.h.

#define ITM_SP18_FIFOREADY_BIT   (0)

Definition at line 7957 of file regs.h.

#define ITM_SP18_FIFOREADY_BITS   (1)

Definition at line 7958 of file regs.h.

#define ITM_SP18_FIFOREADY_MASK   (0x00000001u)

Definition at line 7956 of file regs.h.

#define ITM_SP18_REG   *((volatile int32u *)0xE0000048u)

Definition at line 7951 of file regs.h.

#define ITM_SP18_RESET   (0x00000000u)

Definition at line 7953 of file regs.h.

#define ITM_SP18_STIMULUS   (0xFFFFFFFFu)

Definition at line 7960 of file regs.h.

#define ITM_SP18_STIMULUS_BIT   (0)

Definition at line 7962 of file regs.h.

#define ITM_SP18_STIMULUS_BITS   (32)

Definition at line 7963 of file regs.h.

#define ITM_SP18_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 7961 of file regs.h.

#define ITM_SP19   *((volatile int32u *)0xE000004Cu)

Definition at line 7965 of file regs.h.

#define ITM_SP19_ADDR   (0xE000004Cu)

Definition at line 7967 of file regs.h.

#define ITM_SP19_FIFOREADY   (0x00000001u)

Definition at line 7970 of file regs.h.

#define ITM_SP19_FIFOREADY_BIT   (0)

Definition at line 7972 of file regs.h.

#define ITM_SP19_FIFOREADY_BITS   (1)

Definition at line 7973 of file regs.h.

#define ITM_SP19_FIFOREADY_MASK   (0x00000001u)

Definition at line 7971 of file regs.h.

#define ITM_SP19_REG   *((volatile int32u *)0xE000004Cu)

Definition at line 7966 of file regs.h.

#define ITM_SP19_RESET   (0x00000000u)

Definition at line 7968 of file regs.h.

#define ITM_SP19_STIMULUS   (0xFFFFFFFFu)

Definition at line 7975 of file regs.h.

#define ITM_SP19_STIMULUS_BIT   (0)

Definition at line 7977 of file regs.h.

#define ITM_SP19_STIMULUS_BITS   (32)

Definition at line 7978 of file regs.h.

#define ITM_SP19_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 7976 of file regs.h.

#define ITM_SP1_ADDR   (0xE0000004u)

Definition at line 7697 of file regs.h.

#define ITM_SP1_FIFOREADY   (0x00000001u)

Definition at line 7700 of file regs.h.

#define ITM_SP1_FIFOREADY_BIT   (0)

Definition at line 7702 of file regs.h.

#define ITM_SP1_FIFOREADY_BITS   (1)

Definition at line 7703 of file regs.h.

#define ITM_SP1_FIFOREADY_MASK   (0x00000001u)

Definition at line 7701 of file regs.h.

#define ITM_SP1_REG   *((volatile int32u *)0xE0000004u)

Definition at line 7696 of file regs.h.

#define ITM_SP1_RESET   (0x00000000u)

Definition at line 7698 of file regs.h.

#define ITM_SP1_STIMULUS   (0xFFFFFFFFu)

Definition at line 7705 of file regs.h.

#define ITM_SP1_STIMULUS_BIT   (0)

Definition at line 7707 of file regs.h.

#define ITM_SP1_STIMULUS_BITS   (32)

Definition at line 7708 of file regs.h.

#define ITM_SP1_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 7706 of file regs.h.

#define ITM_SP2   *((volatile int32u *)0xE0000008u)

Definition at line 7710 of file regs.h.

#define ITM_SP20   *((volatile int32u *)0xE0000050u)

Definition at line 7980 of file regs.h.

#define ITM_SP20_ADDR   (0xE0000050u)

Definition at line 7982 of file regs.h.

#define ITM_SP20_FIFOREADY   (0x00000001u)

Definition at line 7985 of file regs.h.

#define ITM_SP20_FIFOREADY_BIT   (0)

Definition at line 7987 of file regs.h.

#define ITM_SP20_FIFOREADY_BITS   (1)

Definition at line 7988 of file regs.h.

#define ITM_SP20_FIFOREADY_MASK   (0x00000001u)

Definition at line 7986 of file regs.h.

#define ITM_SP20_REG   *((volatile int32u *)0xE0000050u)

Definition at line 7981 of file regs.h.

#define ITM_SP20_RESET   (0x00000000u)

Definition at line 7983 of file regs.h.

#define ITM_SP20_STIMULUS   (0xFFFFFFFFu)

Definition at line 7990 of file regs.h.

#define ITM_SP20_STIMULUS_BIT   (0)

Definition at line 7992 of file regs.h.

#define ITM_SP20_STIMULUS_BITS   (32)

Definition at line 7993 of file regs.h.

#define ITM_SP20_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 7991 of file regs.h.

#define ITM_SP21   *((volatile int32u *)0xE0000054u)

Definition at line 7995 of file regs.h.

#define ITM_SP21_ADDR   (0xE0000054u)

Definition at line 7997 of file regs.h.

#define ITM_SP21_FIFOREADY   (0x00000001u)

Definition at line 8000 of file regs.h.

#define ITM_SP21_FIFOREADY_BIT   (0)

Definition at line 8002 of file regs.h.

#define ITM_SP21_FIFOREADY_BITS   (1)

Definition at line 8003 of file regs.h.

#define ITM_SP21_FIFOREADY_MASK   (0x00000001u)

Definition at line 8001 of file regs.h.

#define ITM_SP21_REG   *((volatile int32u *)0xE0000054u)

Definition at line 7996 of file regs.h.

#define ITM_SP21_RESET   (0x00000000u)

Definition at line 7998 of file regs.h.

#define ITM_SP21_STIMULUS   (0xFFFFFFFFu)

Definition at line 8005 of file regs.h.

#define ITM_SP21_STIMULUS_BIT   (0)

Definition at line 8007 of file regs.h.

#define ITM_SP21_STIMULUS_BITS   (32)

Definition at line 8008 of file regs.h.

#define ITM_SP21_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 8006 of file regs.h.

#define ITM_SP22   *((volatile int32u *)0xE0000058u)

Definition at line 8010 of file regs.h.

#define ITM_SP22_ADDR   (0xE0000058u)

Definition at line 8012 of file regs.h.

#define ITM_SP22_FIFOREADY   (0x00000001u)

Definition at line 8015 of file regs.h.

#define ITM_SP22_FIFOREADY_BIT   (0)

Definition at line 8017 of file regs.h.

#define ITM_SP22_FIFOREADY_BITS   (1)

Definition at line 8018 of file regs.h.

#define ITM_SP22_FIFOREADY_MASK   (0x00000001u)

Definition at line 8016 of file regs.h.

#define ITM_SP22_REG   *((volatile int32u *)0xE0000058u)

Definition at line 8011 of file regs.h.

#define ITM_SP22_RESET   (0x00000000u)

Definition at line 8013 of file regs.h.

#define ITM_SP22_STIMULUS   (0xFFFFFFFFu)

Definition at line 8020 of file regs.h.

#define ITM_SP22_STIMULUS_BIT   (0)

Definition at line 8022 of file regs.h.

#define ITM_SP22_STIMULUS_BITS   (32)

Definition at line 8023 of file regs.h.

#define ITM_SP22_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 8021 of file regs.h.

#define ITM_SP23   *((volatile int32u *)0xE000005Cu)

Definition at line 8025 of file regs.h.

#define ITM_SP23_ADDR   (0xE000005Cu)

Definition at line 8027 of file regs.h.

#define ITM_SP23_FIFOREADY   (0x00000001u)

Definition at line 8030 of file regs.h.

#define ITM_SP23_FIFOREADY_BIT   (0)

Definition at line 8032 of file regs.h.

#define ITM_SP23_FIFOREADY_BITS   (1)

Definition at line 8033 of file regs.h.

#define ITM_SP23_FIFOREADY_MASK   (0x00000001u)

Definition at line 8031 of file regs.h.

#define ITM_SP23_REG   *((volatile int32u *)0xE000005Cu)

Definition at line 8026 of file regs.h.

#define ITM_SP23_RESET   (0x00000000u)

Definition at line 8028 of file regs.h.

#define ITM_SP23_STIMULUS   (0xFFFFFFFFu)

Definition at line 8035 of file regs.h.

#define ITM_SP23_STIMULUS_BIT   (0)

Definition at line 8037 of file regs.h.

#define ITM_SP23_STIMULUS_BITS   (32)

Definition at line 8038 of file regs.h.

#define ITM_SP23_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 8036 of file regs.h.

#define ITM_SP24   *((volatile int32u *)0xE0000060u)

Definition at line 8040 of file regs.h.

#define ITM_SP24_ADDR   (0xE0000060u)

Definition at line 8042 of file regs.h.

#define ITM_SP24_FIFOREADY   (0x00000001u)

Definition at line 8045 of file regs.h.

#define ITM_SP24_FIFOREADY_BIT   (0)

Definition at line 8047 of file regs.h.

#define ITM_SP24_FIFOREADY_BITS   (1)

Definition at line 8048 of file regs.h.

#define ITM_SP24_FIFOREADY_MASK   (0x00000001u)

Definition at line 8046 of file regs.h.

#define ITM_SP24_REG   *((volatile int32u *)0xE0000060u)

Definition at line 8041 of file regs.h.

#define ITM_SP24_RESET   (0x00000000u)

Definition at line 8043 of file regs.h.

#define ITM_SP24_STIMULUS   (0xFFFFFFFFu)

Definition at line 8050 of file regs.h.

#define ITM_SP24_STIMULUS_BIT   (0)

Definition at line 8052 of file regs.h.

#define ITM_SP24_STIMULUS_BITS   (32)

Definition at line 8053 of file regs.h.

#define ITM_SP24_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 8051 of file regs.h.

#define ITM_SP25   *((volatile int32u *)0xE0000064u)

Definition at line 8055 of file regs.h.

#define ITM_SP25_ADDR   (0xE0000064u)

Definition at line 8057 of file regs.h.

#define ITM_SP25_FIFOREADY   (0x00000001u)

Definition at line 8060 of file regs.h.

#define ITM_SP25_FIFOREADY_BIT   (0)

Definition at line 8062 of file regs.h.

#define ITM_SP25_FIFOREADY_BITS   (1)

Definition at line 8063 of file regs.h.

#define ITM_SP25_FIFOREADY_MASK   (0x00000001u)

Definition at line 8061 of file regs.h.

#define ITM_SP25_REG   *((volatile int32u *)0xE0000064u)

Definition at line 8056 of file regs.h.

#define ITM_SP25_RESET   (0x00000000u)

Definition at line 8058 of file regs.h.

#define ITM_SP25_STIMULUS   (0xFFFFFFFFu)

Definition at line 8065 of file regs.h.

#define ITM_SP25_STIMULUS_BIT   (0)

Definition at line 8067 of file regs.h.

#define ITM_SP25_STIMULUS_BITS   (32)

Definition at line 8068 of file regs.h.

#define ITM_SP25_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 8066 of file regs.h.

#define ITM_SP26   *((volatile int32u *)0xE0000068u)

Definition at line 8070 of file regs.h.

#define ITM_SP26_ADDR   (0xE0000068u)

Definition at line 8072 of file regs.h.

#define ITM_SP26_FIFOREADY   (0x00000001u)

Definition at line 8075 of file regs.h.

#define ITM_SP26_FIFOREADY_BIT   (0)

Definition at line 8077 of file regs.h.

#define ITM_SP26_FIFOREADY_BITS   (1)

Definition at line 8078 of file regs.h.

#define ITM_SP26_FIFOREADY_MASK   (0x00000001u)

Definition at line 8076 of file regs.h.

#define ITM_SP26_REG   *((volatile int32u *)0xE0000068u)

Definition at line 8071 of file regs.h.

#define ITM_SP26_RESET   (0x00000000u)

Definition at line 8073 of file regs.h.

#define ITM_SP26_STIMULUS   (0xFFFFFFFFu)

Definition at line 8080 of file regs.h.

#define ITM_SP26_STIMULUS_BIT   (0)

Definition at line 8082 of file regs.h.

#define ITM_SP26_STIMULUS_BITS   (32)

Definition at line 8083 of file regs.h.

#define ITM_SP26_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 8081 of file regs.h.

#define ITM_SP27   *((volatile int32u *)0xE000006Cu)

Definition at line 8085 of file regs.h.

#define ITM_SP27_ADDR   (0xE000006Cu)

Definition at line 8087 of file regs.h.

#define ITM_SP27_FIFOREADY   (0x00000001u)

Definition at line 8090 of file regs.h.

#define ITM_SP27_FIFOREADY_BIT   (0)

Definition at line 8092 of file regs.h.

#define ITM_SP27_FIFOREADY_BITS   (1)

Definition at line 8093 of file regs.h.

#define ITM_SP27_FIFOREADY_MASK   (0x00000001u)

Definition at line 8091 of file regs.h.

#define ITM_SP27_REG   *((volatile int32u *)0xE000006Cu)

Definition at line 8086 of file regs.h.

#define ITM_SP27_RESET   (0x00000000u)

Definition at line 8088 of file regs.h.

#define ITM_SP27_STIMULUS   (0xFFFFFFFFu)

Definition at line 8095 of file regs.h.

#define ITM_SP27_STIMULUS_BIT   (0)

Definition at line 8097 of file regs.h.

#define ITM_SP27_STIMULUS_BITS   (32)

Definition at line 8098 of file regs.h.

#define ITM_SP27_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 8096 of file regs.h.

#define ITM_SP28   *((volatile int32u *)0xE0000070u)

Definition at line 8100 of file regs.h.

#define ITM_SP28_ADDR   (0xE0000070u)

Definition at line 8102 of file regs.h.

#define ITM_SP28_FIFOREADY   (0x00000001u)

Definition at line 8105 of file regs.h.

#define ITM_SP28_FIFOREADY_BIT   (0)

Definition at line 8107 of file regs.h.

#define ITM_SP28_FIFOREADY_BITS   (1)

Definition at line 8108 of file regs.h.

#define ITM_SP28_FIFOREADY_MASK   (0x00000001u)

Definition at line 8106 of file regs.h.

#define ITM_SP28_REG   *((volatile int32u *)0xE0000070u)

Definition at line 8101 of file regs.h.

#define ITM_SP28_RESET   (0x00000000u)

Definition at line 8103 of file regs.h.

#define ITM_SP28_STIMULUS   (0xFFFFFFFFu)

Definition at line 8110 of file regs.h.

#define ITM_SP28_STIMULUS_BIT   (0)

Definition at line 8112 of file regs.h.

#define ITM_SP28_STIMULUS_BITS   (32)

Definition at line 8113 of file regs.h.

#define ITM_SP28_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 8111 of file regs.h.

#define ITM_SP29   *((volatile int32u *)0xE0000074u)

Definition at line 8115 of file regs.h.

#define ITM_SP29_ADDR   (0xE0000074u)

Definition at line 8117 of file regs.h.

#define ITM_SP29_FIFOREADY   (0x00000001u)

Definition at line 8120 of file regs.h.

#define ITM_SP29_FIFOREADY_BIT   (0)

Definition at line 8122 of file regs.h.

#define ITM_SP29_FIFOREADY_BITS   (1)

Definition at line 8123 of file regs.h.

#define ITM_SP29_FIFOREADY_MASK   (0x00000001u)

Definition at line 8121 of file regs.h.

#define ITM_SP29_REG   *((volatile int32u *)0xE0000074u)

Definition at line 8116 of file regs.h.

#define ITM_SP29_RESET   (0x00000000u)

Definition at line 8118 of file regs.h.

#define ITM_SP29_STIMULUS   (0xFFFFFFFFu)

Definition at line 8125 of file regs.h.

#define ITM_SP29_STIMULUS_BIT   (0)

Definition at line 8127 of file regs.h.

#define ITM_SP29_STIMULUS_BITS   (32)

Definition at line 8128 of file regs.h.

#define ITM_SP29_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 8126 of file regs.h.

#define ITM_SP2_ADDR   (0xE0000008u)

Definition at line 7712 of file regs.h.

#define ITM_SP2_FIFOREADY   (0x00000001u)

Definition at line 7715 of file regs.h.

#define ITM_SP2_FIFOREADY_BIT   (0)

Definition at line 7717 of file regs.h.

#define ITM_SP2_FIFOREADY_BITS   (1)

Definition at line 7718 of file regs.h.

#define ITM_SP2_FIFOREADY_MASK   (0x00000001u)

Definition at line 7716 of file regs.h.

#define ITM_SP2_REG   *((volatile int32u *)0xE0000008u)

Definition at line 7711 of file regs.h.

#define ITM_SP2_RESET   (0x00000000u)

Definition at line 7713 of file regs.h.

#define ITM_SP2_STIMULUS   (0xFFFFFFFFu)

Definition at line 7720 of file regs.h.

#define ITM_SP2_STIMULUS_BIT   (0)

Definition at line 7722 of file regs.h.

#define ITM_SP2_STIMULUS_BITS   (32)

Definition at line 7723 of file regs.h.

#define ITM_SP2_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 7721 of file regs.h.

#define ITM_SP3   *((volatile int32u *)0xE000000Cu)

Definition at line 7725 of file regs.h.

#define ITM_SP30   *((volatile int32u *)0xE0000078u)

Definition at line 8130 of file regs.h.

#define ITM_SP30_ADDR   (0xE0000078u)

Definition at line 8132 of file regs.h.

#define ITM_SP30_FIFOREADY   (0x00000001u)

Definition at line 8135 of file regs.h.

#define ITM_SP30_FIFOREADY_BIT   (0)

Definition at line 8137 of file regs.h.

#define ITM_SP30_FIFOREADY_BITS   (1)

Definition at line 8138 of file regs.h.

#define ITM_SP30_FIFOREADY_MASK   (0x00000001u)

Definition at line 8136 of file regs.h.

#define ITM_SP30_REG   *((volatile int32u *)0xE0000078u)

Definition at line 8131 of file regs.h.

#define ITM_SP30_RESET   (0x00000000u)

Definition at line 8133 of file regs.h.

#define ITM_SP30_STIMULUS   (0xFFFFFFFFu)

Definition at line 8140 of file regs.h.

#define ITM_SP30_STIMULUS_BIT   (0)

Definition at line 8142 of file regs.h.

#define ITM_SP30_STIMULUS_BITS   (32)

Definition at line 8143 of file regs.h.

#define ITM_SP30_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 8141 of file regs.h.

#define ITM_SP31   *((volatile int32u *)0xE000007Cu)

Definition at line 8145 of file regs.h.

#define ITM_SP31_ADDR   (0xE000007Cu)

Definition at line 8147 of file regs.h.

#define ITM_SP31_FIFOREADY   (0x00000001u)

Definition at line 8150 of file regs.h.

#define ITM_SP31_FIFOREADY_BIT   (0)

Definition at line 8152 of file regs.h.

#define ITM_SP31_FIFOREADY_BITS   (1)

Definition at line 8153 of file regs.h.

#define ITM_SP31_FIFOREADY_MASK   (0x00000001u)

Definition at line 8151 of file regs.h.

#define ITM_SP31_REG   *((volatile int32u *)0xE000007Cu)

Definition at line 8146 of file regs.h.

#define ITM_SP31_RESET   (0x00000000u)

Definition at line 8148 of file regs.h.

#define ITM_SP31_STIMULUS   (0xFFFFFFFFu)

Definition at line 8155 of file regs.h.

#define ITM_SP31_STIMULUS_BIT   (0)

Definition at line 8157 of file regs.h.

#define ITM_SP31_STIMULUS_BITS   (32)

Definition at line 8158 of file regs.h.

#define ITM_SP31_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 8156 of file regs.h.

#define ITM_SP3_ADDR   (0xE000000Cu)

Definition at line 7727 of file regs.h.

#define ITM_SP3_FIFOREADY   (0x00000001u)

Definition at line 7730 of file regs.h.

#define ITM_SP3_FIFOREADY_BIT   (0)

Definition at line 7732 of file regs.h.

#define ITM_SP3_FIFOREADY_BITS   (1)

Definition at line 7733 of file regs.h.

#define ITM_SP3_FIFOREADY_MASK   (0x00000001u)

Definition at line 7731 of file regs.h.

#define ITM_SP3_REG   *((volatile int32u *)0xE000000Cu)

Definition at line 7726 of file regs.h.

#define ITM_SP3_RESET   (0x00000000u)

Definition at line 7728 of file regs.h.

#define ITM_SP3_STIMULUS   (0xFFFFFFFFu)

Definition at line 7735 of file regs.h.

#define ITM_SP3_STIMULUS_BIT   (0)

Definition at line 7737 of file regs.h.

#define ITM_SP3_STIMULUS_BITS   (32)

Definition at line 7738 of file regs.h.

#define ITM_SP3_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 7736 of file regs.h.

#define ITM_SP4   *((volatile int32u *)0xE0000010u)

Definition at line 7740 of file regs.h.

#define ITM_SP4_ADDR   (0xE0000010u)

Definition at line 7742 of file regs.h.

#define ITM_SP4_FIFOREADY   (0x00000001u)

Definition at line 7745 of file regs.h.

#define ITM_SP4_FIFOREADY_BIT   (0)

Definition at line 7747 of file regs.h.

#define ITM_SP4_FIFOREADY_BITS   (1)

Definition at line 7748 of file regs.h.

#define ITM_SP4_FIFOREADY_MASK   (0x00000001u)

Definition at line 7746 of file regs.h.

#define ITM_SP4_REG   *((volatile int32u *)0xE0000010u)

Definition at line 7741 of file regs.h.

#define ITM_SP4_RESET   (0x00000000u)

Definition at line 7743 of file regs.h.

#define ITM_SP4_STIMULUS   (0xFFFFFFFFu)

Definition at line 7750 of file regs.h.

#define ITM_SP4_STIMULUS_BIT   (0)

Definition at line 7752 of file regs.h.

#define ITM_SP4_STIMULUS_BITS   (32)

Definition at line 7753 of file regs.h.

#define ITM_SP4_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 7751 of file regs.h.

#define ITM_SP5   *((volatile int32u *)0xE0000014u)

Definition at line 7755 of file regs.h.

#define ITM_SP5_ADDR   (0xE0000014u)

Definition at line 7757 of file regs.h.

#define ITM_SP5_FIFOREADY   (0x00000001u)

Definition at line 7760 of file regs.h.

#define ITM_SP5_FIFOREADY_BIT   (0)

Definition at line 7762 of file regs.h.

#define ITM_SP5_FIFOREADY_BITS   (1)

Definition at line 7763 of file regs.h.

#define ITM_SP5_FIFOREADY_MASK   (0x00000001u)

Definition at line 7761 of file regs.h.

#define ITM_SP5_REG   *((volatile int32u *)0xE0000014u)

Definition at line 7756 of file regs.h.

#define ITM_SP5_RESET   (0x00000000u)

Definition at line 7758 of file regs.h.

#define ITM_SP5_STIMULUS   (0xFFFFFFFFu)

Definition at line 7765 of file regs.h.

#define ITM_SP5_STIMULUS_BIT   (0)

Definition at line 7767 of file regs.h.

#define ITM_SP5_STIMULUS_BITS   (32)

Definition at line 7768 of file regs.h.

#define ITM_SP5_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 7766 of file regs.h.

#define ITM_SP6   *((volatile int32u *)0xE0000018u)

Definition at line 7770 of file regs.h.

#define ITM_SP6_ADDR   (0xE0000018u)

Definition at line 7772 of file regs.h.

#define ITM_SP6_FIFOREADY   (0x00000001u)

Definition at line 7775 of file regs.h.

#define ITM_SP6_FIFOREADY_BIT   (0)

Definition at line 7777 of file regs.h.

#define ITM_SP6_FIFOREADY_BITS   (1)

Definition at line 7778 of file regs.h.

#define ITM_SP6_FIFOREADY_MASK   (0x00000001u)

Definition at line 7776 of file regs.h.

#define ITM_SP6_REG   *((volatile int32u *)0xE0000018u)

Definition at line 7771 of file regs.h.

#define ITM_SP6_RESET   (0x00000000u)

Definition at line 7773 of file regs.h.

#define ITM_SP6_STIMULUS   (0xFFFFFFFFu)

Definition at line 7780 of file regs.h.

#define ITM_SP6_STIMULUS_BIT   (0)

Definition at line 7782 of file regs.h.

#define ITM_SP6_STIMULUS_BITS   (32)

Definition at line 7783 of file regs.h.

#define ITM_SP6_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 7781 of file regs.h.

#define ITM_SP7   *((volatile int32u *)0xE000001Cu)

Definition at line 7785 of file regs.h.

#define ITM_SP7_ADDR   (0xE000001Cu)

Definition at line 7787 of file regs.h.

#define ITM_SP7_FIFOREADY   (0x00000001u)

Definition at line 7790 of file regs.h.

#define ITM_SP7_FIFOREADY_BIT   (0)

Definition at line 7792 of file regs.h.

#define ITM_SP7_FIFOREADY_BITS   (1)

Definition at line 7793 of file regs.h.

#define ITM_SP7_FIFOREADY_MASK   (0x00000001u)

Definition at line 7791 of file regs.h.

#define ITM_SP7_REG   *((volatile int32u *)0xE000001Cu)

Definition at line 7786 of file regs.h.

#define ITM_SP7_RESET   (0x00000000u)

Definition at line 7788 of file regs.h.

#define ITM_SP7_STIMULUS   (0xFFFFFFFFu)

Definition at line 7795 of file regs.h.

#define ITM_SP7_STIMULUS_BIT   (0)

Definition at line 7797 of file regs.h.

#define ITM_SP7_STIMULUS_BITS   (32)

Definition at line 7798 of file regs.h.

#define ITM_SP7_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 7796 of file regs.h.

#define ITM_SP8   *((volatile int32u *)0xE0000020u)

Definition at line 7800 of file regs.h.

#define ITM_SP8_ADDR   (0xE0000020u)

Definition at line 7802 of file regs.h.

#define ITM_SP8_FIFOREADY   (0x00000001u)

Definition at line 7805 of file regs.h.

#define ITM_SP8_FIFOREADY_BIT   (0)

Definition at line 7807 of file regs.h.

#define ITM_SP8_FIFOREADY_BITS   (1)

Definition at line 7808 of file regs.h.

#define ITM_SP8_FIFOREADY_MASK   (0x00000001u)

Definition at line 7806 of file regs.h.

#define ITM_SP8_REG   *((volatile int32u *)0xE0000020u)

Definition at line 7801 of file regs.h.

#define ITM_SP8_RESET   (0x00000000u)

Definition at line 7803 of file regs.h.

#define ITM_SP8_STIMULUS   (0xFFFFFFFFu)

Definition at line 7810 of file regs.h.

#define ITM_SP8_STIMULUS_BIT   (0)

Definition at line 7812 of file regs.h.

#define ITM_SP8_STIMULUS_BITS   (32)

Definition at line 7813 of file regs.h.

#define ITM_SP8_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 7811 of file regs.h.

#define ITM_SP9   *((volatile int32u *)0xE0000024u)

Definition at line 7815 of file regs.h.

#define ITM_SP9_ADDR   (0xE0000024u)

Definition at line 7817 of file regs.h.

#define ITM_SP9_FIFOREADY   (0x00000001u)

Definition at line 7820 of file regs.h.

#define ITM_SP9_FIFOREADY_BIT   (0)

Definition at line 7822 of file regs.h.

#define ITM_SP9_FIFOREADY_BITS   (1)

Definition at line 7823 of file regs.h.

#define ITM_SP9_FIFOREADY_MASK   (0x00000001u)

Definition at line 7821 of file regs.h.

#define ITM_SP9_REG   *((volatile int32u *)0xE0000024u)

Definition at line 7816 of file regs.h.

#define ITM_SP9_RESET   (0x00000000u)

Definition at line 7818 of file regs.h.

#define ITM_SP9_STIMULUS   (0xFFFFFFFFu)

Definition at line 7825 of file regs.h.

#define ITM_SP9_STIMULUS_BIT   (0)

Definition at line 7827 of file regs.h.

#define ITM_SP9_STIMULUS_BITS   (32)

Definition at line 7828 of file regs.h.

#define ITM_SP9_STIMULUS_MASK   (0xFFFFFFFFu)

Definition at line 7826 of file regs.h.

#define ITM_TCR   *((volatile int32u *)0xE0000E80u)

Definition at line 8180 of file regs.h.

#define ITM_TCR_ADDR   (0xE0000E80u)

Definition at line 8182 of file regs.h.

#define ITM_TCR_ATBID   (0x007F0000u)

Definition at line 8190 of file regs.h.

#define ITM_TCR_ATBID_BIT   (16)

Definition at line 8192 of file regs.h.

#define ITM_TCR_ATBID_BITS   (7)

Definition at line 8193 of file regs.h.

#define ITM_TCR_ATBID_MASK   (0x007F0000u)

Definition at line 8191 of file regs.h.

#define ITM_TCR_BUSY   (0x00800000u)

Definition at line 8185 of file regs.h.

#define ITM_TCR_BUSY_BIT   (23)

Definition at line 8187 of file regs.h.

#define ITM_TCR_BUSY_BITS   (1)

Definition at line 8188 of file regs.h.

#define ITM_TCR_BUSY_MASK   (0x00800000u)

Definition at line 8186 of file regs.h.

#define ITM_TCR_DWTENA   (0x00000008u)

Definition at line 8205 of file regs.h.

#define ITM_TCR_DWTENA_BIT   (3)

Definition at line 8207 of file regs.h.

#define ITM_TCR_DWTENA_BITS   (1)

Definition at line 8208 of file regs.h.

#define ITM_TCR_DWTENA_MASK   (0x00000008u)

Definition at line 8206 of file regs.h.

#define ITM_TCR_ITMEN   (0x00000001u)

Definition at line 8220 of file regs.h.

#define ITM_TCR_ITMEN_BIT   (0)

Definition at line 8222 of file regs.h.

#define ITM_TCR_ITMEN_BITS   (1)

Definition at line 8223 of file regs.h.

#define ITM_TCR_ITMEN_MASK   (0x00000001u)

Definition at line 8221 of file regs.h.

#define ITM_TCR_REG   *((volatile int32u *)0xE0000E80u)

Definition at line 8181 of file regs.h.

#define ITM_TCR_RESET   (0x00000000u)

Definition at line 8183 of file regs.h.

#define ITM_TCR_SWOENA   (0x00000010u)

Definition at line 8200 of file regs.h.

#define ITM_TCR_SWOENA_BIT   (4)

Definition at line 8202 of file regs.h.

#define ITM_TCR_SWOENA_BITS   (1)

Definition at line 8203 of file regs.h.

#define ITM_TCR_SWOENA_MASK   (0x00000010u)

Definition at line 8201 of file regs.h.

#define ITM_TCR_SYNCENA   (0x00000004u)

Definition at line 8210 of file regs.h.

#define ITM_TCR_SYNCENA_BIT   (2)

Definition at line 8212 of file regs.h.

#define ITM_TCR_SYNCENA_BITS   (1)

Definition at line 8213 of file regs.h.

#define ITM_TCR_SYNCENA_MASK   (0x00000004u)

Definition at line 8211 of file regs.h.

#define ITM_TCR_TSENA   (0x00000002u)

Definition at line 8215 of file regs.h.

#define ITM_TCR_TSENA_BIT   (1)

Definition at line 8217 of file regs.h.

#define ITM_TCR_TSENA_BITS   (1)

Definition at line 8218 of file regs.h.

#define ITM_TCR_TSENA_MASK   (0x00000002u)

Definition at line 8216 of file regs.h.

#define ITM_TCR_TSPRESCALE   (0x00000300u)

Definition at line 8195 of file regs.h.

#define ITM_TCR_TSPRESCALE_BIT   (8)

Definition at line 8197 of file regs.h.

#define ITM_TCR_TSPRESCALE_BITS   (2)

Definition at line 8198 of file regs.h.

#define ITM_TCR_TSPRESCALE_MASK   (0x00000300u)

Definition at line 8196 of file regs.h.

#define ITM_TER   *((volatile int32u *)0xE0000E00u)

Definition at line 8160 of file regs.h.

#define ITM_TER_ADDR   (0xE0000E00u)

Definition at line 8162 of file regs.h.

#define ITM_TER_REG   *((volatile int32u *)0xE0000E00u)

Definition at line 8161 of file regs.h.

#define ITM_TER_RESET   (0x00000000u)

Definition at line 8163 of file regs.h.

#define ITM_TER_STIMENA   (0xFFFFFFFFu)

Definition at line 8165 of file regs.h.

#define ITM_TER_STIMENA_BIT   (0)

Definition at line 8167 of file regs.h.

#define ITM_TER_STIMENA_BITS   (32)

Definition at line 8168 of file regs.h.

#define ITM_TER_STIMENA_MASK   (0xFFFFFFFFu)

Definition at line 8166 of file regs.h.

#define ITM_TPR   *((volatile int32u *)0xE0000E40u)

Definition at line 8170 of file regs.h.

#define ITM_TPR_ADDR   (0xE0000E40u)

Definition at line 8172 of file regs.h.

#define ITM_TPR_PRIVMASK   (0x0000000Fu)

Definition at line 8175 of file regs.h.

#define ITM_TPR_PRIVMASK_BIT   (0)

Definition at line 8177 of file regs.h.

#define ITM_TPR_PRIVMASK_BITS   (4)

Definition at line 8178 of file regs.h.

#define ITM_TPR_PRIVMASK_MASK   (0x0000000Fu)

Definition at line 8176 of file regs.h.

#define ITM_TPR_REG   *((volatile int32u *)0xE0000E40u)

Definition at line 8171 of file regs.h.

#define ITM_TPR_RESET   (0x00000000u)

Definition at line 8173 of file regs.h.

#define KEY_0   *((volatile int32u *)0x40003038u)

Definition at line 2395 of file regs.h.

#define KEY_0_ADDR   (0x40003038u)

Definition at line 2397 of file regs.h.

#define KEY_0_KEY_O   (0xFFFFFFFFu)

Definition at line 2400 of file regs.h.

#define KEY_0_KEY_O_BIT   (0)

Definition at line 2402 of file regs.h.

#define KEY_0_KEY_O_BITS   (32)

Definition at line 2403 of file regs.h.

#define KEY_0_KEY_O_MASK   (0xFFFFFFFFu)

Definition at line 2401 of file regs.h.

#define KEY_0_REG   *((volatile int32u *)0x40003038u)

Definition at line 2396 of file regs.h.

#define KEY_0_RESET   (0x00000000u)

Definition at line 2398 of file regs.h.

#define KEY_1   *((volatile int32u *)0x4000303Cu)

Definition at line 2405 of file regs.h.

#define KEY_1_ADDR   (0x4000303Cu)

Definition at line 2407 of file regs.h.

#define KEY_1_KEY_1   (0xFFFFFFFFu)

Definition at line 2410 of file regs.h.

#define KEY_1_KEY_1_BIT   (0)

Definition at line 2412 of file regs.h.

#define KEY_1_KEY_1_BITS   (32)

Definition at line 2413 of file regs.h.

#define KEY_1_KEY_1_MASK   (0xFFFFFFFFu)

Definition at line 2411 of file regs.h.

#define KEY_1_REG   *((volatile int32u *)0x4000303Cu)

Definition at line 2406 of file regs.h.

#define KEY_1_RESET   (0x00000000u)

Definition at line 2408 of file regs.h.

#define KEY_2   *((volatile int32u *)0x40003040u)

Definition at line 2415 of file regs.h.

#define KEY_2_ADDR   (0x40003040u)

Definition at line 2417 of file regs.h.

#define KEY_2_KEY_2   (0xFFFFFFFFu)

Definition at line 2420 of file regs.h.

#define KEY_2_KEY_2_BIT   (0)

Definition at line 2422 of file regs.h.

#define KEY_2_KEY_2_BITS   (32)

Definition at line 2423 of file regs.h.

#define KEY_2_KEY_2_MASK   (0xFFFFFFFFu)

Definition at line 2421 of file regs.h.

#define KEY_2_REG   *((volatile int32u *)0x40003040u)

Definition at line 2416 of file regs.h.

#define KEY_2_RESET   (0x00000000u)

Definition at line 2418 of file regs.h.

#define KEY_3   *((volatile int32u *)0x40003044u)

Definition at line 2425 of file regs.h.

#define KEY_3_ADDR   (0x40003044u)

Definition at line 2427 of file regs.h.

#define KEY_3_KEY_3   (0xFFFFFFFFu)

Definition at line 2430 of file regs.h.

#define KEY_3_KEY_3_BIT   (0)

Definition at line 2432 of file regs.h.

#define KEY_3_KEY_3_BITS   (32)

Definition at line 2433 of file regs.h.

#define KEY_3_KEY_3_MASK   (0xFFFFFFFFu)

Definition at line 2431 of file regs.h.

#define KEY_3_REG   *((volatile int32u *)0x40003044u)

Definition at line 2426 of file regs.h.

#define KEY_3_RESET   (0x00000000u)

Definition at line 2428 of file regs.h.

#define LV_FREEZE   (0x00000002u)

Definition at line 55 of file regs.h.

#define LV_FREEZE_BIT   (1)

Definition at line 57 of file regs.h.

#define LV_FREEZE_BITS   (1)

Definition at line 58 of file regs.h.

#define LV_FREEZE_MASK   (0x00000002u)

Definition at line 56 of file regs.h.

#define LV_SPARE   *((volatile int32u *)0x40004034u)

Definition at line 2625 of file regs.h.

#define LV_SPARE_ADDR   (0x40004034u)

Definition at line 2627 of file regs.h.

#define LV_SPARE_LV_SPARE   (0x000000FFu)

Definition at line 2630 of file regs.h.

#define LV_SPARE_LV_SPARE_BIT   (0)

Definition at line 2632 of file regs.h.

#define LV_SPARE_LV_SPARE_BITS   (8)

Definition at line 2633 of file regs.h.

#define LV_SPARE_LV_SPARE_MASK   (0x000000FFu)

Definition at line 2631 of file regs.h.

#define LV_SPARE_REG   *((volatile int32u *)0x40004034u)

Definition at line 2626 of file regs.h.

#define LV_SPARE_RESET   (0x00000000u)

Definition at line 2628 of file regs.h.

#define MAC_ACK_STROBE   *((volatile int32u *)0x40002064u)

Definition at line 1780 of file regs.h.

#define MAC_ACK_STROBE_ADDR   (0x40002064u)

Definition at line 1782 of file regs.h.

#define MAC_ACK_STROBE_FRAME_PENDING   (0x00000001u)

Definition at line 1790 of file regs.h.

#define MAC_ACK_STROBE_FRAME_PENDING_BIT   (0)

Definition at line 1792 of file regs.h.

#define MAC_ACK_STROBE_FRAME_PENDING_BITS   (1)

Definition at line 1793 of file regs.h.

#define MAC_ACK_STROBE_FRAME_PENDING_MASK   (0x00000001u)

Definition at line 1791 of file regs.h.

#define MAC_ACK_STROBE_MANUAL_ACK   (0x00000002u)

Definition at line 1785 of file regs.h.

#define MAC_ACK_STROBE_MANUAL_ACK_BIT   (1)

Definition at line 1787 of file regs.h.

#define MAC_ACK_STROBE_MANUAL_ACK_BITS   (1)

Definition at line 1788 of file regs.h.

#define MAC_ACK_STROBE_MANUAL_ACK_MASK   (0x00000002u)

Definition at line 1786 of file regs.h.

#define MAC_ACK_STROBE_REG   *((volatile int32u *)0x40002064u)

Definition at line 1781 of file regs.h.

#define MAC_ACK_STROBE_RESET   (0x00000000u)

Definition at line 1783 of file regs.h.

#define MAC_ACK_TO   *((volatile int32u *)0x40002074u)

Definition at line 1880 of file regs.h.

#define MAC_ACK_TO_ACK_TO   (0x00003FFFu)

Definition at line 1885 of file regs.h.

#define MAC_ACK_TO_ACK_TO_BIT   (0)

Definition at line 1887 of file regs.h.

#define MAC_ACK_TO_ACK_TO_BITS   (14)

Definition at line 1888 of file regs.h.

#define MAC_ACK_TO_ACK_TO_MASK   (0x00003FFFu)

Definition at line 1886 of file regs.h.

#define MAC_ACK_TO_ADDR   (0x40002074u)

Definition at line 1882 of file regs.h.

#define MAC_ACK_TO_REG   *((volatile int32u *)0x40002074u)

Definition at line 1881 of file regs.h.

#define MAC_ACK_TO_RESET   (0x00000300u)

Definition at line 1883 of file regs.h.

#define MAC_BO_TIMER   *((volatile int32u *)0x40002058u)

Definition at line 1735 of file regs.h.

#define MAC_BO_TIMER_ADDR   (0x40002058u)

Definition at line 1737 of file regs.h.

#define MAC_BO_TIMER_MAC_BO_TIMER   (0x00000FFFu)

Definition at line 1740 of file regs.h.

#define MAC_BO_TIMER_MAC_BO_TIMER_BIT   (0)

Definition at line 1742 of file regs.h.

#define MAC_BO_TIMER_MAC_BO_TIMER_BITS   (12)

Definition at line 1743 of file regs.h.

#define MAC_BO_TIMER_MAC_BO_TIMER_MASK   (0x00000FFFu)

Definition at line 1741 of file regs.h.

#define MAC_BO_TIMER_REG   *((volatile int32u *)0x40002058u)

Definition at line 1736 of file regs.h.

#define MAC_BO_TIMER_RESET   (0x00000000u)

Definition at line 1738 of file regs.h.

#define MAC_BOP_COMPARE   *((volatile int32u *)0x40002078u)

Definition at line 1890 of file regs.h.

#define MAC_BOP_COMPARE_ADDR   (0x40002078u)

Definition at line 1892 of file regs.h.

#define MAC_BOP_COMPARE_MAC_BOP_COMPARE   (0x0000007Fu)

Definition at line 1895 of file regs.h.

#define MAC_BOP_COMPARE_MAC_BOP_COMPARE_BIT   (0)

Definition at line 1897 of file regs.h.

#define MAC_BOP_COMPARE_MAC_BOP_COMPARE_BITS   (7)

Definition at line 1898 of file regs.h.

#define MAC_BOP_COMPARE_MAC_BOP_COMPARE_MASK   (0x0000007Fu)

Definition at line 1896 of file regs.h.

#define MAC_BOP_COMPARE_REG   *((volatile int32u *)0x40002078u)

Definition at line 1891 of file regs.h.

#define MAC_BOP_COMPARE_RESET   (0x00000014u)

Definition at line 1893 of file regs.h.

#define MAC_BOP_TIMER   *((volatile int32u *)0x4000205Cu)

Definition at line 1745 of file regs.h.

#define MAC_BOP_TIMER_ADDR   (0x4000205Cu)

Definition at line 1747 of file regs.h.

#define MAC_BOP_TIMER_MAC_BOP_TIMER   (0x0000007Fu)

Definition at line 1750 of file regs.h.

#define MAC_BOP_TIMER_MAC_BOP_TIMER_BIT   (0)

Definition at line 1752 of file regs.h.

#define MAC_BOP_TIMER_MAC_BOP_TIMER_BITS   (7)

Definition at line 1753 of file regs.h.

#define MAC_BOP_TIMER_MAC_BOP_TIMER_MASK   (0x0000007Fu)

Definition at line 1751 of file regs.h.

#define MAC_BOP_TIMER_REG   *((volatile int32u *)0x4000205Cu)

Definition at line 1746 of file regs.h.

#define MAC_BOP_TIMER_RESET   (0x00000000u)

Definition at line 1748 of file regs.h.

#define MAC_CONFIG   *((volatile int32u *)0x40002080u)

Definition at line 1950 of file regs.h.

#define MAC_CONFIG_ADDR   (0x40002080u)

Definition at line 1952 of file regs.h.

#define MAC_CONFIG_MAC_MODE   (0x00000001u)

Definition at line 1965 of file regs.h.

#define MAC_CONFIG_MAC_MODE_BIT   (0)

Definition at line 1967 of file regs.h.

#define MAC_CONFIG_MAC_MODE_BITS   (1)

Definition at line 1968 of file regs.h.

#define MAC_CONFIG_MAC_MODE_MASK   (0x00000001u)

Definition at line 1966 of file regs.h.

#define MAC_CONFIG_REG   *((volatile int32u *)0x40002080u)

Definition at line 1951 of file regs.h.

#define MAC_CONFIG_RESET   (0x00000000u)

Definition at line 1953 of file regs.h.

#define MAC_CONFIG_RSSI_INST_EN   (0x00000004u)

Definition at line 1955 of file regs.h.

#define MAC_CONFIG_RSSI_INST_EN_BIT   (2)

Definition at line 1957 of file regs.h.

#define MAC_CONFIG_RSSI_INST_EN_BITS   (1)

Definition at line 1958 of file regs.h.

#define MAC_CONFIG_RSSI_INST_EN_MASK   (0x00000004u)

Definition at line 1956 of file regs.h.

#define MAC_CONFIG_SPI_SPY_EN   (0x00000002u)

Definition at line 1960 of file regs.h.

#define MAC_CONFIG_SPI_SPY_EN_BIT   (1)

Definition at line 1962 of file regs.h.

#define MAC_CONFIG_SPI_SPY_EN_BITS   (1)

Definition at line 1963 of file regs.h.

#define MAC_CONFIG_SPI_SPY_EN_MASK   (0x00000002u)

Definition at line 1961 of file regs.h.

#define MAC_DEBUG   *((volatile int32u *)0x400020B8u)

Definition at line 2215 of file regs.h.

#define MAC_DEBUG_ADDR   (0x400020B8u)

Definition at line 2217 of file regs.h.

#define MAC_DEBUG_MAC_DEBUG_MUX   (0x0000001Fu)

Definition at line 2225 of file regs.h.

#define MAC_DEBUG_MAC_DEBUG_MUX_BIT   (0)

Definition at line 2227 of file regs.h.

#define MAC_DEBUG_MAC_DEBUG_MUX_BITS   (5)

Definition at line 2228 of file regs.h.

#define MAC_DEBUG_MAC_DEBUG_MUX_MASK   (0x0000001Fu)

Definition at line 2226 of file regs.h.

#define MAC_DEBUG_REG   *((volatile int32u *)0x400020B8u)

Definition at line 2216 of file regs.h.

#define MAC_DEBUG_RESET   (0x00000000u)

Definition at line 2218 of file regs.h.

#define MAC_DEBUG_SW_DEBUG_OUT   (0x00000060u)

Definition at line 2220 of file regs.h.

#define MAC_DEBUG_SW_DEBUG_OUT_BIT   (5)

Definition at line 2222 of file regs.h.

#define MAC_DEBUG_SW_DEBUG_OUT_BITS   (2)

Definition at line 2223 of file regs.h.

#define MAC_DEBUG_SW_DEBUG_OUT_MASK   (0x00000060u)

Definition at line 2221 of file regs.h.

#define MAC_DEBUG_VIEW   *((volatile int32u *)0x400020BCu)

Definition at line 2230 of file regs.h.

#define MAC_DEBUG_VIEW_ADDR   (0x400020BCu)

Definition at line 2232 of file regs.h.

#define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW   (0x0000FFFFu)

Definition at line 2235 of file regs.h.

#define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_BIT   (0)

Definition at line 2237 of file regs.h.

#define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_BITS   (16)

Definition at line 2238 of file regs.h.

#define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_MASK   (0x0000FFFFu)

Definition at line 2236 of file regs.h.

#define MAC_DEBUG_VIEW_REG   *((volatile int32u *)0x400020BCu)

Definition at line 2231 of file regs.h.

#define MAC_DEBUG_VIEW_RESET   (0x00000010u)

Definition at line 2233 of file regs.h.

#define MAC_DMA_CONFIG   *((volatile int32u *)0x40002030u)

Definition at line 1630 of file regs.h.

#define MAC_DMA_CONFIG_ADDR   (0x40002030u)

Definition at line 1632 of file regs.h.

#define MAC_DMA_CONFIG_REG   *((volatile int32u *)0x40002030u)

Definition at line 1631 of file regs.h.

#define MAC_DMA_CONFIG_RESET   (0x00000000u)

Definition at line 1633 of file regs.h.

#define MAC_DMA_CONFIG_RX_DMA_RESET   (0x00000010u)

Definition at line 1640 of file regs.h.

#define MAC_DMA_CONFIG_RX_DMA_RESET_BIT   (4)

Definition at line 1642 of file regs.h.

#define MAC_DMA_CONFIG_RX_DMA_RESET_BITS   (1)

Definition at line 1643 of file regs.h.

#define MAC_DMA_CONFIG_RX_DMA_RESET_MASK   (0x00000010u)

Definition at line 1641 of file regs.h.

#define MAC_DMA_CONFIG_RX_LOAD_A   (0x00000001u)

Definition at line 1660 of file regs.h.

#define MAC_DMA_CONFIG_RX_LOAD_A_BIT   (0)

Definition at line 1662 of file regs.h.

#define MAC_DMA_CONFIG_RX_LOAD_A_BITS   (1)

Definition at line 1663 of file regs.h.

#define MAC_DMA_CONFIG_RX_LOAD_A_MASK   (0x00000001u)

Definition at line 1661 of file regs.h.

#define MAC_DMA_CONFIG_RX_LOAD_B   (0x00000002u)

Definition at line 1655 of file regs.h.

#define MAC_DMA_CONFIG_RX_LOAD_B_BIT   (1)

Definition at line 1657 of file regs.h.

#define MAC_DMA_CONFIG_RX_LOAD_B_BITS   (1)

Definition at line 1658 of file regs.h.

#define MAC_DMA_CONFIG_RX_LOAD_B_MASK   (0x00000002u)

Definition at line 1656 of file regs.h.

#define MAC_DMA_CONFIG_TX_DMA_RESET   (0x00000020u)

Definition at line 1635 of file regs.h.

#define MAC_DMA_CONFIG_TX_DMA_RESET_BIT   (5)

Definition at line 1637 of file regs.h.

#define MAC_DMA_CONFIG_TX_DMA_RESET_BITS   (1)

Definition at line 1638 of file regs.h.

#define MAC_DMA_CONFIG_TX_DMA_RESET_MASK   (0x00000020u)

Definition at line 1636 of file regs.h.

#define MAC_DMA_CONFIG_TX_LOAD_A   (0x00000004u)

Definition at line 1650 of file regs.h.

#define MAC_DMA_CONFIG_TX_LOAD_A_BIT   (2)

Definition at line 1652 of file regs.h.

#define MAC_DMA_CONFIG_TX_LOAD_A_BITS   (1)

Definition at line 1653 of file regs.h.

#define MAC_DMA_CONFIG_TX_LOAD_A_MASK   (0x00000004u)

Definition at line 1651 of file regs.h.

#define MAC_DMA_CONFIG_TX_LOAD_B   (0x00000008u)

Definition at line 1645 of file regs.h.

#define MAC_DMA_CONFIG_TX_LOAD_B_BIT   (3)

Definition at line 1647 of file regs.h.

#define MAC_DMA_CONFIG_TX_LOAD_B_BITS   (1)

Definition at line 1648 of file regs.h.

#define MAC_DMA_CONFIG_TX_LOAD_B_MASK   (0x00000008u)

Definition at line 1646 of file regs.h.

#define MAC_DMA_STATUS   *((volatile int32u *)0x4000202Cu)

Definition at line 1605 of file regs.h.

#define MAC_DMA_STATUS_ADDR   (0x4000202Cu)

Definition at line 1607 of file regs.h.

#define MAC_DMA_STATUS_REG   *((volatile int32u *)0x4000202Cu)

Definition at line 1606 of file regs.h.

#define MAC_DMA_STATUS_RESET   (0x00000000u)

Definition at line 1608 of file regs.h.

#define MAC_DMA_STATUS_RX_ACTIVE_A   (0x00000001u)

Definition at line 1625 of file regs.h.

#define MAC_DMA_STATUS_RX_ACTIVE_A_BIT   (0)

Definition at line 1627 of file regs.h.

#define MAC_DMA_STATUS_RX_ACTIVE_A_BITS   (1)

Definition at line 1628 of file regs.h.

#define MAC_DMA_STATUS_RX_ACTIVE_A_MASK   (0x00000001u)

Definition at line 1626 of file regs.h.

#define MAC_DMA_STATUS_RX_ACTIVE_B   (0x00000002u)

Definition at line 1620 of file regs.h.

#define MAC_DMA_STATUS_RX_ACTIVE_B_BIT   (1)

Definition at line 1622 of file regs.h.

#define MAC_DMA_STATUS_RX_ACTIVE_B_BITS   (1)

Definition at line 1623 of file regs.h.

#define MAC_DMA_STATUS_RX_ACTIVE_B_MASK   (0x00000002u)

Definition at line 1621 of file regs.h.

#define MAC_DMA_STATUS_TX_ACTIVE_A   (0x00000004u)

Definition at line 1615 of file regs.h.

#define MAC_DMA_STATUS_TX_ACTIVE_A_BIT   (2)

Definition at line 1617 of file regs.h.

#define MAC_DMA_STATUS_TX_ACTIVE_A_BITS   (1)

Definition at line 1618 of file regs.h.

#define MAC_DMA_STATUS_TX_ACTIVE_A_MASK   (0x00000004u)

Definition at line 1616 of file regs.h.

#define MAC_DMA_STATUS_TX_ACTIVE_B   (0x00000008u)

Definition at line 1610 of file regs.h.

#define MAC_DMA_STATUS_TX_ACTIVE_B_BIT   (3)

Definition at line 1612 of file regs.h.

#define MAC_DMA_STATUS_TX_ACTIVE_B_BITS   (1)

Definition at line 1613 of file regs.h.

#define MAC_DMA_STATUS_TX_ACTIVE_B_MASK   (0x00000008u)

Definition at line 1611 of file regs.h.

#define MAC_RSSI_DELAY   *((volatile int32u *)0x400020C0u)

Definition at line 2240 of file regs.h.

#define MAC_RSSI_DELAY_ADDR   (0x400020C0u)

Definition at line 2242 of file regs.h.

#define MAC_RSSI_DELAY_REG   *((volatile int32u *)0x400020C0u)

Definition at line 2241 of file regs.h.

#define MAC_RSSI_DELAY_RESET   (0x00000000u)

Definition at line 2243 of file regs.h.

#define MAC_RSSI_DELAY_RSSI_INST_DELAY   (0x0000003Fu)

Definition at line 2250 of file regs.h.

#define MAC_RSSI_DELAY_RSSI_INST_DELAY_BIT   (0)

Definition at line 2252 of file regs.h.

#define MAC_RSSI_DELAY_RSSI_INST_DELAY_BITS   (6)

Definition at line 2253 of file regs.h.

#define MAC_RSSI_DELAY_RSSI_INST_DELAY_MASK   (0x0000003Fu)

Definition at line 2251 of file regs.h.

#define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK   (0x00000FC0u)

Definition at line 2245 of file regs.h.

#define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK_BIT   (6)

Definition at line 2247 of file regs.h.

#define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK_BITS   (6)

Definition at line 2248 of file regs.h.

#define MAC_RSSI_DELAY_RSSI_INST_DELAY_OK_MASK   (0x00000FC0u)

Definition at line 2246 of file regs.h.

#define MAC_RX_CONFIG   *((volatile int32u *)0x40002084u)

Definition at line 1970 of file regs.h.

#define MAC_RX_CONFIG_ADDR   (0x40002084u)

Definition at line 1972 of file regs.h.

#define MAC_RX_CONFIG_APPEND_INFO   (0x00000040u)

Definition at line 1980 of file regs.h.

#define MAC_RX_CONFIG_APPEND_INFO_BIT   (6)

Definition at line 1982 of file regs.h.

#define MAC_RX_CONFIG_APPEND_INFO_BITS   (1)

Definition at line 1983 of file regs.h.

#define MAC_RX_CONFIG_APPEND_INFO_MASK   (0x00000040u)

Definition at line 1981 of file regs.h.

#define MAC_RX_CONFIG_AUTO_ACK   (0x00000080u)

Definition at line 1975 of file regs.h.

#define MAC_RX_CONFIG_AUTO_ACK_BIT   (7)

Definition at line 1977 of file regs.h.

#define MAC_RX_CONFIG_AUTO_ACK_BITS   (1)

Definition at line 1978 of file regs.h.

#define MAC_RX_CONFIG_AUTO_ACK_MASK   (0x00000080u)

Definition at line 1976 of file regs.h.

#define MAC_RX_CONFIG_COORDINATOR   (0x00000020u)

Definition at line 1985 of file regs.h.

#define MAC_RX_CONFIG_COORDINATOR_BIT   (5)

Definition at line 1987 of file regs.h.

#define MAC_RX_CONFIG_COORDINATOR_BITS   (1)

Definition at line 1988 of file regs.h.

#define MAC_RX_CONFIG_COORDINATOR_MASK   (0x00000020u)

Definition at line 1986 of file regs.h.

#define MAC_RX_CONFIG_FILT_ADDR_ON   (0x00000010u)

Definition at line 1990 of file regs.h.

#define MAC_RX_CONFIG_FILT_ADDR_ON_BIT   (4)

Definition at line 1992 of file regs.h.

#define MAC_RX_CONFIG_FILT_ADDR_ON_BITS   (1)

Definition at line 1993 of file regs.h.

#define MAC_RX_CONFIG_FILT_ADDR_ON_MASK   (0x00000010u)

Definition at line 1991 of file regs.h.

#define MAC_RX_CONFIG_FILT_FORMAT_ON   (0x00000002u)

Definition at line 2005 of file regs.h.

#define MAC_RX_CONFIG_FILT_FORMAT_ON_BIT   (1)

Definition at line 2007 of file regs.h.

#define MAC_RX_CONFIG_FILT_FORMAT_ON_BITS   (1)

Definition at line 2008 of file regs.h.

#define MAC_RX_CONFIG_FILT_FORMAT_ON_MASK   (0x00000002u)

Definition at line 2006 of file regs.h.

#define MAC_RX_CONFIG_MAC_RX_RST   (0x00000001u)

Definition at line 2010 of file regs.h.

#define MAC_RX_CONFIG_MAC_RX_RST_BIT   (0)

Definition at line 2012 of file regs.h.

#define MAC_RX_CONFIG_MAC_RX_RST_BITS   (1)

Definition at line 2013 of file regs.h.

#define MAC_RX_CONFIG_MAC_RX_RST_MASK   (0x00000001u)

Definition at line 2011 of file regs.h.

#define MAC_RX_CONFIG_REG   *((volatile int32u *)0x40002084u)

Definition at line 1971 of file regs.h.

#define MAC_RX_CONFIG_RES_FILT_PASS   (0x00000004u)

Definition at line 2000 of file regs.h.

#define MAC_RX_CONFIG_RES_FILT_PASS_ADDR   (0x00000008u)

Definition at line 1995 of file regs.h.

#define MAC_RX_CONFIG_RES_FILT_PASS_ADDR_BIT   (3)

Definition at line 1997 of file regs.h.

#define MAC_RX_CONFIG_RES_FILT_PASS_ADDR_BITS   (1)

Definition at line 1998 of file regs.h.

#define MAC_RX_CONFIG_RES_FILT_PASS_ADDR_MASK   (0x00000008u)

Definition at line 1996 of file regs.h.

#define MAC_RX_CONFIG_RES_FILT_PASS_BIT   (2)

Definition at line 2002 of file regs.h.

#define MAC_RX_CONFIG_RES_FILT_PASS_BITS   (1)

Definition at line 2003 of file regs.h.

#define MAC_RX_CONFIG_RES_FILT_PASS_MASK   (0x00000004u)

Definition at line 2001 of file regs.h.

#define MAC_RX_CONFIG_RESET   (0x00000000u)

Definition at line 1973 of file regs.h.

#define MAC_RX_END_ADDR_A   *((volatile int32u *)0x40002004u)

Definition at line 1470 of file regs.h.

#define MAC_RX_END_ADDR_A_ADDR   (0x40002004u)

Definition at line 1472 of file regs.h.

#define MAC_RX_END_ADDR_A_MAC_RAM_OFFS   (0xFFFFE000u)

Definition at line 1475 of file regs.h.

#define MAC_RX_END_ADDR_A_MAC_RAM_OFFS_BIT   (13)

Definition at line 1477 of file regs.h.

#define MAC_RX_END_ADDR_A_MAC_RAM_OFFS_BITS   (19)

Definition at line 1478 of file regs.h.

#define MAC_RX_END_ADDR_A_MAC_RAM_OFFS_MASK   (0xFFFFE000u)

Definition at line 1476 of file regs.h.

#define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A   (0x00001FFEu)

Definition at line 1480 of file regs.h.

#define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_BIT   (1)

Definition at line 1482 of file regs.h.

#define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_BITS   (12)

Definition at line 1483 of file regs.h.

#define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_MASK   (0x00001FFEu)

Definition at line 1481 of file regs.h.

#define MAC_RX_END_ADDR_A_REG   *((volatile int32u *)0x40002004u)

Definition at line 1471 of file regs.h.

#define MAC_RX_END_ADDR_A_RESET   (0x20000088u)

Definition at line 1473 of file regs.h.

#define MAC_RX_END_ADDR_B   *((volatile int32u *)0x4000200Cu)

Definition at line 1500 of file regs.h.

#define MAC_RX_END_ADDR_B_ADDR   (0x4000200Cu)

Definition at line 1502 of file regs.h.

#define MAC_RX_END_ADDR_B_MAC_RAM_OFFS   (0xFFFFE000u)

Definition at line 1505 of file regs.h.

#define MAC_RX_END_ADDR_B_MAC_RAM_OFFS_BIT   (13)

Definition at line 1507 of file regs.h.

#define MAC_RX_END_ADDR_B_MAC_RAM_OFFS_BITS   (19)

Definition at line 1508 of file regs.h.

#define MAC_RX_END_ADDR_B_MAC_RAM_OFFS_MASK   (0xFFFFE000u)

Definition at line 1506 of file regs.h.

#define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B   (0x00001FFEu)

Definition at line 1510 of file regs.h.

#define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_BIT   (1)

Definition at line 1512 of file regs.h.

#define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_BITS   (12)

Definition at line 1513 of file regs.h.

#define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_MASK   (0x00001FFEu)

Definition at line 1511 of file regs.h.

#define MAC_RX_END_ADDR_B_REG   *((volatile int32u *)0x4000200Cu)

Definition at line 1501 of file regs.h.

#define MAC_RX_END_ADDR_B_RESET   (0x20000088u)

Definition at line 1503 of file regs.h.

#define MAC_RX_INT_MASK   *((volatile int32u *)0x4000A040u)

Definition at line 3530 of file regs.h.

#define MAC_RX_INT_MASK_ADDR   (0x4000A040u)

Definition at line 3532 of file regs.h.

#define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK   (0x00000800u)

Definition at line 3555 of file regs.h.

#define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK_BIT   (11)

Definition at line 3557 of file regs.h.

#define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK_BITS   (1)

Definition at line 3558 of file regs.h.

#define MAC_RX_INT_MASK_BB_RX_LEN_ERR_MSK_MASK   (0x00000800u)

Definition at line 3556 of file regs.h.

#define MAC_RX_INT_MASK_REG   *((volatile int32u *)0x4000A040u)

Definition at line 3531 of file regs.h.

#define MAC_RX_INT_MASK_RESET   (0x00000000u)

Definition at line 3533 of file regs.h.

#define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK   (0x00000200u)

Definition at line 3565 of file regs.h.

#define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK_BIT   (9)

Definition at line 3567 of file regs.h.

#define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK_BITS   (1)

Definition at line 3568 of file regs.h.

#define MAC_RX_INT_MASK_RSSI_INST_MEAS_MSK_MASK   (0x00000200u)

Definition at line 3566 of file regs.h.

#define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK   (0x00000008u)

Definition at line 3595 of file regs.h.

#define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK_BIT   (3)

Definition at line 3597 of file regs.h.

#define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK_BITS   (1)

Definition at line 3598 of file regs.h.

#define MAC_RX_INT_MASK_RX_A_ADDR_REC_MSK_MASK   (0x00000008u)

Definition at line 3596 of file regs.h.

#define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK   (0x00000002u)

Definition at line 3605 of file regs.h.

#define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK_BIT   (1)

Definition at line 3607 of file regs.h.

#define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK_BITS   (1)

Definition at line 3608 of file regs.h.

#define MAC_RX_INT_MASK_RX_A_FILT_COMP_MSK_MASK   (0x00000002u)

Definition at line 3606 of file regs.h.

#define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK   (0x00000020u)

Definition at line 3585 of file regs.h.

#define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK_BIT   (5)

Definition at line 3587 of file regs.h.

#define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK_BITS   (1)

Definition at line 3588 of file regs.h.

#define MAC_RX_INT_MASK_RX_A_UNLOAD_COMP_MSK_MASK   (0x00000020u)

Definition at line 3586 of file regs.h.

#define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK   (0x00000010u)

Definition at line 3590 of file regs.h.

#define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK_BIT   (4)

Definition at line 3592 of file regs.h.

#define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK_BITS   (1)

Definition at line 3593 of file regs.h.

#define MAC_RX_INT_MASK_RX_B_ADDR_REC_MSK_MASK   (0x00000010u)

Definition at line 3591 of file regs.h.

#define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK   (0x00000004u)

Definition at line 3600 of file regs.h.

#define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK_BIT   (2)

Definition at line 3602 of file regs.h.

#define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK_BITS   (1)

Definition at line 3603 of file regs.h.

#define MAC_RX_INT_MASK_RX_B_FILT_COMP_MSK_MASK   (0x00000004u)

Definition at line 3601 of file regs.h.

#define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK   (0x00000040u)

Definition at line 3580 of file regs.h.

#define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK_BIT   (6)

Definition at line 3582 of file regs.h.

#define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK_BITS   (1)

Definition at line 3583 of file regs.h.

#define MAC_RX_INT_MASK_RX_B_UNLOAD_COMP_MSK_MASK   (0x00000040u)

Definition at line 3581 of file regs.h.

#define MAC_RX_INT_MASK_RX_ERROR_MSK   (0x00001000u)

Definition at line 3550 of file regs.h.

#define MAC_RX_INT_MASK_RX_ERROR_MSK_BIT   (12)

Definition at line 3552 of file regs.h.

#define MAC_RX_INT_MASK_RX_ERROR_MSK_BITS   (1)

Definition at line 3553 of file regs.h.

#define MAC_RX_INT_MASK_RX_ERROR_MSK_MASK   (0x00001000u)

Definition at line 3551 of file regs.h.

#define MAC_RX_INT_MASK_RX_FRAME_MSK   (0x00000001u)

Definition at line 3610 of file regs.h.

#define MAC_RX_INT_MASK_RX_FRAME_MSK_BIT   (0)

Definition at line 3612 of file regs.h.

#define MAC_RX_INT_MASK_RX_FRAME_MSK_BITS   (1)

Definition at line 3613 of file regs.h.

#define MAC_RX_INT_MASK_RX_FRAME_MSK_MASK   (0x00000001u)

Definition at line 3611 of file regs.h.

#define MAC_RX_INT_MASK_RX_OVFLW_MSK   (0x00002000u)

Definition at line 3545 of file regs.h.

#define MAC_RX_INT_MASK_RX_OVFLW_MSK_BIT   (13)

Definition at line 3547 of file regs.h.

#define MAC_RX_INT_MASK_RX_OVFLW_MSK_BITS   (1)

Definition at line 3548 of file regs.h.

#define MAC_RX_INT_MASK_RX_OVFLW_MSK_MASK   (0x00002000u)

Definition at line 3546 of file regs.h.

#define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK   (0x00004000u)

Definition at line 3540 of file regs.h.

#define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK_BIT   (14)

Definition at line 3542 of file regs.h.

#define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK_BITS   (1)

Definition at line 3543 of file regs.h.

#define MAC_RX_INT_MASK_TX_A_ACK_ERR_MSK_MASK   (0x00004000u)

Definition at line 3541 of file regs.h.

#define MAC_RX_INT_MASK_TX_A_ACK_MSK   (0x00000080u)

Definition at line 3575 of file regs.h.

#define MAC_RX_INT_MASK_TX_A_ACK_MSK_BIT   (7)

Definition at line 3577 of file regs.h.

#define MAC_RX_INT_MASK_TX_A_ACK_MSK_BITS   (1)

Definition at line 3578 of file regs.h.

#define MAC_RX_INT_MASK_TX_A_ACK_MSK_MASK   (0x00000080u)

Definition at line 3576 of file regs.h.

#define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK   (0x00008000u)

Definition at line 3535 of file regs.h.

#define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK_BIT   (15)

Definition at line 3537 of file regs.h.

#define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK_BITS   (1)

Definition at line 3538 of file regs.h.

#define MAC_RX_INT_MASK_TX_B_ACK_ERR_MSK_MASK   (0x00008000u)

Definition at line 3536 of file regs.h.

#define MAC_RX_INT_MASK_TX_B_ACK_MSK   (0x00000100u)

Definition at line 3570 of file regs.h.

#define MAC_RX_INT_MASK_TX_B_ACK_MSK_BIT   (8)

Definition at line 3572 of file regs.h.

#define MAC_RX_INT_MASK_TX_B_ACK_MSK_BITS   (1)

Definition at line 3573 of file regs.h.

#define MAC_RX_INT_MASK_TX_B_ACK_MSK_MASK   (0x00000100u)

Definition at line 3571 of file regs.h.

#define MAC_RX_INT_MASK_TX_COLL_RX_MSK   (0x00000400u)

Definition at line 3560 of file regs.h.

#define MAC_RX_INT_MASK_TX_COLL_RX_MSK_BIT   (10)

Definition at line 3562 of file regs.h.

#define MAC_RX_INT_MASK_TX_COLL_RX_MSK_BITS   (1)

Definition at line 3563 of file regs.h.

#define MAC_RX_INT_MASK_TX_COLL_RX_MSK_MASK   (0x00000400u)

Definition at line 3561 of file regs.h.

#define MAC_RX_INT_SRC   *((volatile int32u *)0x4000A000u)

Definition at line 3230 of file regs.h.

#define MAC_RX_INT_SRC_ADDR   (0x4000A000u)

Definition at line 3232 of file regs.h.

#define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC   (0x00000800u)

Definition at line 3255 of file regs.h.

#define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC_BIT   (11)

Definition at line 3257 of file regs.h.

#define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC_BITS   (1)

Definition at line 3258 of file regs.h.

#define MAC_RX_INT_SRC_BB_RX_LEN_ERR_SRC_MASK   (0x00000800u)

Definition at line 3256 of file regs.h.

#define MAC_RX_INT_SRC_REG   *((volatile int32u *)0x4000A000u)

Definition at line 3231 of file regs.h.

#define MAC_RX_INT_SRC_RESET   (0x00000000u)

Definition at line 3233 of file regs.h.

#define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC   (0x00000200u)

Definition at line 3265 of file regs.h.

#define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC_BIT   (9)

Definition at line 3267 of file regs.h.

#define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC_BITS   (1)

Definition at line 3268 of file regs.h.

#define MAC_RX_INT_SRC_RSSI_INST_MEAS_SRC_MASK   (0x00000200u)

Definition at line 3266 of file regs.h.

#define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC   (0x00000008u)

Definition at line 3295 of file regs.h.

#define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC_BIT   (3)

Definition at line 3297 of file regs.h.

#define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC_BITS   (1)

Definition at line 3298 of file regs.h.

#define MAC_RX_INT_SRC_RX_A_ADDR_REC_SRC_MASK   (0x00000008u)

Definition at line 3296 of file regs.h.

#define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC   (0x00000002u)

Definition at line 3305 of file regs.h.

#define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC_BIT   (1)

Definition at line 3307 of file regs.h.

#define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC_BITS   (1)

Definition at line 3308 of file regs.h.

#define MAC_RX_INT_SRC_RX_A_FILT_COMP_SRC_MASK   (0x00000002u)

Definition at line 3306 of file regs.h.

#define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC   (0x00000020u)

Definition at line 3285 of file regs.h.

#define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC_BIT   (5)

Definition at line 3287 of file regs.h.

#define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC_BITS   (1)

Definition at line 3288 of file regs.h.

#define MAC_RX_INT_SRC_RX_A_UNLOAD_COMP_SRC_MASK   (0x00000020u)

Definition at line 3286 of file regs.h.

#define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC   (0x00000010u)

Definition at line 3290 of file regs.h.

#define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC_BIT   (4)

Definition at line 3292 of file regs.h.

#define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC_BITS   (1)

Definition at line 3293 of file regs.h.

#define MAC_RX_INT_SRC_RX_B_ADDR_REC_SRC_MASK   (0x00000010u)

Definition at line 3291 of file regs.h.

#define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC   (0x00000004u)

Definition at line 3300 of file regs.h.

#define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC_BIT   (2)

Definition at line 3302 of file regs.h.

#define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC_BITS   (1)

Definition at line 3303 of file regs.h.

#define MAC_RX_INT_SRC_RX_B_FILT_COMP_SRC_MASK   (0x00000004u)

Definition at line 3301 of file regs.h.

#define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC   (0x00000040u)

Definition at line 3280 of file regs.h.

#define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC_BIT   (6)

Definition at line 3282 of file regs.h.

#define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC_BITS   (1)

Definition at line 3283 of file regs.h.

#define MAC_RX_INT_SRC_RX_B_UNLOAD_COMP_SRC_MASK   (0x00000040u)

Definition at line 3281 of file regs.h.

#define MAC_RX_INT_SRC_RX_ERROR_SRC   (0x00001000u)

Definition at line 3250 of file regs.h.

#define MAC_RX_INT_SRC_RX_ERROR_SRC_BIT   (12)

Definition at line 3252 of file regs.h.

#define MAC_RX_INT_SRC_RX_ERROR_SRC_BITS   (1)

Definition at line 3253 of file regs.h.

#define MAC_RX_INT_SRC_RX_ERROR_SRC_MASK   (0x00001000u)

Definition at line 3251 of file regs.h.

#define MAC_RX_INT_SRC_RX_FRAME_SRC   (0x00000001u)

Definition at line 3310 of file regs.h.

#define MAC_RX_INT_SRC_RX_FRAME_SRC_BIT   (0)

Definition at line 3312 of file regs.h.

#define MAC_RX_INT_SRC_RX_FRAME_SRC_BITS   (1)

Definition at line 3313 of file regs.h.

#define MAC_RX_INT_SRC_RX_FRAME_SRC_MASK   (0x00000001u)

Definition at line 3311 of file regs.h.

#define MAC_RX_INT_SRC_RX_OVFLW_SRC   (0x00002000u)

Definition at line 3245 of file regs.h.

#define MAC_RX_INT_SRC_RX_OVFLW_SRC_BIT   (13)

Definition at line 3247 of file regs.h.

#define MAC_RX_INT_SRC_RX_OVFLW_SRC_BITS   (1)

Definition at line 3248 of file regs.h.

#define MAC_RX_INT_SRC_RX_OVFLW_SRC_MASK   (0x00002000u)

Definition at line 3246 of file regs.h.

#define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC   (0x00004000u)

Definition at line 3240 of file regs.h.

#define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC_BIT   (14)

Definition at line 3242 of file regs.h.

#define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC_BITS   (1)

Definition at line 3243 of file regs.h.

#define MAC_RX_INT_SRC_TX_A_ACK_ERR_SRC_MASK   (0x00004000u)

Definition at line 3241 of file regs.h.

#define MAC_RX_INT_SRC_TX_A_ACK_SRC   (0x00000080u)

Definition at line 3275 of file regs.h.

#define MAC_RX_INT_SRC_TX_A_ACK_SRC_BIT   (7)

Definition at line 3277 of file regs.h.

#define MAC_RX_INT_SRC_TX_A_ACK_SRC_BITS   (1)

Definition at line 3278 of file regs.h.

#define MAC_RX_INT_SRC_TX_A_ACK_SRC_MASK   (0x00000080u)

Definition at line 3276 of file regs.h.

#define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC   (0x00008000u)

Definition at line 3235 of file regs.h.

#define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC_BIT   (15)

Definition at line 3237 of file regs.h.

#define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC_BITS   (1)

Definition at line 3238 of file regs.h.

#define MAC_RX_INT_SRC_TX_B_ACK_ERR_SRC_MASK   (0x00008000u)

Definition at line 3236 of file regs.h.

#define MAC_RX_INT_SRC_TX_B_ACK_SRC   (0x00000100u)

Definition at line 3270 of file regs.h.

#define MAC_RX_INT_SRC_TX_B_ACK_SRC_BIT   (8)

Definition at line 3272 of file regs.h.

#define MAC_RX_INT_SRC_TX_B_ACK_SRC_BITS   (1)

Definition at line 3273 of file regs.h.

#define MAC_RX_INT_SRC_TX_B_ACK_SRC_MASK   (0x00000100u)

Definition at line 3271 of file regs.h.

#define MAC_RX_INT_SRC_TX_COLL_RX_SRC   (0x00000400u)

Definition at line 3260 of file regs.h.

#define MAC_RX_INT_SRC_TX_COLL_RX_SRC_BIT   (10)

Definition at line 3262 of file regs.h.

#define MAC_RX_INT_SRC_TX_COLL_RX_SRC_BITS   (1)

Definition at line 3263 of file regs.h.

#define MAC_RX_INT_SRC_TX_COLL_RX_SRC_MASK   (0x00000400u)

Definition at line 3261 of file regs.h.

#define MAC_RX_ST_ADDR_A   *((volatile int32u *)0x40002000u)

Definition at line 1455 of file regs.h.

#define MAC_RX_ST_ADDR_A_ADDR   (0x40002000u)

Definition at line 1457 of file regs.h.

#define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS   (0xFFFFE000u)

Definition at line 1460 of file regs.h.

#define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS_BIT   (13)

Definition at line 1462 of file regs.h.

#define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS_BITS   (19)

Definition at line 1463 of file regs.h.

#define MAC_RX_ST_ADDR_A_MAC_RAM_OFFS_MASK   (0xFFFFE000u)

Definition at line 1461 of file regs.h.

#define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A   (0x00001FFEu)

Definition at line 1465 of file regs.h.

#define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_BIT   (1)

Definition at line 1467 of file regs.h.

#define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_BITS   (12)

Definition at line 1468 of file regs.h.

#define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_MASK   (0x00001FFEu)

Definition at line 1466 of file regs.h.

#define MAC_RX_ST_ADDR_A_REG   *((volatile int32u *)0x40002000u)

Definition at line 1456 of file regs.h.

#define MAC_RX_ST_ADDR_A_RESET   (0x20000000u)

Definition at line 1458 of file regs.h.

#define MAC_RX_ST_ADDR_B   *((volatile int32u *)0x40002008u)

Definition at line 1485 of file regs.h.

#define MAC_RX_ST_ADDR_B_ADDR   (0x40002008u)

Definition at line 1487 of file regs.h.

#define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS   (0xFFFFE000u)

Definition at line 1490 of file regs.h.

#define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS_BIT   (13)

Definition at line 1492 of file regs.h.

#define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS_BITS   (19)

Definition at line 1493 of file regs.h.

#define MAC_RX_ST_ADDR_B_MAC_RAM_OFFS_MASK   (0xFFFFE000u)

Definition at line 1491 of file regs.h.

#define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B   (0x00001FFEu)

Definition at line 1495 of file regs.h.

#define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_BIT   (1)

Definition at line 1497 of file regs.h.

#define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_BITS   (12)

Definition at line 1498 of file regs.h.

#define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_MASK   (0x00001FFEu)

Definition at line 1496 of file regs.h.

#define MAC_RX_ST_ADDR_B_REG   *((volatile int32u *)0x40002008u)

Definition at line 1486 of file regs.h.

#define MAC_RX_ST_ADDR_B_RESET   (0x20000000u)

Definition at line 1488 of file regs.h.

#define MAC_STATE   *((volatile int32u *)0x400020A8u)

Definition at line 2145 of file regs.h.

#define MAC_STATE_ACK_STATE   (0x000000C0u)

Definition at line 2155 of file regs.h.

#define MAC_STATE_ACK_STATE_BIT   (6)

Definition at line 2157 of file regs.h.

#define MAC_STATE_ACK_STATE_BITS   (2)

Definition at line 2158 of file regs.h.

#define MAC_STATE_ACK_STATE_MASK   (0x000000C0u)

Definition at line 2156 of file regs.h.

#define MAC_STATE_ADDR   (0x400020A8u)

Definition at line 2147 of file regs.h.

#define MAC_STATE_BO_STATE   (0x0000003Cu)

Definition at line 2160 of file regs.h.

#define MAC_STATE_BO_STATE_BIT   (2)

Definition at line 2162 of file regs.h.

#define MAC_STATE_BO_STATE_BITS   (4)

Definition at line 2163 of file regs.h.

#define MAC_STATE_BO_STATE_MASK   (0x0000003Cu)

Definition at line 2161 of file regs.h.

#define MAC_STATE_REG   *((volatile int32u *)0x400020A8u)

Definition at line 2146 of file regs.h.

#define MAC_STATE_RESET   (0x00000000u)

Definition at line 2148 of file regs.h.

#define MAC_STATE_SPY_STATE   (0x00000700u)

Definition at line 2150 of file regs.h.

#define MAC_STATE_SPY_STATE_BIT   (8)

Definition at line 2152 of file regs.h.

#define MAC_STATE_SPY_STATE_BITS   (3)

Definition at line 2153 of file regs.h.

#define MAC_STATE_SPY_STATE_MASK   (0x00000700u)

Definition at line 2151 of file regs.h.

#define MAC_STATE_TOP_STATE   (0x00000003u)

Definition at line 2165 of file regs.h.

#define MAC_STATE_TOP_STATE_BIT   (0)

Definition at line 2167 of file regs.h.

#define MAC_STATE_TOP_STATE_BITS   (2)

Definition at line 2168 of file regs.h.

#define MAC_STATE_TOP_STATE_MASK   (0x00000003u)

Definition at line 2166 of file regs.h.

#define MAC_STATUS   *((volatile int32u *)0x40002068u)

Definition at line 1795 of file regs.h.

#define MAC_STATUS_ADDR   (0x40002068u)

Definition at line 1797 of file regs.h.

#define MAC_STATUS_REG   *((volatile int32u *)0x40002068u)

Definition at line 1796 of file regs.h.

#define MAC_STATUS_RESET   (0x00000000u)

Definition at line 1798 of file regs.h.

#define MAC_STATUS_RUN_BO   (0x00000008u)

Definition at line 1840 of file regs.h.

#define MAC_STATUS_RUN_BO_BIT   (3)

Definition at line 1842 of file regs.h.

#define MAC_STATUS_RUN_BO_BITS   (1)

Definition at line 1843 of file regs.h.

#define MAC_STATUS_RUN_BO_MASK   (0x00000008u)

Definition at line 1841 of file regs.h.

#define MAC_STATUS_RX_A_LAST_UNLOAD   (0x00000100u)

Definition at line 1815 of file regs.h.

#define MAC_STATUS_RX_A_LAST_UNLOAD_BIT   (8)

Definition at line 1817 of file regs.h.

#define MAC_STATUS_RX_A_LAST_UNLOAD_BITS   (1)

Definition at line 1818 of file regs.h.

#define MAC_STATUS_RX_A_LAST_UNLOAD_MASK   (0x00000100u)

Definition at line 1816 of file regs.h.

#define MAC_STATUS_RX_A_PEND_TX_ACK   (0x00000400u)

Definition at line 1805 of file regs.h.

#define MAC_STATUS_RX_A_PEND_TX_ACK_BIT   (10)

Definition at line 1807 of file regs.h.

#define MAC_STATUS_RX_A_PEND_TX_ACK_BITS   (1)

Definition at line 1808 of file regs.h.

#define MAC_STATUS_RX_A_PEND_TX_ACK_MASK   (0x00000400u)

Definition at line 1806 of file regs.h.

#define MAC_STATUS_RX_ACK_REC   (0x00000020u)

Definition at line 1830 of file regs.h.

#define MAC_STATUS_RX_ACK_REC_BIT   (5)

Definition at line 1832 of file regs.h.

#define MAC_STATUS_RX_ACK_REC_BITS   (1)

Definition at line 1833 of file regs.h.

#define MAC_STATUS_RX_ACK_REC_MASK   (0x00000020u)

Definition at line 1831 of file regs.h.

#define MAC_STATUS_RX_B_LAST_UNLOAD   (0x00000200u)

Definition at line 1810 of file regs.h.

#define MAC_STATUS_RX_B_LAST_UNLOAD_BIT   (9)

Definition at line 1812 of file regs.h.

#define MAC_STATUS_RX_B_LAST_UNLOAD_BITS   (1)

Definition at line 1813 of file regs.h.

#define MAC_STATUS_RX_B_LAST_UNLOAD_MASK   (0x00000200u)

Definition at line 1811 of file regs.h.

#define MAC_STATUS_RX_B_PEND_TX_ACK   (0x00000800u)

Definition at line 1800 of file regs.h.

#define MAC_STATUS_RX_B_PEND_TX_ACK_BIT   (11)

Definition at line 1802 of file regs.h.

#define MAC_STATUS_RX_B_PEND_TX_ACK_BITS   (1)

Definition at line 1803 of file regs.h.

#define MAC_STATUS_RX_B_PEND_TX_ACK_MASK   (0x00000800u)

Definition at line 1801 of file regs.h.

#define MAC_STATUS_RX_CRC_PASS   (0x00000001u)

Definition at line 1855 of file regs.h.

#define MAC_STATUS_RX_CRC_PASS_BIT   (0)

Definition at line 1857 of file regs.h.

#define MAC_STATUS_RX_CRC_PASS_BITS   (1)

Definition at line 1858 of file regs.h.

#define MAC_STATUS_RX_CRC_PASS_MASK   (0x00000001u)

Definition at line 1856 of file regs.h.

#define MAC_STATUS_RX_FRAME   (0x00000002u)

Definition at line 1850 of file regs.h.

#define MAC_STATUS_RX_FRAME_BIT   (1)

Definition at line 1852 of file regs.h.

#define MAC_STATUS_RX_FRAME_BITS   (1)

Definition at line 1853 of file regs.h.

#define MAC_STATUS_RX_FRAME_MASK   (0x00000002u)

Definition at line 1851 of file regs.h.

#define MAC_STATUS_SENDING_ACK   (0x00000010u)

Definition at line 1835 of file regs.h.

#define MAC_STATUS_SENDING_ACK_BIT   (4)

Definition at line 1837 of file regs.h.

#define MAC_STATUS_SENDING_ACK_BITS   (1)

Definition at line 1838 of file regs.h.

#define MAC_STATUS_SENDING_ACK_MASK   (0x00000010u)

Definition at line 1836 of file regs.h.

#define MAC_STATUS_TX_FRAME   (0x00000004u)

Definition at line 1845 of file regs.h.

#define MAC_STATUS_TX_FRAME_BIT   (2)

Definition at line 1847 of file regs.h.

#define MAC_STATUS_TX_FRAME_BITS   (1)

Definition at line 1848 of file regs.h.

#define MAC_STATUS_TX_FRAME_MASK   (0x00000004u)

Definition at line 1846 of file regs.h.

#define MAC_STATUS_WRONG_ADDRESS   (0x00000040u)

Definition at line 1825 of file regs.h.

#define MAC_STATUS_WRONG_ADDRESS_BIT   (6)

Definition at line 1827 of file regs.h.

#define MAC_STATUS_WRONG_ADDRESS_BITS   (1)

Definition at line 1828 of file regs.h.

#define MAC_STATUS_WRONG_ADDRESS_MASK   (0x00000040u)

Definition at line 1826 of file regs.h.

#define MAC_STATUS_WRONG_FORMAT   (0x00000080u)

Definition at line 1820 of file regs.h.

#define MAC_STATUS_WRONG_FORMAT_BIT   (7)

Definition at line 1822 of file regs.h.

#define MAC_STATUS_WRONG_FORMAT_BITS   (1)

Definition at line 1823 of file regs.h.

#define MAC_STATUS_WRONG_FORMAT_MASK   (0x00000080u)

Definition at line 1821 of file regs.h.

#define MAC_TIMER   *((volatile int32u *)0x40002038u)

Definition at line 1665 of file regs.h.

#define MAC_TIMER_ADDR   (0x40002038u)

Definition at line 1667 of file regs.h.

#define MAC_TIMER_CAPTURE_H   *((volatile int32u *)0x40002050u)

Definition at line 1715 of file regs.h.

#define MAC_TIMER_CAPTURE_H_ADDR   (0x40002050u)

Definition at line 1717 of file regs.h.

#define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH   (0x0000000Fu)

Definition at line 1720 of file regs.h.

#define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_BIT   (0)

Definition at line 1722 of file regs.h.

#define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_BITS   (4)

Definition at line 1723 of file regs.h.

#define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_MASK   (0x0000000Fu)

Definition at line 1721 of file regs.h.

#define MAC_TIMER_CAPTURE_H_REG   *((volatile int32u *)0x40002050u)

Definition at line 1716 of file regs.h.

#define MAC_TIMER_CAPTURE_H_RESET   (0x00000000u)

Definition at line 1718 of file regs.h.

#define MAC_TIMER_CAPTURE_L   *((volatile int32u *)0x40002054u)

Definition at line 1725 of file regs.h.

#define MAC_TIMER_CAPTURE_L_ADDR   (0x40002054u)

Definition at line 1727 of file regs.h.

#define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW   (0x0000FFFFu)

Definition at line 1730 of file regs.h.

#define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_BIT   (0)

Definition at line 1732 of file regs.h.

#define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_BITS   (16)

Definition at line 1733 of file regs.h.

#define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_MASK   (0x0000FFFFu)

Definition at line 1731 of file regs.h.

#define MAC_TIMER_CAPTURE_L_REG   *((volatile int32u *)0x40002054u)

Definition at line 1726 of file regs.h.

#define MAC_TIMER_CAPTURE_L_RESET   (0x00000000u)

Definition at line 1728 of file regs.h.

#define MAC_TIMER_COMPARE_A_H   *((volatile int32u *)0x40002040u)

Definition at line 1675 of file regs.h.

#define MAC_TIMER_COMPARE_A_H_ADDR   (0x40002040u)

Definition at line 1677 of file regs.h.

#define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H   (0x0000000Fu)

Definition at line 1680 of file regs.h.

#define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_BIT   (0)

Definition at line 1682 of file regs.h.

#define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_BITS   (4)

Definition at line 1683 of file regs.h.

#define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_MASK   (0x0000000Fu)

Definition at line 1681 of file regs.h.

#define MAC_TIMER_COMPARE_A_H_REG   *((volatile int32u *)0x40002040u)

Definition at line 1676 of file regs.h.

#define MAC_TIMER_COMPARE_A_H_RESET   (0x00000000u)

Definition at line 1678 of file regs.h.

#define MAC_TIMER_COMPARE_A_L   *((volatile int32u *)0x40002044u)

Definition at line 1685 of file regs.h.

#define MAC_TIMER_COMPARE_A_L_ADDR   (0x40002044u)

Definition at line 1687 of file regs.h.

#define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L   (0x0000FFFFu)

Definition at line 1690 of file regs.h.

#define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_BIT   (0)

Definition at line 1692 of file regs.h.

#define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_BITS   (16)

Definition at line 1693 of file regs.h.

#define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_MASK   (0x0000FFFFu)

Definition at line 1691 of file regs.h.

#define MAC_TIMER_COMPARE_A_L_REG   *((volatile int32u *)0x40002044u)

Definition at line 1686 of file regs.h.

#define MAC_TIMER_COMPARE_A_L_RESET   (0x00000000u)

Definition at line 1688 of file regs.h.

#define MAC_TIMER_COMPARE_B_H   *((volatile int32u *)0x40002048u)

Definition at line 1695 of file regs.h.

#define MAC_TIMER_COMPARE_B_H_ADDR   (0x40002048u)

Definition at line 1697 of file regs.h.

#define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H   (0x0000000Fu)

Definition at line 1700 of file regs.h.

#define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_BIT   (0)

Definition at line 1702 of file regs.h.

#define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_BITS   (4)

Definition at line 1703 of file regs.h.

#define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_MASK   (0x0000000Fu)

Definition at line 1701 of file regs.h.

#define MAC_TIMER_COMPARE_B_H_REG   *((volatile int32u *)0x40002048u)

Definition at line 1696 of file regs.h.

#define MAC_TIMER_COMPARE_B_H_RESET   (0x00000000u)

Definition at line 1698 of file regs.h.

#define MAC_TIMER_COMPARE_B_L   *((volatile int32u *)0x4000204Cu)

Definition at line 1705 of file regs.h.

#define MAC_TIMER_COMPARE_B_L_ADDR   (0x4000204Cu)

Definition at line 1707 of file regs.h.

#define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L   (0x0000FFFFu)

Definition at line 1710 of file regs.h.

#define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_BIT   (0)

Definition at line 1712 of file regs.h.

#define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_BITS   (16)

Definition at line 1713 of file regs.h.

#define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_MASK   (0x0000FFFFu)

Definition at line 1711 of file regs.h.

#define MAC_TIMER_COMPARE_B_L_REG   *((volatile int32u *)0x4000204Cu)

Definition at line 1706 of file regs.h.

#define MAC_TIMER_COMPARE_B_L_RESET   (0x00000000u)

Definition at line 1708 of file regs.h.

#define MAC_TIMER_CTRL   *((volatile int32u *)0x4000208Cu)

Definition at line 2045 of file regs.h.

#define MAC_TIMER_CTRL_ADDR   (0x4000208Cu)

Definition at line 2047 of file regs.h.

#define MAC_TIMER_CTRL_BO_TIMER_EN   (0x00000004u)

Definition at line 2070 of file regs.h.

#define MAC_TIMER_CTRL_BO_TIMER_EN_BIT   (2)

Definition at line 2072 of file regs.h.

#define MAC_TIMER_CTRL_BO_TIMER_EN_BITS   (1)

Definition at line 2073 of file regs.h.

#define MAC_TIMER_CTRL_BO_TIMER_EN_MASK   (0x00000004u)

Definition at line 2071 of file regs.h.

#define MAC_TIMER_CTRL_BO_TIMER_RST   (0x00000008u)

Definition at line 2065 of file regs.h.

#define MAC_TIMER_CTRL_BO_TIMER_RST_BIT   (3)

Definition at line 2067 of file regs.h.

#define MAC_TIMER_CTRL_BO_TIMER_RST_BITS   (1)

Definition at line 2068 of file regs.h.

#define MAC_TIMER_CTRL_BO_TIMER_RST_MASK   (0x00000008u)

Definition at line 2066 of file regs.h.

#define MAC_TIMER_CTRL_BOP_TIMER_EN   (0x00000010u)

Definition at line 2060 of file regs.h.

#define MAC_TIMER_CTRL_BOP_TIMER_EN_BIT   (4)

Definition at line 2062 of file regs.h.

#define MAC_TIMER_CTRL_BOP_TIMER_EN_BITS   (1)

Definition at line 2063 of file regs.h.

#define MAC_TIMER_CTRL_BOP_TIMER_EN_MASK   (0x00000010u)

Definition at line 2061 of file regs.h.

#define MAC_TIMER_CTRL_BOP_TIMER_RST   (0x00000020u)

Definition at line 2055 of file regs.h.

#define MAC_TIMER_CTRL_BOP_TIMER_RST_BIT   (5)

Definition at line 2057 of file regs.h.

#define MAC_TIMER_CTRL_BOP_TIMER_RST_BITS   (1)

Definition at line 2058 of file regs.h.

#define MAC_TIMER_CTRL_BOP_TIMER_RST_MASK   (0x00000020u)

Definition at line 2056 of file regs.h.

#define MAC_TIMER_CTRL_COMP_A_SYNC   (0x00000040u)

Definition at line 2050 of file regs.h.

#define MAC_TIMER_CTRL_COMP_A_SYNC_BIT   (6)

Definition at line 2052 of file regs.h.

#define MAC_TIMER_CTRL_COMP_A_SYNC_BITS   (1)

Definition at line 2053 of file regs.h.

#define MAC_TIMER_CTRL_COMP_A_SYNC_MASK   (0x00000040u)

Definition at line 2051 of file regs.h.

#define MAC_TIMER_CTRL_MAC_TIMER_EN   (0x00000001u)

Definition at line 2080 of file regs.h.

#define MAC_TIMER_CTRL_MAC_TIMER_EN_BIT   (0)

Definition at line 2082 of file regs.h.

#define MAC_TIMER_CTRL_MAC_TIMER_EN_BITS   (1)

Definition at line 2083 of file regs.h.

#define MAC_TIMER_CTRL_MAC_TIMER_EN_MASK   (0x00000001u)

Definition at line 2081 of file regs.h.

#define MAC_TIMER_CTRL_MAC_TIMER_RST   (0x00000002u)

Definition at line 2075 of file regs.h.

#define MAC_TIMER_CTRL_MAC_TIMER_RST_BIT   (1)

Definition at line 2077 of file regs.h.

#define MAC_TIMER_CTRL_MAC_TIMER_RST_BITS   (1)

Definition at line 2078 of file regs.h.

#define MAC_TIMER_CTRL_MAC_TIMER_RST_MASK   (0x00000002u)

Definition at line 2076 of file regs.h.

#define MAC_TIMER_CTRL_REG   *((volatile int32u *)0x4000208Cu)

Definition at line 2046 of file regs.h.

#define MAC_TIMER_CTRL_RESET   (0x00000000u)

Definition at line 2048 of file regs.h.

#define MAC_TIMER_INT_MASK   *((volatile int32u *)0x4000A048u)

Definition at line 3680 of file regs.h.

#define MAC_TIMER_INT_MASK_ADDR   (0x4000A048u)

Definition at line 3682 of file regs.h.

#define MAC_TIMER_INT_MASK_REG   *((volatile int32u *)0x4000A048u)

Definition at line 3681 of file regs.h.

#define MAC_TIMER_INT_MASK_RESET   (0x00000000u)

Definition at line 3683 of file regs.h.

#define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK   (0x00000002u)

Definition at line 3690 of file regs.h.

#define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK_BIT   (1)

Definition at line 3692 of file regs.h.

#define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK_BITS   (1)

Definition at line 3693 of file regs.h.

#define MAC_TIMER_INT_MASK_TIMER_COMP_A_MSK_MASK   (0x00000002u)

Definition at line 3691 of file regs.h.

#define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK   (0x00000004u)

Definition at line 3685 of file regs.h.

#define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK_BIT   (2)

Definition at line 3687 of file regs.h.

#define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK_BITS   (1)

Definition at line 3688 of file regs.h.

#define MAC_TIMER_INT_MASK_TIMER_COMP_B_MSK_MASK   (0x00000004u)

Definition at line 3686 of file regs.h.

#define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK   (0x00000001u)

Definition at line 3695 of file regs.h.

#define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_BIT   (0)

Definition at line 3697 of file regs.h.

#define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_BITS   (1)

Definition at line 3698 of file regs.h.

#define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_MASK   (0x00000001u)

Definition at line 3696 of file regs.h.

#define MAC_TIMER_INT_SRC   *((volatile int32u *)0x4000A008u)

Definition at line 3380 of file regs.h.

#define MAC_TIMER_INT_SRC_ADDR   (0x4000A008u)

Definition at line 3382 of file regs.h.

#define MAC_TIMER_INT_SRC_REG   *((volatile int32u *)0x4000A008u)

Definition at line 3381 of file regs.h.

#define MAC_TIMER_INT_SRC_RESET   (0x00000000u)

Definition at line 3383 of file regs.h.

#define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC   (0x00000002u)

Definition at line 3390 of file regs.h.

#define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC_BIT   (1)

Definition at line 3392 of file regs.h.

#define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC_BITS   (1)

Definition at line 3393 of file regs.h.

#define MAC_TIMER_INT_SRC_TIMER_COMP_A_SRC_MASK   (0x00000002u)

Definition at line 3391 of file regs.h.

#define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC   (0x00000004u)

Definition at line 3385 of file regs.h.

#define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC_BIT   (2)

Definition at line 3387 of file regs.h.

#define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC_BITS   (1)

Definition at line 3388 of file regs.h.

#define MAC_TIMER_INT_SRC_TIMER_COMP_B_SRC_MASK   (0x00000004u)

Definition at line 3386 of file regs.h.

#define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC   (0x00000001u)

Definition at line 3395 of file regs.h.

#define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_BIT   (0)

Definition at line 3397 of file regs.h.

#define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_BITS   (1)

Definition at line 3398 of file regs.h.

#define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_MASK   (0x00000001u)

Definition at line 3396 of file regs.h.

#define MAC_TIMER_MAC_TIMER   (0x000FFFFFu)

Definition at line 1670 of file regs.h.

#define MAC_TIMER_MAC_TIMER_BIT   (0)

Definition at line 1672 of file regs.h.

#define MAC_TIMER_MAC_TIMER_BITS   (20)

Definition at line 1673 of file regs.h.

#define MAC_TIMER_MAC_TIMER_MASK   (0x000FFFFFu)

Definition at line 1671 of file regs.h.

#define MAC_TIMER_REG   *((volatile int32u *)0x40002038u)

Definition at line 1666 of file regs.h.

#define MAC_TIMER_RESET   (0x00000000u)

Definition at line 1668 of file regs.h.

#define MAC_TX_ACK_FRAME   *((volatile int32u *)0x4000207Cu)

Definition at line 1900 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_ACK_REQ   (0x00000020u)

Definition at line 1930 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_ACK_REQ_BIT   (5)

Definition at line 1932 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_ACK_REQ_BITS   (1)

Definition at line 1933 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_ACK_REQ_MASK   (0x00000020u)

Definition at line 1931 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_DST_AM   (0x00000C00u)

Definition at line 1915 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_DST_AM_BIT   (10)

Definition at line 1917 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_DST_AM_BITS   (2)

Definition at line 1918 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_DST_AM_MASK   (0x00000C00u)

Definition at line 1916 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_FRAME_P   (0x00000010u)

Definition at line 1935 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_FRAME_P_BIT   (4)

Definition at line 1937 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_FRAME_P_BITS   (1)

Definition at line 1938 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_FRAME_P_MASK   (0x00000010u)

Definition at line 1936 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_FRAME_T   (0x00000007u)

Definition at line 1945 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_FRAME_T_BIT   (0)

Definition at line 1947 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_FRAME_T_BITS   (3)

Definition at line 1948 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_FRAME_T_MASK   (0x00000007u)

Definition at line 1946 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_IP   (0x00000040u)

Definition at line 1925 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_IP_BIT   (6)

Definition at line 1927 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_IP_BITS   (1)

Definition at line 1928 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_IP_MASK   (0x00000040u)

Definition at line 1926 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_SEC_EN   (0x00000008u)

Definition at line 1940 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_SEC_EN_BIT   (3)

Definition at line 1942 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_SEC_EN_BITS   (1)

Definition at line 1943 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_SEC_EN_MASK   (0x00000008u)

Definition at line 1941 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_SRC_AM   (0x0000C000u)

Definition at line 1905 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_SRC_AM_BIT   (14)

Definition at line 1907 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_SRC_AM_BITS   (2)

Definition at line 1908 of file regs.h.

#define MAC_TX_ACK_FRAME_ACK_SRC_AM_MASK   (0x0000C000u)

Definition at line 1906 of file regs.h.

#define MAC_TX_ACK_FRAME_ADDR   (0x4000207Cu)

Definition at line 1902 of file regs.h.

#define MAC_TX_ACK_FRAME_REG   *((volatile int32u *)0x4000207Cu)

Definition at line 1901 of file regs.h.

#define MAC_TX_ACK_FRAME_RES1213   (0x00003000u)

Definition at line 1910 of file regs.h.

#define MAC_TX_ACK_FRAME_RES1213_BIT   (12)

Definition at line 1912 of file regs.h.

#define MAC_TX_ACK_FRAME_RES1213_BITS   (2)

Definition at line 1913 of file regs.h.

#define MAC_TX_ACK_FRAME_RES1213_MASK   (0x00003000u)

Definition at line 1911 of file regs.h.

#define MAC_TX_ACK_FRAME_RES789   (0x00000380u)

Definition at line 1920 of file regs.h.

#define MAC_TX_ACK_FRAME_RES789_BIT   (7)

Definition at line 1922 of file regs.h.

#define MAC_TX_ACK_FRAME_RES789_BITS   (3)

Definition at line 1923 of file regs.h.

#define MAC_TX_ACK_FRAME_RES789_MASK   (0x00000380u)

Definition at line 1921 of file regs.h.

#define MAC_TX_ACK_FRAME_RESET   (0x00000002u)

Definition at line 1903 of file regs.h.

#define MAC_TX_CONFIG   *((volatile int32u *)0x40002088u)

Definition at line 2015 of file regs.h.

#define MAC_TX_CONFIG_ADDR   (0x40002088u)

Definition at line 2017 of file regs.h.

#define MAC_TX_CONFIG_CCA_DELAY   (0x00000008u)

Definition at line 2025 of file regs.h.

#define MAC_TX_CONFIG_CCA_DELAY_BIT   (3)

Definition at line 2027 of file regs.h.

#define MAC_TX_CONFIG_CCA_DELAY_BITS   (1)

Definition at line 2028 of file regs.h.

#define MAC_TX_CONFIG_CCA_DELAY_MASK   (0x00000008u)

Definition at line 2026 of file regs.h.

#define MAC_TX_CONFIG_INFINITE_CRC   (0x00000002u)

Definition at line 2035 of file regs.h.

#define MAC_TX_CONFIG_INFINITE_CRC_BIT   (1)

Definition at line 2037 of file regs.h.

#define MAC_TX_CONFIG_INFINITE_CRC_BITS   (1)

Definition at line 2038 of file regs.h.

#define MAC_TX_CONFIG_INFINITE_CRC_MASK   (0x00000002u)

Definition at line 2036 of file regs.h.

#define MAC_TX_CONFIG_REG   *((volatile int32u *)0x40002088u)

Definition at line 2016 of file regs.h.

#define MAC_TX_CONFIG_RESET   (0x00000008u)

Definition at line 2018 of file regs.h.

#define MAC_TX_CONFIG_SLOTTED   (0x00000010u)

Definition at line 2020 of file regs.h.

#define MAC_TX_CONFIG_SLOTTED_ACK   (0x00000004u)

Definition at line 2030 of file regs.h.

#define MAC_TX_CONFIG_SLOTTED_ACK_BIT   (2)

Definition at line 2032 of file regs.h.

#define MAC_TX_CONFIG_SLOTTED_ACK_BITS   (1)

Definition at line 2033 of file regs.h.

#define MAC_TX_CONFIG_SLOTTED_ACK_MASK   (0x00000004u)

Definition at line 2031 of file regs.h.

#define MAC_TX_CONFIG_SLOTTED_BIT   (4)

Definition at line 2022 of file regs.h.

#define MAC_TX_CONFIG_SLOTTED_BITS   (1)

Definition at line 2023 of file regs.h.

#define MAC_TX_CONFIG_SLOTTED_MASK   (0x00000010u)

Definition at line 2021 of file regs.h.

#define MAC_TX_CONFIG_WAIT_ACK   (0x00000001u)

Definition at line 2040 of file regs.h.

#define MAC_TX_CONFIG_WAIT_ACK_BIT   (0)

Definition at line 2042 of file regs.h.

#define MAC_TX_CONFIG_WAIT_ACK_BITS   (1)

Definition at line 2043 of file regs.h.

#define MAC_TX_CONFIG_WAIT_ACK_MASK   (0x00000001u)

Definition at line 2041 of file regs.h.

#define MAC_TX_END_ADDR_A   *((volatile int32u *)0x40002014u)

Definition at line 1530 of file regs.h.

#define MAC_TX_END_ADDR_A_ADDR   (0x40002014u)

Definition at line 1532 of file regs.h.

#define MAC_TX_END_ADDR_A_MAC_RAM_OFFS   (0xFFFFE000u)

Definition at line 1535 of file regs.h.

#define MAC_TX_END_ADDR_A_MAC_RAM_OFFS_BIT   (13)

Definition at line 1537 of file regs.h.

#define MAC_TX_END_ADDR_A_MAC_RAM_OFFS_BITS   (19)

Definition at line 1538 of file regs.h.

#define MAC_TX_END_ADDR_A_MAC_RAM_OFFS_MASK   (0xFFFFE000u)

Definition at line 1536 of file regs.h.

#define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A   (0x00001FFEu)

Definition at line 1540 of file regs.h.

#define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_BIT   (1)

Definition at line 1542 of file regs.h.

#define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_BITS   (12)

Definition at line 1543 of file regs.h.

#define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_MASK   (0x00001FFEu)

Definition at line 1541 of file regs.h.

#define MAC_TX_END_ADDR_A_REG   *((volatile int32u *)0x40002014u)

Definition at line 1531 of file regs.h.

#define MAC_TX_END_ADDR_A_RESET   (0x20000000u)

Definition at line 1533 of file regs.h.

#define MAC_TX_END_ADDR_B   *((volatile int32u *)0x4000201Cu)

Definition at line 1560 of file regs.h.

#define MAC_TX_END_ADDR_B_ADDR   (0x4000201Cu)

Definition at line 1562 of file regs.h.

#define MAC_TX_END_ADDR_B_MAC_RAM_OFFS   (0xFFFFE000u)

Definition at line 1565 of file regs.h.

#define MAC_TX_END_ADDR_B_MAC_RAM_OFFS_BIT   (13)

Definition at line 1567 of file regs.h.

#define MAC_TX_END_ADDR_B_MAC_RAM_OFFS_BITS   (19)

Definition at line 1568 of file regs.h.

#define MAC_TX_END_ADDR_B_MAC_RAM_OFFS_MASK   (0xFFFFE000u)

Definition at line 1566 of file regs.h.

#define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B   (0x00001FFEu)

Definition at line 1570 of file regs.h.

#define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_BIT   (1)

Definition at line 1572 of file regs.h.

#define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_BITS   (12)

Definition at line 1573 of file regs.h.

#define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_MASK   (0x00001FFEu)

Definition at line 1571 of file regs.h.

#define MAC_TX_END_ADDR_B_REG   *((volatile int32u *)0x4000201Cu)

Definition at line 1561 of file regs.h.

#define MAC_TX_END_ADDR_B_RESET   (0x20000000u)

Definition at line 1563 of file regs.h.

#define MAC_TX_INT_MASK   *((volatile int32u *)0x4000A044u)

Definition at line 3615 of file regs.h.

#define MAC_TX_INT_MASK_ACK_EXPIRED_MSK   (0x00000080u)

Definition at line 3640 of file regs.h.

#define MAC_TX_INT_MASK_ACK_EXPIRED_MSK_BIT   (7)

Definition at line 3642 of file regs.h.

#define MAC_TX_INT_MASK_ACK_EXPIRED_MSK_BITS   (1)

Definition at line 3643 of file regs.h.

#define MAC_TX_INT_MASK_ACK_EXPIRED_MSK_MASK   (0x00000080u)

Definition at line 3641 of file regs.h.

#define MAC_TX_INT_MASK_ADDR   (0x4000A044u)

Definition at line 3617 of file regs.h.

#define MAC_TX_INT_MASK_BO_COMPLETE_MSK   (0x00000004u)

Definition at line 3665 of file regs.h.

#define MAC_TX_INT_MASK_BO_COMPLETE_MSK_BIT   (2)

Definition at line 3667 of file regs.h.

#define MAC_TX_INT_MASK_BO_COMPLETE_MSK_BITS   (1)

Definition at line 3668 of file regs.h.

#define MAC_TX_INT_MASK_BO_COMPLETE_MSK_MASK   (0x00000004u)

Definition at line 3666 of file regs.h.

#define MAC_TX_INT_MASK_CCA_FAIL_MSK   (0x00000010u)

Definition at line 3655 of file regs.h.

#define MAC_TX_INT_MASK_CCA_FAIL_MSK_BIT   (4)

Definition at line 3657 of file regs.h.

#define MAC_TX_INT_MASK_CCA_FAIL_MSK_BITS   (1)

Definition at line 3658 of file regs.h.

#define MAC_TX_INT_MASK_CCA_FAIL_MSK_MASK   (0x00000010u)

Definition at line 3656 of file regs.h.

#define MAC_TX_INT_MASK_REG   *((volatile int32u *)0x4000A044u)

Definition at line 3616 of file regs.h.

#define MAC_TX_INT_MASK_RESET   (0x00000000u)

Definition at line 3618 of file regs.h.

#define MAC_TX_INT_MASK_RX_A_ACK_MSK   (0x00000400u)

Definition at line 3625 of file regs.h.

#define MAC_TX_INT_MASK_RX_A_ACK_MSK_BIT   (10)

Definition at line 3627 of file regs.h.

#define MAC_TX_INT_MASK_RX_A_ACK_MSK_BITS   (1)

Definition at line 3628 of file regs.h.

#define MAC_TX_INT_MASK_RX_A_ACK_MSK_MASK   (0x00000400u)

Definition at line 3626 of file regs.h.

#define MAC_TX_INT_MASK_RX_ACK_MSK   (0x00000002u)

Definition at line 3670 of file regs.h.

#define MAC_TX_INT_MASK_RX_ACK_MSK_BIT   (1)

Definition at line 3672 of file regs.h.

#define MAC_TX_INT_MASK_RX_ACK_MSK_BITS   (1)

Definition at line 3673 of file regs.h.

#define MAC_TX_INT_MASK_RX_ACK_MSK_MASK   (0x00000002u)

Definition at line 3671 of file regs.h.

#define MAC_TX_INT_MASK_RX_B_ACK_MSK   (0x00000800u)

Definition at line 3620 of file regs.h.

#define MAC_TX_INT_MASK_RX_B_ACK_MSK_BIT   (11)

Definition at line 3622 of file regs.h.

#define MAC_TX_INT_MASK_RX_B_ACK_MSK_BITS   (1)

Definition at line 3623 of file regs.h.

#define MAC_TX_INT_MASK_RX_B_ACK_MSK_MASK   (0x00000800u)

Definition at line 3621 of file regs.h.

#define MAC_TX_INT_MASK_SFD_SENT_MSK   (0x00000008u)

Definition at line 3660 of file regs.h.

#define MAC_TX_INT_MASK_SFD_SENT_MSK_BIT   (3)

Definition at line 3662 of file regs.h.

#define MAC_TX_INT_MASK_SFD_SENT_MSK_BITS   (1)

Definition at line 3663 of file regs.h.

#define MAC_TX_INT_MASK_SFD_SENT_MSK_MASK   (0x00000008u)

Definition at line 3661 of file regs.h.

#define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK   (0x00000100u)

Definition at line 3635 of file regs.h.

#define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK_BIT   (8)

Definition at line 3637 of file regs.h.

#define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK_BITS   (1)

Definition at line 3638 of file regs.h.

#define MAC_TX_INT_MASK_TX_A_UNLOAD_MSK_MASK   (0x00000100u)

Definition at line 3636 of file regs.h.

#define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK   (0x00000200u)

Definition at line 3630 of file regs.h.

#define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK_BIT   (9)

Definition at line 3632 of file regs.h.

#define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK_BITS   (1)

Definition at line 3633 of file regs.h.

#define MAC_TX_INT_MASK_TX_B_UNLOAD_MSK_MASK   (0x00000200u)

Definition at line 3631 of file regs.h.

#define MAC_TX_INT_MASK_TX_COMPLETE_MSK   (0x00000001u)

Definition at line 3675 of file regs.h.

#define MAC_TX_INT_MASK_TX_COMPLETE_MSK_BIT   (0)

Definition at line 3677 of file regs.h.

#define MAC_TX_INT_MASK_TX_COMPLETE_MSK_BITS   (1)

Definition at line 3678 of file regs.h.

#define MAC_TX_INT_MASK_TX_COMPLETE_MSK_MASK   (0x00000001u)

Definition at line 3676 of file regs.h.

#define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK   (0x00000040u)

Definition at line 3645 of file regs.h.

#define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK_BIT   (6)

Definition at line 3647 of file regs.h.

#define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK_BITS   (1)

Definition at line 3648 of file regs.h.

#define MAC_TX_INT_MASK_TX_LOCK_FAIL_MSK_MASK   (0x00000040u)

Definition at line 3646 of file regs.h.

#define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK   (0x00000020u)

Definition at line 3650 of file regs.h.

#define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK_BIT   (5)

Definition at line 3652 of file regs.h.

#define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK_BITS   (1)

Definition at line 3653 of file regs.h.

#define MAC_TX_INT_MASK_TX_UNDERFLOW_MSK_MASK   (0x00000020u)

Definition at line 3651 of file regs.h.

#define MAC_TX_INT_SRC   *((volatile int32u *)0x4000A004u)

Definition at line 3315 of file regs.h.

#define MAC_TX_INT_SRC_ACK_EXPIRED_SRC   (0x00000080u)

Definition at line 3340 of file regs.h.

#define MAC_TX_INT_SRC_ACK_EXPIRED_SRC_BIT   (7)

Definition at line 3342 of file regs.h.

#define MAC_TX_INT_SRC_ACK_EXPIRED_SRC_BITS   (1)

Definition at line 3343 of file regs.h.

#define MAC_TX_INT_SRC_ACK_EXPIRED_SRC_MASK   (0x00000080u)

Definition at line 3341 of file regs.h.

#define MAC_TX_INT_SRC_ADDR   (0x4000A004u)

Definition at line 3317 of file regs.h.

#define MAC_TX_INT_SRC_BO_COMPLETE_SRC   (0x00000004u)

Definition at line 3365 of file regs.h.

#define MAC_TX_INT_SRC_BO_COMPLETE_SRC_BIT   (2)

Definition at line 3367 of file regs.h.

#define MAC_TX_INT_SRC_BO_COMPLETE_SRC_BITS   (1)

Definition at line 3368 of file regs.h.

#define MAC_TX_INT_SRC_BO_COMPLETE_SRC_MASK   (0x00000004u)

Definition at line 3366 of file regs.h.

#define MAC_TX_INT_SRC_CCA_FAIL_SRC   (0x00000010u)

Definition at line 3355 of file regs.h.

#define MAC_TX_INT_SRC_CCA_FAIL_SRC_BIT   (4)

Definition at line 3357 of file regs.h.

#define MAC_TX_INT_SRC_CCA_FAIL_SRC_BITS   (1)

Definition at line 3358 of file regs.h.

#define MAC_TX_INT_SRC_CCA_FAIL_SRC_MASK   (0x00000010u)

Definition at line 3356 of file regs.h.

#define MAC_TX_INT_SRC_REG   *((volatile int32u *)0x4000A004u)

Definition at line 3316 of file regs.h.

#define MAC_TX_INT_SRC_RESET   (0x00000000u)

Definition at line 3318 of file regs.h.

#define MAC_TX_INT_SRC_RX_A_ACK_SRC   (0x00000400u)

Definition at line 3325 of file regs.h.

#define MAC_TX_INT_SRC_RX_A_ACK_SRC_BIT   (10)

Definition at line 3327 of file regs.h.

#define MAC_TX_INT_SRC_RX_A_ACK_SRC_BITS   (1)

Definition at line 3328 of file regs.h.

#define MAC_TX_INT_SRC_RX_A_ACK_SRC_MASK   (0x00000400u)

Definition at line 3326 of file regs.h.

#define MAC_TX_INT_SRC_RX_ACK_SRC   (0x00000002u)

Definition at line 3370 of file regs.h.

#define MAC_TX_INT_SRC_RX_ACK_SRC_BIT   (1)

Definition at line 3372 of file regs.h.

#define MAC_TX_INT_SRC_RX_ACK_SRC_BITS   (1)

Definition at line 3373 of file regs.h.

#define MAC_TX_INT_SRC_RX_ACK_SRC_MASK   (0x00000002u)

Definition at line 3371 of file regs.h.

#define MAC_TX_INT_SRC_RX_B_ACK_SRC   (0x00000800u)

Definition at line 3320 of file regs.h.

#define MAC_TX_INT_SRC_RX_B_ACK_SRC_BIT   (11)

Definition at line 3322 of file regs.h.

#define MAC_TX_INT_SRC_RX_B_ACK_SRC_BITS   (1)

Definition at line 3323 of file regs.h.

#define MAC_TX_INT_SRC_RX_B_ACK_SRC_MASK   (0x00000800u)

Definition at line 3321 of file regs.h.

#define MAC_TX_INT_SRC_SFD_SENT_SRC   (0x00000008u)

Definition at line 3360 of file regs.h.

#define MAC_TX_INT_SRC_SFD_SENT_SRC_BIT   (3)

Definition at line 3362 of file regs.h.

#define MAC_TX_INT_SRC_SFD_SENT_SRC_BITS   (1)

Definition at line 3363 of file regs.h.

#define MAC_TX_INT_SRC_SFD_SENT_SRC_MASK   (0x00000008u)

Definition at line 3361 of file regs.h.

#define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC   (0x00000100u)

Definition at line 3335 of file regs.h.

#define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC_BIT   (8)

Definition at line 3337 of file regs.h.

#define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC_BITS   (1)

Definition at line 3338 of file regs.h.

#define MAC_TX_INT_SRC_TX_A_UNLOAD_SRC_MASK   (0x00000100u)

Definition at line 3336 of file regs.h.

#define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC   (0x00000200u)

Definition at line 3330 of file regs.h.

#define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC_BIT   (9)

Definition at line 3332 of file regs.h.

#define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC_BITS   (1)

Definition at line 3333 of file regs.h.

#define MAC_TX_INT_SRC_TX_B_UNLOAD_SRC_MASK   (0x00000200u)

Definition at line 3331 of file regs.h.

#define MAC_TX_INT_SRC_TX_COMPLETE_SRC   (0x00000001u)

Definition at line 3375 of file regs.h.

#define MAC_TX_INT_SRC_TX_COMPLETE_SRC_BIT   (0)

Definition at line 3377 of file regs.h.

#define MAC_TX_INT_SRC_TX_COMPLETE_SRC_BITS   (1)

Definition at line 3378 of file regs.h.

#define MAC_TX_INT_SRC_TX_COMPLETE_SRC_MASK   (0x00000001u)

Definition at line 3376 of file regs.h.

#define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC   (0x00000040u)

Definition at line 3345 of file regs.h.

#define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC_BIT   (6)

Definition at line 3347 of file regs.h.

#define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC_BITS   (1)

Definition at line 3348 of file regs.h.

#define MAC_TX_INT_SRC_TX_LOCK_FAIL_SRC_MASK   (0x00000040u)

Definition at line 3346 of file regs.h.

#define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC   (0x00000020u)

Definition at line 3350 of file regs.h.

#define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC_BIT   (5)

Definition at line 3352 of file regs.h.

#define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC_BITS   (1)

Definition at line 3353 of file regs.h.

#define MAC_TX_INT_SRC_TX_UNDERFLOW_SRC_MASK   (0x00000020u)

Definition at line 3351 of file regs.h.

#define MAC_TX_ST_ADDR_A   *((volatile int32u *)0x40002010u)

Definition at line 1515 of file regs.h.

#define MAC_TX_ST_ADDR_A_ADDR   (0x40002010u)

Definition at line 1517 of file regs.h.

#define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS   (0xFFFFE000u)

Definition at line 1520 of file regs.h.

#define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS_BIT   (13)

Definition at line 1522 of file regs.h.

#define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS_BITS   (19)

Definition at line 1523 of file regs.h.

#define MAC_TX_ST_ADDR_A_MAC_RAM_OFFS_MASK   (0xFFFFE000u)

Definition at line 1521 of file regs.h.

#define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A   (0x00001FFEu)

Definition at line 1525 of file regs.h.

#define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_BIT   (1)

Definition at line 1527 of file regs.h.

#define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_BITS   (12)

Definition at line 1528 of file regs.h.

#define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_MASK   (0x00001FFEu)

Definition at line 1526 of file regs.h.

#define MAC_TX_ST_ADDR_A_REG   *((volatile int32u *)0x40002010u)

Definition at line 1516 of file regs.h.

#define MAC_TX_ST_ADDR_A_RESET   (0x20000000u)

Definition at line 1518 of file regs.h.

#define MAC_TX_ST_ADDR_B   *((volatile int32u *)0x40002018u)

Definition at line 1545 of file regs.h.

#define MAC_TX_ST_ADDR_B_ADDR   (0x40002018u)

Definition at line 1547 of file regs.h.

#define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS   (0xFFFFE000u)

Definition at line 1550 of file regs.h.

#define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS_BIT   (13)

Definition at line 1552 of file regs.h.

#define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS_BITS   (19)

Definition at line 1553 of file regs.h.

#define MAC_TX_ST_ADDR_B_MAC_RAM_OFFS_MASK   (0xFFFFE000u)

Definition at line 1551 of file regs.h.

#define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B   (0x00001FFEu)

Definition at line 1555 of file regs.h.

#define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_BIT   (1)

Definition at line 1557 of file regs.h.

#define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_BITS   (12)

Definition at line 1558 of file regs.h.

#define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_MASK   (0x00001FFEu)

Definition at line 1556 of file regs.h.

#define MAC_TX_ST_ADDR_B_REG   *((volatile int32u *)0x40002018u)

Definition at line 1546 of file regs.h.

#define MAC_TX_ST_ADDR_B_RESET   (0x20000000u)

Definition at line 1548 of file regs.h.

#define MAC_TX_STROBE   *((volatile int32u *)0x40002060u)

Definition at line 1755 of file regs.h.

#define MAC_TX_STROBE_ADDR   (0x40002060u)

Definition at line 1757 of file regs.h.

#define MAC_TX_STROBE_AUTO_CRC_TX   (0x00000008u)

Definition at line 1760 of file regs.h.

#define MAC_TX_STROBE_AUTO_CRC_TX_BIT   (3)

Definition at line 1762 of file regs.h.

#define MAC_TX_STROBE_AUTO_CRC_TX_BITS   (1)

Definition at line 1763 of file regs.h.

#define MAC_TX_STROBE_AUTO_CRC_TX_MASK   (0x00000008u)

Definition at line 1761 of file regs.h.

#define MAC_TX_STROBE_CCA_ON   (0x00000004u)

Definition at line 1765 of file regs.h.

#define MAC_TX_STROBE_CCA_ON_BIT   (2)

Definition at line 1767 of file regs.h.

#define MAC_TX_STROBE_CCA_ON_BITS   (1)

Definition at line 1768 of file regs.h.

#define MAC_TX_STROBE_CCA_ON_MASK   (0x00000004u)

Definition at line 1766 of file regs.h.

#define MAC_TX_STROBE_MAC_TX_RST   (0x00000002u)

Definition at line 1770 of file regs.h.

#define MAC_TX_STROBE_MAC_TX_RST_BIT   (1)

Definition at line 1772 of file regs.h.

#define MAC_TX_STROBE_MAC_TX_RST_BITS   (1)

Definition at line 1773 of file regs.h.

#define MAC_TX_STROBE_MAC_TX_RST_MASK   (0x00000002u)

Definition at line 1771 of file regs.h.

#define MAC_TX_STROBE_REG   *((volatile int32u *)0x40002060u)

Definition at line 1756 of file regs.h.

#define MAC_TX_STROBE_RESET   (0x00000000u)

Definition at line 1758 of file regs.h.

#define MAC_TX_STROBE_START_TX   (0x00000001u)

Definition at line 1775 of file regs.h.

#define MAC_TX_STROBE_START_TX_BIT   (0)

Definition at line 1777 of file regs.h.

#define MAC_TX_STROBE_START_TX_BITS   (1)

Definition at line 1778 of file regs.h.

#define MAC_TX_STROBE_START_TX_MASK   (0x00000001u)

Definition at line 1776 of file regs.h.

#define MEM_PROT_0   *((volatile int32u *)0x40005000u)

Definition at line 2640 of file regs.h.

#define MEM_PROT_0_ADDR   (0x40005000u)

Definition at line 2642 of file regs.h.

#define MEM_PROT_0_MEM_PROT_0   (0xFFFFFFFFu)

Definition at line 2645 of file regs.h.

#define MEM_PROT_0_MEM_PROT_0_BIT   (0)

Definition at line 2647 of file regs.h.

#define MEM_PROT_0_MEM_PROT_0_BITS   (32)

Definition at line 2648 of file regs.h.

#define MEM_PROT_0_MEM_PROT_0_MASK   (0xFFFFFFFFu)

Definition at line 2646 of file regs.h.

#define MEM_PROT_0_REG   *((volatile int32u *)0x40005000u)

Definition at line 2641 of file regs.h.

#define MEM_PROT_0_RESET   (0x00000000u)

Definition at line 2643 of file regs.h.

#define MEM_PROT_1   *((volatile int32u *)0x40005004u)

Definition at line 2650 of file regs.h.

#define MEM_PROT_1_ADDR   (0x40005004u)

Definition at line 2652 of file regs.h.

#define MEM_PROT_1_MEM_PROT_1   (0xFFFFFFFFu)

Definition at line 2655 of file regs.h.

#define MEM_PROT_1_MEM_PROT_1_BIT   (0)

Definition at line 2657 of file regs.h.

#define MEM_PROT_1_MEM_PROT_1_BITS   (32)

Definition at line 2658 of file regs.h.

#define MEM_PROT_1_MEM_PROT_1_MASK   (0xFFFFFFFFu)

Definition at line 2656 of file regs.h.

#define MEM_PROT_1_REG   *((volatile int32u *)0x40005004u)

Definition at line 2651 of file regs.h.

#define MEM_PROT_1_RESET   (0x00000000u)

Definition at line 2653 of file regs.h.

#define MEM_PROT_2   *((volatile int32u *)0x40005008u)

Definition at line 2660 of file regs.h.

#define MEM_PROT_2_ADDR   (0x40005008u)

Definition at line 2662 of file regs.h.

#define MEM_PROT_2_MEM_PROT_2   (0xFFFFFFFFu)

Definition at line 2665 of file regs.h.

#define MEM_PROT_2_MEM_PROT_2_BIT   (0)

Definition at line 2667 of file regs.h.

#define MEM_PROT_2_MEM_PROT_2_BITS   (32)

Definition at line 2668 of file regs.h.

#define MEM_PROT_2_MEM_PROT_2_MASK   (0xFFFFFFFFu)

Definition at line 2666 of file regs.h.

#define MEM_PROT_2_REG   *((volatile int32u *)0x40005008u)

Definition at line 2661 of file regs.h.

#define MEM_PROT_2_RESET   (0x00000000u)

Definition at line 2663 of file regs.h.

#define MEM_PROT_3   *((volatile int32u *)0x4000500Cu)

Definition at line 2670 of file regs.h.

#define MEM_PROT_3_ADDR   (0x4000500Cu)

Definition at line 2672 of file regs.h.

#define MEM_PROT_3_MEM_PROT_3   (0xFFFFFFFFu)

Definition at line 2675 of file regs.h.

#define MEM_PROT_3_MEM_PROT_3_BIT   (0)

Definition at line 2677 of file regs.h.

#define MEM_PROT_3_MEM_PROT_3_BITS   (32)

Definition at line 2678 of file regs.h.

#define MEM_PROT_3_MEM_PROT_3_MASK   (0xFFFFFFFFu)

Definition at line 2676 of file regs.h.

#define MEM_PROT_3_REG   *((volatile int32u *)0x4000500Cu)

Definition at line 2671 of file regs.h.

#define MEM_PROT_3_RESET   (0x00000000u)

Definition at line 2673 of file regs.h.

#define MEM_PROT_4   *((volatile int32u *)0x40005010u)

Definition at line 2680 of file regs.h.

#define MEM_PROT_4_ADDR   (0x40005010u)

Definition at line 2682 of file regs.h.

#define MEM_PROT_4_MEM_PROT_4   (0xFFFFFFFFu)

Definition at line 2685 of file regs.h.

#define MEM_PROT_4_MEM_PROT_4_BIT   (0)

Definition at line 2687 of file regs.h.

#define MEM_PROT_4_MEM_PROT_4_BITS   (32)

Definition at line 2688 of file regs.h.

#define MEM_PROT_4_MEM_PROT_4_MASK   (0xFFFFFFFFu)

Definition at line 2686 of file regs.h.

#define MEM_PROT_4_REG   *((volatile int32u *)0x40005010u)

Definition at line 2681 of file regs.h.

#define MEM_PROT_4_RESET   (0x00000000u)

Definition at line 2683 of file regs.h.

#define MEM_PROT_5   *((volatile int32u *)0x40005014u)

Definition at line 2690 of file regs.h.

#define MEM_PROT_5_ADDR   (0x40005014u)

Definition at line 2692 of file regs.h.

#define MEM_PROT_5_MEM_PROT_5   (0xFFFFFFFFu)

Definition at line 2695 of file regs.h.

#define MEM_PROT_5_MEM_PROT_5_BIT   (0)

Definition at line 2697 of file regs.h.

#define MEM_PROT_5_MEM_PROT_5_BITS   (32)

Definition at line 2698 of file regs.h.

#define MEM_PROT_5_MEM_PROT_5_MASK   (0xFFFFFFFFu)

Definition at line 2696 of file regs.h.

#define MEM_PROT_5_REG   *((volatile int32u *)0x40005014u)

Definition at line 2691 of file regs.h.

#define MEM_PROT_5_RESET   (0x00000000u)

Definition at line 2693 of file regs.h.

#define MEM_PROT_6   *((volatile int32u *)0x40005018u)

Definition at line 2700 of file regs.h.

#define MEM_PROT_6_ADDR   (0x40005018u)

Definition at line 2702 of file regs.h.

#define MEM_PROT_6_MEM_PROT_6   (0xFFFFFFFFu)

Definition at line 2705 of file regs.h.

#define MEM_PROT_6_MEM_PROT_6_BIT   (0)

Definition at line 2707 of file regs.h.

#define MEM_PROT_6_MEM_PROT_6_BITS   (32)

Definition at line 2708 of file regs.h.

#define MEM_PROT_6_MEM_PROT_6_MASK   (0xFFFFFFFFu)

Definition at line 2706 of file regs.h.

#define MEM_PROT_6_REG   *((volatile int32u *)0x40005018u)

Definition at line 2701 of file regs.h.

#define MEM_PROT_6_RESET   (0x00000000u)

Definition at line 2703 of file regs.h.

#define MEM_PROT_7   *((volatile int32u *)0x4000501Cu)

Definition at line 2710 of file regs.h.

#define MEM_PROT_7_ADDR   (0x4000501Cu)

Definition at line 2712 of file regs.h.

#define MEM_PROT_7_MEM_PROT_7   (0xFFFFFFFFu)

Definition at line 2715 of file regs.h.

#define MEM_PROT_7_MEM_PROT_7_BIT   (0)

Definition at line 2717 of file regs.h.

#define MEM_PROT_7_MEM_PROT_7_BITS   (32)

Definition at line 2718 of file regs.h.

#define MEM_PROT_7_MEM_PROT_7_MASK   (0xFFFFFFFFu)

Definition at line 2716 of file regs.h.

#define MEM_PROT_7_REG   *((volatile int32u *)0x4000501Cu)

Definition at line 2711 of file regs.h.

#define MEM_PROT_7_RESET   (0x00000000u)

Definition at line 2713 of file regs.h.

#define MEM_PROT_EN   *((volatile int32u *)0x40005028u)

Definition at line 2745 of file regs.h.

#define MEM_PROT_EN_ADDR   (0x40005028u)

Definition at line 2747 of file regs.h.

#define MEM_PROT_EN_DMA_PROT_EN_MAC   (0x00000002u)

Definition at line 2755 of file regs.h.

#define MEM_PROT_EN_DMA_PROT_EN_MAC_BIT   (1)

Definition at line 2757 of file regs.h.

#define MEM_PROT_EN_DMA_PROT_EN_MAC_BITS   (1)

Definition at line 2758 of file regs.h.

#define MEM_PROT_EN_DMA_PROT_EN_MAC_MASK   (0x00000002u)

Definition at line 2756 of file regs.h.

#define MEM_PROT_EN_DMA_PROT_EN_OTHER   (0x00000001u)

Definition at line 2760 of file regs.h.

#define MEM_PROT_EN_DMA_PROT_EN_OTHER_BIT   (0)

Definition at line 2762 of file regs.h.

#define MEM_PROT_EN_DMA_PROT_EN_OTHER_BITS   (1)

Definition at line 2763 of file regs.h.

#define MEM_PROT_EN_DMA_PROT_EN_OTHER_MASK   (0x00000001u)

Definition at line 2761 of file regs.h.

#define MEM_PROT_EN_FORCE_PROT   (0x00000004u)

Definition at line 2750 of file regs.h.

#define MEM_PROT_EN_FORCE_PROT_BIT   (2)

Definition at line 2752 of file regs.h.

#define MEM_PROT_EN_FORCE_PROT_BITS   (1)

Definition at line 2753 of file regs.h.

#define MEM_PROT_EN_FORCE_PROT_MASK   (0x00000004u)

Definition at line 2751 of file regs.h.

#define MEM_PROT_EN_REG   *((volatile int32u *)0x40005028u)

Definition at line 2746 of file regs.h.

#define MEM_PROT_EN_RESET   (0x00000000u)

Definition at line 2748 of file regs.h.

#define MIXER_GAIN_STEP   *((volatile int32u *)0x400010ACu)

Definition at line 1010 of file regs.h.

#define MIXER_GAIN_STEP_ADDR   (0x400010ACu)

Definition at line 1012 of file regs.h.

#define MIXER_GAIN_STEP_MIXER_GAIN_STEP   (0x0000000Fu)

Definition at line 1015 of file regs.h.

#define MIXER_GAIN_STEP_MIXER_GAIN_STEP_BIT   (0)

Definition at line 1017 of file regs.h.

#define MIXER_GAIN_STEP_MIXER_GAIN_STEP_BITS   (4)

Definition at line 1018 of file regs.h.

#define MIXER_GAIN_STEP_MIXER_GAIN_STEP_MASK   (0x0000000Fu)

Definition at line 1016 of file regs.h.

#define MIXER_GAIN_STEP_REG   *((volatile int32u *)0x400010ACu)

Definition at line 1011 of file regs.h.

#define MIXER_GAIN_STEP_RESET   (0x0000000Cu)

Definition at line 1013 of file regs.h.

#define MOD_CAL_COUNT_H   *((volatile int32u *)0x40001004u)

Definition at line 405 of file regs.h.

#define MOD_CAL_COUNT_H_ADDR   (0x40001004u)

Definition at line 407 of file regs.h.

#define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H   (0x000000FFu)

Definition at line 410 of file regs.h.

#define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_BIT   (0)

Definition at line 412 of file regs.h.

#define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_BITS   (8)

Definition at line 413 of file regs.h.

#define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_MASK   (0x000000FFu)

Definition at line 411 of file regs.h.

#define MOD_CAL_COUNT_H_REG   *((volatile int32u *)0x40001004u)

Definition at line 406 of file regs.h.

#define MOD_CAL_COUNT_H_RESET   (0x00000000u)

Definition at line 408 of file regs.h.

#define MOD_CAL_COUNT_L   *((volatile int32u *)0x40001008u)

Definition at line 415 of file regs.h.

#define MOD_CAL_COUNT_L_ADDR   (0x40001008u)

Definition at line 417 of file regs.h.

#define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L   (0x0000FFFFu)

Definition at line 420 of file regs.h.

#define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_BIT   (0)

Definition at line 422 of file regs.h.

#define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_BITS   (16)

Definition at line 423 of file regs.h.

#define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_MASK   (0x0000FFFFu)

Definition at line 421 of file regs.h.

#define MOD_CAL_COUNT_L_REG   *((volatile int32u *)0x40001008u)

Definition at line 416 of file regs.h.

#define MOD_CAL_COUNT_L_RESET   (0x00000000u)

Definition at line 418 of file regs.h.

#define MOD_CAL_CTRL   *((volatile int32u *)0x40001000u)

Definition at line 385 of file regs.h.

#define MOD_CAL_CTRL_ADDR   (0x40001000u)

Definition at line 387 of file regs.h.

#define MOD_CAL_CTRL_MOD_CAL_CYCLES   (0x00000003u)

Definition at line 400 of file regs.h.

#define MOD_CAL_CTRL_MOD_CAL_CYCLES_BIT   (0)

Definition at line 402 of file regs.h.

#define MOD_CAL_CTRL_MOD_CAL_CYCLES_BITS   (2)

Definition at line 403 of file regs.h.

#define MOD_CAL_CTRL_MOD_CAL_CYCLES_MASK   (0x00000003u)

Definition at line 401 of file regs.h.

#define MOD_CAL_CTRL_MOD_CAL_DONE   (0x00000010u)

Definition at line 395 of file regs.h.

#define MOD_CAL_CTRL_MOD_CAL_DONE_BIT   (4)

Definition at line 397 of file regs.h.

#define MOD_CAL_CTRL_MOD_CAL_DONE_BITS   (1)

Definition at line 398 of file regs.h.

#define MOD_CAL_CTRL_MOD_CAL_DONE_MASK   (0x00000010u)

Definition at line 396 of file regs.h.

#define MOD_CAL_CTRL_MOD_CAL_GO   (0x00008000u)

Definition at line 390 of file regs.h.

#define MOD_CAL_CTRL_MOD_CAL_GO_BIT   (15)

Definition at line 392 of file regs.h.

#define MOD_CAL_CTRL_MOD_CAL_GO_BITS   (1)

Definition at line 393 of file regs.h.

#define MOD_CAL_CTRL_MOD_CAL_GO_MASK   (0x00008000u)

Definition at line 391 of file regs.h.

#define MOD_CAL_CTRL_REG   *((volatile int32u *)0x40001000u)

Definition at line 386 of file regs.h.

#define MOD_CAL_CTRL_RESET   (0x00000000u)

Definition at line 388 of file regs.h.

#define MOD_EN   *((volatile int32u *)0x40001028u)

Definition at line 515 of file regs.h.

#define MOD_EN_ADDR   (0x40001028u)

Definition at line 517 of file regs.h.

#define MOD_EN_MOD_EN   (0x00000001u)

Definition at line 520 of file regs.h.

#define MOD_EN_MOD_EN_BIT   (0)

Definition at line 522 of file regs.h.

#define MOD_EN_MOD_EN_BITS   (1)

Definition at line 523 of file regs.h.

#define MOD_EN_MOD_EN_MASK   (0x00000001u)

Definition at line 521 of file regs.h.

#define MOD_EN_REG   *((volatile int32u *)0x40001028u)

Definition at line 516 of file regs.h.

#define MOD_EN_RESET   (0x00000001u)

Definition at line 518 of file regs.h.

#define MPU_ATTR   *((volatile int32u *)0xE000EDA0u)

Definition at line 10570 of file regs.h.

#define MPU_ATTR1   *((volatile int32u *)0xE000EDA8u)

Definition at line 10640 of file regs.h.

#define MPU_ATTR1_ADDR   (0xE000EDA8u)

Definition at line 10642 of file regs.h.

#define MPU_ATTR1_AP   (0x07000000u)

Definition at line 10650 of file regs.h.

#define MPU_ATTR1_AP_BIT   (24)

Definition at line 10652 of file regs.h.

#define MPU_ATTR1_AP_BITS   (3)

Definition at line 10653 of file regs.h.

#define MPU_ATTR1_AP_MASK   (0x07000000u)

Definition at line 10651 of file regs.h.

#define MPU_ATTR1_B   (0x00010000u)

Definition at line 10670 of file regs.h.

#define MPU_ATTR1_B_BIT   (16)

Definition at line 10672 of file regs.h.

#define MPU_ATTR1_B_BITS   (1)

Definition at line 10673 of file regs.h.

#define MPU_ATTR1_B_MASK   (0x00010000u)

Definition at line 10671 of file regs.h.

#define MPU_ATTR1_C   (0x00020000u)

Definition at line 10665 of file regs.h.

#define MPU_ATTR1_C_BIT   (17)

Definition at line 10667 of file regs.h.

#define MPU_ATTR1_C_BITS   (1)

Definition at line 10668 of file regs.h.

#define MPU_ATTR1_C_MASK   (0x00020000u)

Definition at line 10666 of file regs.h.

#define MPU_ATTR1_ENABLE   (0x00000001u)

Definition at line 10685 of file regs.h.

#define MPU_ATTR1_ENABLE_BIT   (0)

Definition at line 10687 of file regs.h.

#define MPU_ATTR1_ENABLE_BITS   (1)

Definition at line 10688 of file regs.h.

#define MPU_ATTR1_ENABLE_MASK   (0x00000001u)

Definition at line 10686 of file regs.h.

#define MPU_ATTR1_REG   *((volatile int32u *)0xE000EDA8u)

Definition at line 10641 of file regs.h.

#define MPU_ATTR1_RESET   (0x00000000u)

Definition at line 10643 of file regs.h.

#define MPU_ATTR1_S   (0x00040000u)

Definition at line 10660 of file regs.h.

#define MPU_ATTR1_S_BIT   (18)

Definition at line 10662 of file regs.h.

#define MPU_ATTR1_S_BITS   (1)

Definition at line 10663 of file regs.h.

#define MPU_ATTR1_S_MASK   (0x00040000u)

Definition at line 10661 of file regs.h.

#define MPU_ATTR1_SIZE   (0x0000003Eu)

Definition at line 10680 of file regs.h.

#define MPU_ATTR1_SIZE_BIT   (1)

Definition at line 10682 of file regs.h.

#define MPU_ATTR1_SIZE_BITS   (5)

Definition at line 10683 of file regs.h.

#define MPU_ATTR1_SIZE_MASK   (0x0000003Eu)

Definition at line 10681 of file regs.h.

#define MPU_ATTR1_SRD   (0x0000FF00u)

Definition at line 10675 of file regs.h.

#define MPU_ATTR1_SRD_BIT   (8)

Definition at line 10677 of file regs.h.

#define MPU_ATTR1_SRD_BITS   (8)

Definition at line 10678 of file regs.h.

#define MPU_ATTR1_SRD_MASK   (0x0000FF00u)

Definition at line 10676 of file regs.h.

#define MPU_ATTR1_TEX   (0x00380000u)

Definition at line 10655 of file regs.h.

#define MPU_ATTR1_TEX_BIT   (19)

Definition at line 10657 of file regs.h.

#define MPU_ATTR1_TEX_BITS   (3)

Definition at line 10658 of file regs.h.

#define MPU_ATTR1_TEX_MASK   (0x00380000u)

Definition at line 10656 of file regs.h.

#define MPU_ATTR1_XN   (0x10000000u)

Definition at line 10645 of file regs.h.

#define MPU_ATTR1_XN_BIT   (28)

Definition at line 10647 of file regs.h.

#define MPU_ATTR1_XN_BITS   (1)

Definition at line 10648 of file regs.h.

#define MPU_ATTR1_XN_MASK   (0x10000000u)

Definition at line 10646 of file regs.h.

#define MPU_ATTR2   *((volatile int32u *)0xE000EDB0u)

Definition at line 10710 of file regs.h.

#define MPU_ATTR2_ADDR   (0xE000EDB0u)

Definition at line 10712 of file regs.h.

#define MPU_ATTR2_AP   (0x1F000000u)

Definition at line 10720 of file regs.h.

#define MPU_ATTR2_AP_BIT   (24)

Definition at line 10722 of file regs.h.

#define MPU_ATTR2_AP_BITS   (5)

Definition at line 10723 of file regs.h.

#define MPU_ATTR2_AP_MASK   (0x1F000000u)

Definition at line 10721 of file regs.h.

#define MPU_ATTR2_B   (0x00010000u)

Definition at line 10740 of file regs.h.

#define MPU_ATTR2_B_BIT   (16)

Definition at line 10742 of file regs.h.

#define MPU_ATTR2_B_BITS   (1)

Definition at line 10743 of file regs.h.

#define MPU_ATTR2_B_MASK   (0x00010000u)

Definition at line 10741 of file regs.h.

#define MPU_ATTR2_C   (0x00020000u)

Definition at line 10735 of file regs.h.

#define MPU_ATTR2_C_BIT   (17)

Definition at line 10737 of file regs.h.

#define MPU_ATTR2_C_BITS   (1)

Definition at line 10738 of file regs.h.

#define MPU_ATTR2_C_MASK   (0x00020000u)

Definition at line 10736 of file regs.h.

#define MPU_ATTR2_ENABLE   (0x00000003u)

Definition at line 10755 of file regs.h.

#define MPU_ATTR2_ENABLE_BIT   (0)

Definition at line 10757 of file regs.h.

#define MPU_ATTR2_ENABLE_BITS   (2)

Definition at line 10758 of file regs.h.

#define MPU_ATTR2_ENABLE_MASK   (0x00000003u)

Definition at line 10756 of file regs.h.

#define MPU_ATTR2_REG   *((volatile int32u *)0xE000EDB0u)

Definition at line 10711 of file regs.h.

#define MPU_ATTR2_RESET   (0x00000000u)

Definition at line 10713 of file regs.h.

#define MPU_ATTR2_S   (0x00040000u)

Definition at line 10730 of file regs.h.

#define MPU_ATTR2_S_BIT   (18)

Definition at line 10732 of file regs.h.

#define MPU_ATTR2_S_BITS   (1)

Definition at line 10733 of file regs.h.

#define MPU_ATTR2_S_MASK   (0x00040000u)

Definition at line 10731 of file regs.h.

#define MPU_ATTR2_SIZE   (0x0000003Eu)

Definition at line 10750 of file regs.h.

#define MPU_ATTR2_SIZE_BIT   (1)

Definition at line 10752 of file regs.h.

#define MPU_ATTR2_SIZE_BITS   (5)

Definition at line 10753 of file regs.h.

#define MPU_ATTR2_SIZE_MASK   (0x0000003Eu)

Definition at line 10751 of file regs.h.

#define MPU_ATTR2_SRD   (0x0000FF00u)

Definition at line 10745 of file regs.h.

#define MPU_ATTR2_SRD_BIT   (8)

Definition at line 10747 of file regs.h.

#define MPU_ATTR2_SRD_BITS   (8)

Definition at line 10748 of file regs.h.

#define MPU_ATTR2_SRD_MASK   (0x0000FF00u)

Definition at line 10746 of file regs.h.

#define MPU_ATTR2_TEX   (0x00380000u)

Definition at line 10725 of file regs.h.

#define MPU_ATTR2_TEX_BIT   (19)

Definition at line 10727 of file regs.h.

#define MPU_ATTR2_TEX_BITS   (3)

Definition at line 10728 of file regs.h.

#define MPU_ATTR2_TEX_MASK   (0x00380000u)

Definition at line 10726 of file regs.h.

#define MPU_ATTR2_XN   (0x10000000u)

Definition at line 10715 of file regs.h.

#define MPU_ATTR2_XN_BIT   (28)

Definition at line 10717 of file regs.h.

#define MPU_ATTR2_XN_BITS   (1)

Definition at line 10718 of file regs.h.

#define MPU_ATTR2_XN_MASK   (0x10000000u)

Definition at line 10716 of file regs.h.

#define MPU_ATTR3   *((volatile int32u *)0xE000EDBCu)

Definition at line 10780 of file regs.h.

#define MPU_ATTR3_ADDR   (0xE000EDBCu)

Definition at line 10782 of file regs.h.

#define MPU_ATTR3_AP   (0x1F000000u)

Definition at line 10790 of file regs.h.

#define MPU_ATTR3_AP_BIT   (24)

Definition at line 10792 of file regs.h.

#define MPU_ATTR3_AP_BITS   (5)

Definition at line 10793 of file regs.h.

#define MPU_ATTR3_AP_MASK   (0x1F000000u)

Definition at line 10791 of file regs.h.

#define MPU_ATTR3_B   (0x00010000u)

Definition at line 10810 of file regs.h.

#define MPU_ATTR3_B_BIT   (16)

Definition at line 10812 of file regs.h.

#define MPU_ATTR3_B_BITS   (1)

Definition at line 10813 of file regs.h.

#define MPU_ATTR3_B_MASK   (0x00010000u)

Definition at line 10811 of file regs.h.

#define MPU_ATTR3_C   (0x00020000u)

Definition at line 10805 of file regs.h.

#define MPU_ATTR3_C_BIT   (17)

Definition at line 10807 of file regs.h.

#define MPU_ATTR3_C_BITS   (1)

Definition at line 10808 of file regs.h.

#define MPU_ATTR3_C_MASK   (0x00020000u)

Definition at line 10806 of file regs.h.

#define MPU_ATTR3_ENABLE   (0x00000003u)

Definition at line 10825 of file regs.h.

#define MPU_ATTR3_ENABLE_BIT   (0)

Definition at line 10827 of file regs.h.

#define MPU_ATTR3_ENABLE_BITS   (2)

Definition at line 10828 of file regs.h.

#define MPU_ATTR3_ENABLE_MASK   (0x00000003u)

Definition at line 10826 of file regs.h.

#define MPU_ATTR3_REG   *((volatile int32u *)0xE000EDBCu)

Definition at line 10781 of file regs.h.

#define MPU_ATTR3_RESET   (0x00000000u)

Definition at line 10783 of file regs.h.

#define MPU_ATTR3_S   (0x00040000u)

Definition at line 10800 of file regs.h.

#define MPU_ATTR3_S_BIT   (18)

Definition at line 10802 of file regs.h.

#define MPU_ATTR3_S_BITS   (1)

Definition at line 10803 of file regs.h.

#define MPU_ATTR3_S_MASK   (0x00040000u)

Definition at line 10801 of file regs.h.

#define MPU_ATTR3_SIZE   (0x0000003Eu)

Definition at line 10820 of file regs.h.

#define MPU_ATTR3_SIZE_BIT   (1)

Definition at line 10822 of file regs.h.

#define MPU_ATTR3_SIZE_BITS   (5)

Definition at line 10823 of file regs.h.

#define MPU_ATTR3_SIZE_MASK   (0x0000003Eu)

Definition at line 10821 of file regs.h.

#define MPU_ATTR3_SRD   (0x0000FF00u)

Definition at line 10815 of file regs.h.

#define MPU_ATTR3_SRD_BIT   (8)

Definition at line 10817 of file regs.h.

#define MPU_ATTR3_SRD_BITS   (8)

Definition at line 10818 of file regs.h.

#define MPU_ATTR3_SRD_MASK   (0x0000FF00u)

Definition at line 10816 of file regs.h.

#define MPU_ATTR3_TEX   (0x00380000u)

Definition at line 10795 of file regs.h.

#define MPU_ATTR3_TEX_BIT   (19)

Definition at line 10797 of file regs.h.

#define MPU_ATTR3_TEX_BITS   (3)

Definition at line 10798 of file regs.h.

#define MPU_ATTR3_TEX_MASK   (0x00380000u)

Definition at line 10796 of file regs.h.

#define MPU_ATTR3_XN   (0x10000000u)

Definition at line 10785 of file regs.h.

#define MPU_ATTR3_XN_BIT   (28)

Definition at line 10787 of file regs.h.

#define MPU_ATTR3_XN_BITS   (1)

Definition at line 10788 of file regs.h.

#define MPU_ATTR3_XN_MASK   (0x10000000u)

Definition at line 10786 of file regs.h.

#define MPU_ATTR_ADDR   (0xE000EDA0u)

Definition at line 10572 of file regs.h.

#define MPU_ATTR_AP   (0x07000000u)

Definition at line 10580 of file regs.h.

#define MPU_ATTR_AP_BIT   (24)

Definition at line 10582 of file regs.h.

#define MPU_ATTR_AP_BITS   (3)

Definition at line 10583 of file regs.h.

#define MPU_ATTR_AP_MASK   (0x07000000u)

Definition at line 10581 of file regs.h.

#define MPU_ATTR_B   (0x00010000u)

Definition at line 10600 of file regs.h.

#define MPU_ATTR_B_BIT   (16)

Definition at line 10602 of file regs.h.

#define MPU_ATTR_B_BITS   (1)

Definition at line 10603 of file regs.h.

#define MPU_ATTR_B_MASK   (0x00010000u)

Definition at line 10601 of file regs.h.

#define MPU_ATTR_C   (0x00020000u)

Definition at line 10595 of file regs.h.

#define MPU_ATTR_C_BIT   (17)

Definition at line 10597 of file regs.h.

#define MPU_ATTR_C_BITS   (1)

Definition at line 10598 of file regs.h.

#define MPU_ATTR_C_MASK   (0x00020000u)

Definition at line 10596 of file regs.h.

#define MPU_ATTR_ENABLE   (0x00000001u)

Definition at line 10615 of file regs.h.

#define MPU_ATTR_ENABLE_BIT   (0)

Definition at line 10617 of file regs.h.

#define MPU_ATTR_ENABLE_BITS   (1)

Definition at line 10618 of file regs.h.

#define MPU_ATTR_ENABLE_MASK   (0x00000001u)

Definition at line 10616 of file regs.h.

#define MPU_ATTR_REG   *((volatile int32u *)0xE000EDA0u)

Definition at line 10571 of file regs.h.

#define MPU_ATTR_RESET   (0x00000000u)

Definition at line 10573 of file regs.h.

#define MPU_ATTR_S   (0x00040000u)

Definition at line 10590 of file regs.h.

#define MPU_ATTR_S_BIT   (18)

Definition at line 10592 of file regs.h.

#define MPU_ATTR_S_BITS   (1)

Definition at line 10593 of file regs.h.

#define MPU_ATTR_S_MASK   (0x00040000u)

Definition at line 10591 of file regs.h.

#define MPU_ATTR_SIZE   (0x0000003Eu)

Definition at line 10610 of file regs.h.

#define MPU_ATTR_SIZE_BIT   (1)

Definition at line 10612 of file regs.h.

#define MPU_ATTR_SIZE_BITS   (5)

Definition at line 10613 of file regs.h.

#define MPU_ATTR_SIZE_MASK   (0x0000003Eu)

Definition at line 10611 of file regs.h.

#define MPU_ATTR_SRD   (0x0000FF00u)

Definition at line 10605 of file regs.h.

#define MPU_ATTR_SRD_BIT   (8)

Definition at line 10607 of file regs.h.

#define MPU_ATTR_SRD_BITS   (8)

Definition at line 10608 of file regs.h.

#define MPU_ATTR_SRD_MASK   (0x0000FF00u)

Definition at line 10606 of file regs.h.

#define MPU_ATTR_TEX   (0x00380000u)

Definition at line 10585 of file regs.h.

#define MPU_ATTR_TEX_BIT   (19)

Definition at line 10587 of file regs.h.

#define MPU_ATTR_TEX_BITS   (3)

Definition at line 10588 of file regs.h.

#define MPU_ATTR_TEX_MASK   (0x00380000u)

Definition at line 10586 of file regs.h.

#define MPU_ATTR_XN   (0x10000000u)

Definition at line 10575 of file regs.h.

#define MPU_ATTR_XN_BIT   (28)

Definition at line 10577 of file regs.h.

#define MPU_ATTR_XN_BITS   (1)

Definition at line 10578 of file regs.h.

#define MPU_ATTR_XN_MASK   (0x10000000u)

Definition at line 10576 of file regs.h.

#define MPU_BASE   *((volatile int32u *)0xE000ED9Cu)

Definition at line 10550 of file regs.h.

#define MPU_BASE1   *((volatile int32u *)0xE000EDA4u)

Definition at line 10620 of file regs.h.

#define MPU_BASE1_ADDR   (0xE000EDA4u)

Definition at line 10622 of file regs.h.

#define MPU_BASE1_ADDRESS   (0xFFFFFFE0u)

Definition at line 10625 of file regs.h.

#define MPU_BASE1_ADDRESS_BIT   (5)

Definition at line 10627 of file regs.h.

#define MPU_BASE1_ADDRESS_BITS   (27)

Definition at line 10628 of file regs.h.

#define MPU_BASE1_ADDRESS_MASK   (0xFFFFFFE0u)

Definition at line 10626 of file regs.h.

#define MPU_BASE1_REG   *((volatile int32u *)0xE000EDA4u)

Definition at line 10621 of file regs.h.

#define MPU_BASE1_REGION   (0x0000000Fu)

Definition at line 10635 of file regs.h.

#define MPU_BASE1_REGION_BIT   (0)

Definition at line 10637 of file regs.h.

#define MPU_BASE1_REGION_BITS   (4)

Definition at line 10638 of file regs.h.

#define MPU_BASE1_REGION_MASK   (0x0000000Fu)

Definition at line 10636 of file regs.h.

#define MPU_BASE1_RESET   (0x00000000u)

Definition at line 10623 of file regs.h.

#define MPU_BASE1_VALID   (0x00000010u)

Definition at line 10630 of file regs.h.

#define MPU_BASE1_VALID_BIT   (4)

Definition at line 10632 of file regs.h.

#define MPU_BASE1_VALID_BITS   (1)

Definition at line 10633 of file regs.h.

#define MPU_BASE1_VALID_MASK   (0x00000010u)

Definition at line 10631 of file regs.h.

#define MPU_BASE2   *((volatile int32u *)0xE000EDACu)

Definition at line 10690 of file regs.h.

#define MPU_BASE2_ADDR   (0xE000EDACu)

Definition at line 10692 of file regs.h.

#define MPU_BASE2_ADDRESS   (0xFFFFFFE0u)

Definition at line 10695 of file regs.h.

#define MPU_BASE2_ADDRESS_BIT   (5)

Definition at line 10697 of file regs.h.

#define MPU_BASE2_ADDRESS_BITS   (27)

Definition at line 10698 of file regs.h.

#define MPU_BASE2_ADDRESS_MASK   (0xFFFFFFE0u)

Definition at line 10696 of file regs.h.

#define MPU_BASE2_REG   *((volatile int32u *)0xE000EDACu)

Definition at line 10691 of file regs.h.

#define MPU_BASE2_REGION   (0x0000000Fu)

Definition at line 10705 of file regs.h.

#define MPU_BASE2_REGION_BIT   (0)

Definition at line 10707 of file regs.h.

#define MPU_BASE2_REGION_BITS   (4)

Definition at line 10708 of file regs.h.

#define MPU_BASE2_REGION_MASK   (0x0000000Fu)

Definition at line 10706 of file regs.h.

#define MPU_BASE2_RESET   (0x00000000u)

Definition at line 10693 of file regs.h.

#define MPU_BASE2_VALID   (0x00000010u)

Definition at line 10700 of file regs.h.

#define MPU_BASE2_VALID_BIT   (4)

Definition at line 10702 of file regs.h.

#define MPU_BASE2_VALID_BITS   (1)

Definition at line 10703 of file regs.h.

#define MPU_BASE2_VALID_MASK   (0x00000010u)

Definition at line 10701 of file regs.h.

#define MPU_BASE3   *((volatile int32u *)0xE000EDB4u)

Definition at line 10760 of file regs.h.

#define MPU_BASE3_ADDR   (0xE000EDB4u)

Definition at line 10762 of file regs.h.

#define MPU_BASE3_ADDRESS   (0xFFFFFFE0u)

Definition at line 10765 of file regs.h.

#define MPU_BASE3_ADDRESS_BIT   (5)

Definition at line 10767 of file regs.h.

#define MPU_BASE3_ADDRESS_BITS   (27)

Definition at line 10768 of file regs.h.

#define MPU_BASE3_ADDRESS_MASK   (0xFFFFFFE0u)

Definition at line 10766 of file regs.h.

#define MPU_BASE3_REG   *((volatile int32u *)0xE000EDB4u)

Definition at line 10761 of file regs.h.

#define MPU_BASE3_REGION   (0x0000000Fu)

Definition at line 10775 of file regs.h.

#define MPU_BASE3_REGION_BIT   (0)

Definition at line 10777 of file regs.h.

#define MPU_BASE3_REGION_BITS   (4)

Definition at line 10778 of file regs.h.

#define MPU_BASE3_REGION_MASK   (0x0000000Fu)

Definition at line 10776 of file regs.h.

#define MPU_BASE3_RESET   (0x00000000u)

Definition at line 10763 of file regs.h.

#define MPU_BASE3_VALID   (0x00000010u)

Definition at line 10770 of file regs.h.

#define MPU_BASE3_VALID_BIT   (4)

Definition at line 10772 of file regs.h.

#define MPU_BASE3_VALID_BITS   (1)

Definition at line 10773 of file regs.h.

#define MPU_BASE3_VALID_MASK   (0x00000010u)

Definition at line 10771 of file regs.h.

#define MPU_BASE_ADDR   (0xE000ED9Cu)

Definition at line 10552 of file regs.h.

#define MPU_BASE_ADDRESS   (0xFFFFFFE0u)

Definition at line 10555 of file regs.h.

#define MPU_BASE_ADDRESS_BIT   (5)

Definition at line 10557 of file regs.h.

#define MPU_BASE_ADDRESS_BITS   (27)

Definition at line 10558 of file regs.h.

#define MPU_BASE_ADDRESS_MASK   (0xFFFFFFE0u)

Definition at line 10556 of file regs.h.

#define MPU_BASE_REG   *((volatile int32u *)0xE000ED9Cu)

Definition at line 10551 of file regs.h.

#define MPU_BASE_REGION   (0x0000000Fu)

Definition at line 10565 of file regs.h.

#define MPU_BASE_REGION_BIT   (0)

Definition at line 10567 of file regs.h.

#define MPU_BASE_REGION_BITS   (4)

Definition at line 10568 of file regs.h.

#define MPU_BASE_REGION_MASK   (0x0000000Fu)

Definition at line 10566 of file regs.h.

#define MPU_BASE_RESET   (0x00000000u)

Definition at line 10553 of file regs.h.

#define MPU_BASE_VALID   (0x00000010u)

Definition at line 10560 of file regs.h.

#define MPU_BASE_VALID_BIT   (4)

Definition at line 10562 of file regs.h.

#define MPU_BASE_VALID_BITS   (1)

Definition at line 10563 of file regs.h.

#define MPU_BASE_VALID_MASK   (0x00000010u)

Definition at line 10561 of file regs.h.

#define MPU_CTRL   *((volatile int32u *)0xE000ED94u)

Definition at line 10520 of file regs.h.

#define MPU_CTRL_ADDR   (0xE000ED94u)

Definition at line 10522 of file regs.h.

#define MPU_CTRL_ENABLE   (0x00000001u)

Definition at line 10535 of file regs.h.

#define MPU_CTRL_ENABLE_BIT   (0)

Definition at line 10537 of file regs.h.

#define MPU_CTRL_ENABLE_BITS   (1)

Definition at line 10538 of file regs.h.

#define MPU_CTRL_ENABLE_MASK   (0x00000001u)

Definition at line 10536 of file regs.h.

#define MPU_CTRL_HFNMIENA   (0x00000002u)

Definition at line 10530 of file regs.h.

#define MPU_CTRL_HFNMIENA_BIT   (1)

Definition at line 10532 of file regs.h.

#define MPU_CTRL_HFNMIENA_BITS   (1)

Definition at line 10533 of file regs.h.

#define MPU_CTRL_HFNMIENA_MASK   (0x00000002u)

Definition at line 10531 of file regs.h.

#define MPU_CTRL_PRIVDEFENA   (0x00000004u)

Definition at line 10525 of file regs.h.

#define MPU_CTRL_PRIVDEFENA_BIT   (2)

Definition at line 10527 of file regs.h.

#define MPU_CTRL_PRIVDEFENA_BITS   (1)

Definition at line 10528 of file regs.h.

#define MPU_CTRL_PRIVDEFENA_MASK   (0x00000004u)

Definition at line 10526 of file regs.h.

#define MPU_CTRL_REG   *((volatile int32u *)0xE000ED94u)

Definition at line 10521 of file regs.h.

#define MPU_CTRL_RESET   (0x00000000u)

Definition at line 10523 of file regs.h.

#define MPU_REGION   *((volatile int32u *)0xE000ED98u)

Definition at line 10540 of file regs.h.

#define MPU_REGION_ADDR   (0xE000ED98u)

Definition at line 10542 of file regs.h.

#define MPU_REGION_REG   *((volatile int32u *)0xE000ED98u)

Definition at line 10541 of file regs.h.

#define MPU_REGION_REGION   (0x000000FFu)

Definition at line 10545 of file regs.h.

#define MPU_REGION_REGION_BIT   (0)

Definition at line 10547 of file regs.h.

#define MPU_REGION_REGION_BITS   (8)

Definition at line 10548 of file regs.h.

#define MPU_REGION_REGION_MASK   (0x000000FFu)

Definition at line 10546 of file regs.h.

#define MPU_REGION_RESET   (0x00000000u)

Definition at line 10543 of file regs.h.

#define MPU_TYPE   *((volatile int32u *)0xE000ED90u)

Definition at line 10505 of file regs.h.

#define MPU_TYPE_ADDR   (0xE000ED90u)

Definition at line 10507 of file regs.h.

#define MPU_TYPE_DREGION   (0x0000FF00u)

Definition at line 10515 of file regs.h.

#define MPU_TYPE_DREGION_BIT   (8)

Definition at line 10517 of file regs.h.

#define MPU_TYPE_DREGION_BITS   (8)

Definition at line 10518 of file regs.h.

#define MPU_TYPE_DREGION_MASK   (0x0000FF00u)

Definition at line 10516 of file regs.h.

#define MPU_TYPE_IREGION   (0x00FF0000u)

Definition at line 10510 of file regs.h.

#define MPU_TYPE_IREGION_BIT   (16)

Definition at line 10512 of file regs.h.

#define MPU_TYPE_IREGION_BITS   (8)

Definition at line 10513 of file regs.h.

#define MPU_TYPE_IREGION_MASK   (0x00FF0000u)

Definition at line 10511 of file regs.h.

#define MPU_TYPE_REG   *((volatile int32u *)0xE000ED90u)

Definition at line 10506 of file regs.h.

#define MPU_TYPE_RESET   (0x00000800u)

Definition at line 10508 of file regs.h.

#define NOISE_EN   *((volatile int32u *)0x40001114u)

Definition at line 1440 of file regs.h.

#define NOISE_EN_ADDR   (0x40001114u)

Definition at line 1442 of file regs.h.

#define NOISE_EN_NOISE_EN   (0x00000001u)

Definition at line 1445 of file regs.h.

#define NOISE_EN_NOISE_EN_BIT   (0)

Definition at line 1447 of file regs.h.

#define NOISE_EN_NOISE_EN_BITS   (1)

Definition at line 1448 of file regs.h.

#define NOISE_EN_NOISE_EN_MASK   (0x00000001u)

Definition at line 1446 of file regs.h.

#define NOISE_EN_REG   *((volatile int32u *)0x40001114u)

Definition at line 1441 of file regs.h.

#define NOISE_EN_RESET   (0x00000000u)

Definition at line 1443 of file regs.h.

#define NONPAN_COUNT   *((volatile int32u *)0x400020C8u)

Definition at line 2265 of file regs.h.

#define NONPAN_COUNT_ADDR   (0x400020C8u)

Definition at line 2267 of file regs.h.

#define NONPAN_COUNT_NONPAN_COUNT   (0x0000FFFFu)

Definition at line 2270 of file regs.h.

#define NONPAN_COUNT_NONPAN_COUNT_BIT   (0)

Definition at line 2272 of file regs.h.

#define NONPAN_COUNT_NONPAN_COUNT_BITS   (16)

Definition at line 2273 of file regs.h.

#define NONPAN_COUNT_NONPAN_COUNT_MASK   (0x0000FFFFu)

Definition at line 2271 of file regs.h.

#define NONPAN_COUNT_REG   *((volatile int32u *)0x400020C8u)

Definition at line 2266 of file regs.h.

#define NONPAN_COUNT_RESET   (0x00000000u)

Definition at line 2268 of file regs.h.

#define NVIC_ICTR   *((volatile int32u *)0xE000E004u)

Definition at line 9195 of file regs.h.

#define NVIC_ICTR_ADDR   (0xE000E004u)

Definition at line 9197 of file regs.h.

#define NVIC_ICTR_INTLINESNUM   (0x0000001Fu)

Definition at line 9200 of file regs.h.

#define NVIC_ICTR_INTLINESNUM_BIT   (0)

Definition at line 9202 of file regs.h.

#define NVIC_ICTR_INTLINESNUM_BITS   (5)

Definition at line 9203 of file regs.h.

#define NVIC_ICTR_INTLINESNUM_MASK   (0x0000001Fu)

Definition at line 9201 of file regs.h.

#define NVIC_ICTR_REG   *((volatile int32u *)0xE000E004u)

Definition at line 9196 of file regs.h.

#define NVIC_ICTR_RESET   (0x00000000u)

Definition at line 9198 of file regs.h.

#define NVIC_IPR_11to8   *((volatile int32u *)0xE000E408u)

Definition at line 9770 of file regs.h.

#define NVIC_IPR_11to8_ADDR   (0xE000E408u)

Definition at line 9772 of file regs.h.

#define NVIC_IPR_11to8_PRI_10   (0x00FF0000u)

Definition at line 9780 of file regs.h.

#define NVIC_IPR_11to8_PRI_10_BIT   (16)

Definition at line 9782 of file regs.h.

#define NVIC_IPR_11to8_PRI_10_BITS   (8)

Definition at line 9783 of file regs.h.

#define NVIC_IPR_11to8_PRI_10_MASK   (0x00FF0000u)

Definition at line 9781 of file regs.h.

#define NVIC_IPR_11to8_PRI_11   (0xFF000000u)

Definition at line 9775 of file regs.h.

#define NVIC_IPR_11to8_PRI_11_BIT   (24)

Definition at line 9777 of file regs.h.

#define NVIC_IPR_11to8_PRI_11_BITS   (8)

Definition at line 9778 of file regs.h.

#define NVIC_IPR_11to8_PRI_11_MASK   (0xFF000000u)

Definition at line 9776 of file regs.h.

#define NVIC_IPR_11to8_PRI_8   (0x000000FFu)

Definition at line 9790 of file regs.h.

#define NVIC_IPR_11to8_PRI_8_BIT   (0)

Definition at line 9792 of file regs.h.

#define NVIC_IPR_11to8_PRI_8_BITS   (8)

Definition at line 9793 of file regs.h.

#define NVIC_IPR_11to8_PRI_8_MASK   (0x000000FFu)

Definition at line 9791 of file regs.h.

#define NVIC_IPR_11to8_PRI_9   (0x0000FF00u)

Definition at line 9785 of file regs.h.

#define NVIC_IPR_11to8_PRI_9_BIT   (8)

Definition at line 9787 of file regs.h.

#define NVIC_IPR_11to8_PRI_9_BITS   (8)

Definition at line 9788 of file regs.h.

#define NVIC_IPR_11to8_PRI_9_MASK   (0x0000FF00u)

Definition at line 9786 of file regs.h.

#define NVIC_IPR_11to8_REG   *((volatile int32u *)0xE000E408u)

Definition at line 9771 of file regs.h.

#define NVIC_IPR_11to8_RESET   (0x00000000u)

Definition at line 9773 of file regs.h.

#define NVIC_IPR_15to12   *((volatile int32u *)0xE000E40Cu)

Definition at line 9795 of file regs.h.

#define NVIC_IPR_15to12_ADDR   (0xE000E40Cu)

Definition at line 9797 of file regs.h.

#define NVIC_IPR_15to12_PRI_12   (0x000000FFu)

Definition at line 9815 of file regs.h.

#define NVIC_IPR_15to12_PRI_12_BIT   (0)

Definition at line 9817 of file regs.h.

#define NVIC_IPR_15to12_PRI_12_BITS   (8)

Definition at line 9818 of file regs.h.

#define NVIC_IPR_15to12_PRI_12_MASK   (0x000000FFu)

Definition at line 9816 of file regs.h.

#define NVIC_IPR_15to12_PRI_13   (0x0000FF00u)

Definition at line 9810 of file regs.h.

#define NVIC_IPR_15to12_PRI_13_BIT   (8)

Definition at line 9812 of file regs.h.

#define NVIC_IPR_15to12_PRI_13_BITS   (8)

Definition at line 9813 of file regs.h.

#define NVIC_IPR_15to12_PRI_13_MASK   (0x0000FF00u)

Definition at line 9811 of file regs.h.

#define NVIC_IPR_15to12_PRI_14   (0x00FF0000u)

Definition at line 9805 of file regs.h.

#define NVIC_IPR_15to12_PRI_14_BIT   (16)

Definition at line 9807 of file regs.h.

#define NVIC_IPR_15to12_PRI_14_BITS   (8)

Definition at line 9808 of file regs.h.

#define NVIC_IPR_15to12_PRI_14_MASK   (0x00FF0000u)

Definition at line 9806 of file regs.h.

#define NVIC_IPR_15to12_PRI_15   (0xFF000000u)

Definition at line 9800 of file regs.h.

#define NVIC_IPR_15to12_PRI_15_BIT   (24)

Definition at line 9802 of file regs.h.

#define NVIC_IPR_15to12_PRI_15_BITS   (8)

Definition at line 9803 of file regs.h.

#define NVIC_IPR_15to12_PRI_15_MASK   (0xFF000000u)

Definition at line 9801 of file regs.h.

#define NVIC_IPR_15to12_REG   *((volatile int32u *)0xE000E40Cu)

Definition at line 9796 of file regs.h.

#define NVIC_IPR_15to12_RESET   (0x00000000u)

Definition at line 9798 of file regs.h.

#define NVIC_IPR_19to16   *((volatile int32u *)0xE000E410u)

Definition at line 9820 of file regs.h.

#define NVIC_IPR_19to16_ADDR   (0xE000E410u)

Definition at line 9822 of file regs.h.

#define NVIC_IPR_19to16_PRI_16   (0x000000FFu)

Definition at line 9840 of file regs.h.

#define NVIC_IPR_19to16_PRI_16_BIT   (0)

Definition at line 9842 of file regs.h.

#define NVIC_IPR_19to16_PRI_16_BITS   (8)

Definition at line 9843 of file regs.h.

#define NVIC_IPR_19to16_PRI_16_MASK   (0x000000FFu)

Definition at line 9841 of file regs.h.

#define NVIC_IPR_19to16_PRI_17   (0x0000FF00u)

Definition at line 9835 of file regs.h.

#define NVIC_IPR_19to16_PRI_17_BIT   (8)

Definition at line 9837 of file regs.h.

#define NVIC_IPR_19to16_PRI_17_BITS   (8)

Definition at line 9838 of file regs.h.

#define NVIC_IPR_19to16_PRI_17_MASK   (0x0000FF00u)

Definition at line 9836 of file regs.h.

#define NVIC_IPR_19to16_PRI_18   (0x00FF0000u)

Definition at line 9830 of file regs.h.

#define NVIC_IPR_19to16_PRI_18_BIT   (16)

Definition at line 9832 of file regs.h.

#define NVIC_IPR_19to16_PRI_18_BITS   (8)

Definition at line 9833 of file regs.h.

#define NVIC_IPR_19to16_PRI_18_MASK   (0x00FF0000u)

Definition at line 9831 of file regs.h.

#define NVIC_IPR_19to16_PRI_19   (0xFF000000u)

Definition at line 9825 of file regs.h.

#define NVIC_IPR_19to16_PRI_19_BIT   (24)

Definition at line 9827 of file regs.h.

#define NVIC_IPR_19to16_PRI_19_BITS   (8)

Definition at line 9828 of file regs.h.

#define NVIC_IPR_19to16_PRI_19_MASK   (0xFF000000u)

Definition at line 9826 of file regs.h.

#define NVIC_IPR_19to16_REG   *((volatile int32u *)0xE000E410u)

Definition at line 9821 of file regs.h.

#define NVIC_IPR_19to16_RESET   (0x00000000u)

Definition at line 9823 of file regs.h.

#define NVIC_IPR_3to0   *((volatile int32u *)0xE000E400u)

Definition at line 9720 of file regs.h.

#define NVIC_IPR_3to0_ADDR   (0xE000E400u)

Definition at line 9722 of file regs.h.

#define NVIC_IPR_3to0_PRI_0   (0x000000FFu)

Definition at line 9740 of file regs.h.

#define NVIC_IPR_3to0_PRI_0_BIT   (0)

Definition at line 9742 of file regs.h.

#define NVIC_IPR_3to0_PRI_0_BITS   (8)

Definition at line 9743 of file regs.h.

#define NVIC_IPR_3to0_PRI_0_MASK   (0x000000FFu)

Definition at line 9741 of file regs.h.

#define NVIC_IPR_3to0_PRI_1   (0x0000FF00u)

Definition at line 9735 of file regs.h.

#define NVIC_IPR_3to0_PRI_1_BIT   (8)

Definition at line 9737 of file regs.h.

#define NVIC_IPR_3to0_PRI_1_BITS   (8)

Definition at line 9738 of file regs.h.

#define NVIC_IPR_3to0_PRI_1_MASK   (0x0000FF00u)

Definition at line 9736 of file regs.h.

#define NVIC_IPR_3to0_PRI_2   (0x00FF0000u)

Definition at line 9730 of file regs.h.

#define NVIC_IPR_3to0_PRI_2_BIT   (16)

Definition at line 9732 of file regs.h.

#define NVIC_IPR_3to0_PRI_2_BITS   (8)

Definition at line 9733 of file regs.h.

#define NVIC_IPR_3to0_PRI_2_MASK   (0x00FF0000u)

Definition at line 9731 of file regs.h.

#define NVIC_IPR_3to0_PRI_3   (0xFF000000u)

Definition at line 9725 of file regs.h.

#define NVIC_IPR_3to0_PRI_3_BIT   (24)

Definition at line 9727 of file regs.h.

#define NVIC_IPR_3to0_PRI_3_BITS   (8)

Definition at line 9728 of file regs.h.

#define NVIC_IPR_3to0_PRI_3_MASK   (0xFF000000u)

Definition at line 9726 of file regs.h.

#define NVIC_IPR_3to0_REG   *((volatile int32u *)0xE000E400u)

Definition at line 9721 of file regs.h.

#define NVIC_IPR_3to0_RESET   (0x00000000u)

Definition at line 9723 of file regs.h.

#define NVIC_IPR_7to4   *((volatile int32u *)0xE000E404u)

Definition at line 9745 of file regs.h.

#define NVIC_IPR_7to4_ADDR   (0xE000E404u)

Definition at line 9747 of file regs.h.

#define NVIC_IPR_7to4_PRI_4   (0x000000FFu)

Definition at line 9765 of file regs.h.

#define NVIC_IPR_7to4_PRI_4_BIT   (0)

Definition at line 9767 of file regs.h.

#define NVIC_IPR_7to4_PRI_4_BITS   (8)

Definition at line 9768 of file regs.h.

#define NVIC_IPR_7to4_PRI_4_MASK   (0x000000FFu)

Definition at line 9766 of file regs.h.

#define NVIC_IPR_7to4_PRI_5   (0x0000FF00u)

Definition at line 9760 of file regs.h.

#define NVIC_IPR_7to4_PRI_5_BIT   (8)

Definition at line 9762 of file regs.h.

#define NVIC_IPR_7to4_PRI_5_BITS   (8)

Definition at line 9763 of file regs.h.

#define NVIC_IPR_7to4_PRI_5_MASK   (0x0000FF00u)

Definition at line 9761 of file regs.h.

#define NVIC_IPR_7to4_PRI_6   (0x00FF0000u)

Definition at line 9755 of file regs.h.

#define NVIC_IPR_7to4_PRI_6_BIT   (16)

Definition at line 9757 of file regs.h.

#define NVIC_IPR_7to4_PRI_6_BITS   (8)

Definition at line 9758 of file regs.h.

#define NVIC_IPR_7to4_PRI_6_MASK   (0x00FF0000u)

Definition at line 9756 of file regs.h.

#define NVIC_IPR_7to4_PRI_7   (0xFF000000u)

Definition at line 9750 of file regs.h.

#define NVIC_IPR_7to4_PRI_7_BIT   (24)

Definition at line 9752 of file regs.h.

#define NVIC_IPR_7to4_PRI_7_BITS   (8)

Definition at line 9753 of file regs.h.

#define NVIC_IPR_7to4_PRI_7_MASK   (0xFF000000u)

Definition at line 9751 of file regs.h.

#define NVIC_IPR_7to4_REG   *((volatile int32u *)0xE000E404u)

Definition at line 9746 of file regs.h.

#define NVIC_IPR_7to4_RESET   (0x00000000u)

Definition at line 9748 of file regs.h.

#define NVIC_MCR   *((volatile int32u *)0xE000E000u)

Definition at line 9190 of file regs.h.

#define NVIC_MCR_ADDR   (0xE000E000u)

Definition at line 9192 of file regs.h.

#define NVIC_MCR_REG   *((volatile int32u *)0xE000E000u)

Definition at line 9191 of file regs.h.

#define NVIC_MCR_RESET   (0x00000000u)

Definition at line 9193 of file regs.h.

#define NVIC_PCELLID0   *((volatile int32u *)0xE000EFF0u)

Definition at line 11080 of file regs.h.

#define NVIC_PCELLID0_ADDR   (0xE000EFF0u)

Definition at line 11082 of file regs.h.

#define NVIC_PCELLID0_PCELLID   (0xFFFFFFFFu)

Definition at line 11085 of file regs.h.

#define NVIC_PCELLID0_PCELLID_BIT   (0)

Definition at line 11087 of file regs.h.

#define NVIC_PCELLID0_PCELLID_BITS   (32)

Definition at line 11088 of file regs.h.

#define NVIC_PCELLID0_PCELLID_MASK   (0xFFFFFFFFu)

Definition at line 11086 of file regs.h.

#define NVIC_PCELLID0_REG   *((volatile int32u *)0xE000EFF0u)

Definition at line 11081 of file regs.h.

#define NVIC_PCELLID0_RESET   (0x0000000Du)

Definition at line 11083 of file regs.h.

#define NVIC_PCELLID1   *((volatile int32u *)0xE000EFF4u)

Definition at line 11090 of file regs.h.

#define NVIC_PCELLID1_ADDR   (0xE000EFF4u)

Definition at line 11092 of file regs.h.

#define NVIC_PCELLID1_PCELLID   (0xFFFFFFFFu)

Definition at line 11095 of file regs.h.

#define NVIC_PCELLID1_PCELLID_BIT   (0)

Definition at line 11097 of file regs.h.

#define NVIC_PCELLID1_PCELLID_BITS   (32)

Definition at line 11098 of file regs.h.

#define NVIC_PCELLID1_PCELLID_MASK   (0xFFFFFFFFu)

Definition at line 11096 of file regs.h.

#define NVIC_PCELLID1_REG   *((volatile int32u *)0xE000EFF4u)

Definition at line 11091 of file regs.h.

#define NVIC_PCELLID1_RESET   (0x000000E0u)

Definition at line 11093 of file regs.h.

#define NVIC_PCELLID2   *((volatile int32u *)0xE000EFF8u)

Definition at line 11100 of file regs.h.

#define NVIC_PCELLID2_ADDR   (0xE000EFF8u)

Definition at line 11102 of file regs.h.

#define NVIC_PCELLID2_PCELLID   (0xFFFFFFFFu)

Definition at line 11105 of file regs.h.

#define NVIC_PCELLID2_PCELLID_BIT   (0)

Definition at line 11107 of file regs.h.

#define NVIC_PCELLID2_PCELLID_BITS   (32)

Definition at line 11108 of file regs.h.

#define NVIC_PCELLID2_PCELLID_MASK   (0xFFFFFFFFu)

Definition at line 11106 of file regs.h.

#define NVIC_PCELLID2_REG   *((volatile int32u *)0xE000EFF8u)

Definition at line 11101 of file regs.h.

#define NVIC_PCELLID2_RESET   (0x00000005u)

Definition at line 11103 of file regs.h.

#define NVIC_PCELLID3   *((volatile int32u *)0xE000EFFCu)

Definition at line 11110 of file regs.h.

#define NVIC_PCELLID3_ADDR   (0xE000EFFCu)

Definition at line 11112 of file regs.h.

#define NVIC_PCELLID3_PCELLID   (0xFFFFFFFFu)

Definition at line 11115 of file regs.h.

#define NVIC_PCELLID3_PCELLID_BIT   (0)

Definition at line 11117 of file regs.h.

#define NVIC_PCELLID3_PCELLID_BITS   (32)

Definition at line 11118 of file regs.h.

#define NVIC_PCELLID3_PCELLID_MASK   (0xFFFFFFFFu)

Definition at line 11116 of file regs.h.

#define NVIC_PCELLID3_REG   *((volatile int32u *)0xE000EFFCu)

Definition at line 11111 of file regs.h.

#define NVIC_PCELLID3_RESET   (0x000000B1u)

Definition at line 11113 of file regs.h.

#define NVIC_PERIPHID0   *((volatile int32u *)0xE000EFE0u)

Definition at line 11040 of file regs.h.

#define NVIC_PERIPHID0_ADDR   (0xE000EFE0u)

Definition at line 11042 of file regs.h.

#define NVIC_PERIPHID0_PERIPHID   (0xFFFFFFFFu)

Definition at line 11045 of file regs.h.

#define NVIC_PERIPHID0_PERIPHID_BIT   (0)

Definition at line 11047 of file regs.h.

#define NVIC_PERIPHID0_PERIPHID_BITS   (32)

Definition at line 11048 of file regs.h.

#define NVIC_PERIPHID0_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 11046 of file regs.h.

#define NVIC_PERIPHID0_REG   *((volatile int32u *)0xE000EFE0u)

Definition at line 11041 of file regs.h.

#define NVIC_PERIPHID0_RESET   (0x00000000u)

Definition at line 11043 of file regs.h.

#define NVIC_PERIPHID1   *((volatile int32u *)0xE000EFE4u)

Definition at line 11050 of file regs.h.

#define NVIC_PERIPHID1_ADDR   (0xE000EFE4u)

Definition at line 11052 of file regs.h.

#define NVIC_PERIPHID1_PERIPHID   (0xFFFFFFFFu)

Definition at line 11055 of file regs.h.

#define NVIC_PERIPHID1_PERIPHID_BIT   (0)

Definition at line 11057 of file regs.h.

#define NVIC_PERIPHID1_PERIPHID_BITS   (32)

Definition at line 11058 of file regs.h.

#define NVIC_PERIPHID1_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 11056 of file regs.h.

#define NVIC_PERIPHID1_REG   *((volatile int32u *)0xE000EFE4u)

Definition at line 11051 of file regs.h.

#define NVIC_PERIPHID1_RESET   (0x000000B0u)

Definition at line 11053 of file regs.h.

#define NVIC_PERIPHID2   *((volatile int32u *)0xE000EFE8u)

Definition at line 11060 of file regs.h.

#define NVIC_PERIPHID2_ADDR   (0xE000EFE8u)

Definition at line 11062 of file regs.h.

#define NVIC_PERIPHID2_PERIPHID   (0xFFFFFFFFu)

Definition at line 11065 of file regs.h.

#define NVIC_PERIPHID2_PERIPHID_BIT   (0)

Definition at line 11067 of file regs.h.

#define NVIC_PERIPHID2_PERIPHID_BITS   (32)

Definition at line 11068 of file regs.h.

#define NVIC_PERIPHID2_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 11066 of file regs.h.

#define NVIC_PERIPHID2_REG   *((volatile int32u *)0xE000EFE8u)

Definition at line 11061 of file regs.h.

#define NVIC_PERIPHID2_RESET   (0x0000001Bu)

Definition at line 11063 of file regs.h.

#define NVIC_PERIPHID3   *((volatile int32u *)0xE000EFECu)

Definition at line 11070 of file regs.h.

#define NVIC_PERIPHID3_ADDR   (0xE000EFECu)

Definition at line 11072 of file regs.h.

#define NVIC_PERIPHID3_PERIPHID   (0xFFFFFFFFu)

Definition at line 11075 of file regs.h.

#define NVIC_PERIPHID3_PERIPHID_BIT   (0)

Definition at line 11077 of file regs.h.

#define NVIC_PERIPHID3_PERIPHID_BITS   (32)

Definition at line 11078 of file regs.h.

#define NVIC_PERIPHID3_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 11076 of file regs.h.

#define NVIC_PERIPHID3_REG   *((volatile int32u *)0xE000EFECu)

Definition at line 11071 of file regs.h.

#define NVIC_PERIPHID3_RESET   (0x00000000u)

Definition at line 11073 of file regs.h.

#define NVIC_PERIPHID4   *((volatile int32u *)0xE000EFD0u)

Definition at line 11000 of file regs.h.

#define NVIC_PERIPHID4_ADDR   (0xE000EFD0u)

Definition at line 11002 of file regs.h.

#define NVIC_PERIPHID4_PERIPHID   (0xFFFFFFFFu)

Definition at line 11005 of file regs.h.

#define NVIC_PERIPHID4_PERIPHID_BIT   (0)

Definition at line 11007 of file regs.h.

#define NVIC_PERIPHID4_PERIPHID_BITS   (32)

Definition at line 11008 of file regs.h.

#define NVIC_PERIPHID4_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 11006 of file regs.h.

#define NVIC_PERIPHID4_REG   *((volatile int32u *)0xE000EFD0u)

Definition at line 11001 of file regs.h.

#define NVIC_PERIPHID4_RESET   (0x00000004u)

Definition at line 11003 of file regs.h.

#define NVIC_PERIPHID5   *((volatile int32u *)0xE000EFD4u)

Definition at line 11010 of file regs.h.

#define NVIC_PERIPHID5_ADDR   (0xE000EFD4u)

Definition at line 11012 of file regs.h.

#define NVIC_PERIPHID5_PERIPHID   (0xFFFFFFFFu)

Definition at line 11015 of file regs.h.

#define NVIC_PERIPHID5_PERIPHID_BIT   (0)

Definition at line 11017 of file regs.h.

#define NVIC_PERIPHID5_PERIPHID_BITS   (32)

Definition at line 11018 of file regs.h.

#define NVIC_PERIPHID5_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 11016 of file regs.h.

#define NVIC_PERIPHID5_REG   *((volatile int32u *)0xE000EFD4u)

Definition at line 11011 of file regs.h.

#define NVIC_PERIPHID5_RESET   (0x00000000u)

Definition at line 11013 of file regs.h.

#define NVIC_PERIPHID6   *((volatile int32u *)0xE000EFD8u)

Definition at line 11020 of file regs.h.

#define NVIC_PERIPHID6_ADDR   (0xE000EFD8u)

Definition at line 11022 of file regs.h.

#define NVIC_PERIPHID6_PERIPHID   (0xFFFFFFFFu)

Definition at line 11025 of file regs.h.

#define NVIC_PERIPHID6_PERIPHID_BIT   (0)

Definition at line 11027 of file regs.h.

#define NVIC_PERIPHID6_PERIPHID_BITS   (32)

Definition at line 11028 of file regs.h.

#define NVIC_PERIPHID6_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 11026 of file regs.h.

#define NVIC_PERIPHID6_REG   *((volatile int32u *)0xE000EFD8u)

Definition at line 11021 of file regs.h.

#define NVIC_PERIPHID6_RESET   (0x00000000u)

Definition at line 11023 of file regs.h.

#define NVIC_PERIPHID7   *((volatile int32u *)0xE000EFDCu)

Definition at line 11030 of file regs.h.

#define NVIC_PERIPHID7_ADDR   (0xE000EFDCu)

Definition at line 11032 of file regs.h.

#define NVIC_PERIPHID7_PERIPHID   (0xFFFFFFFFu)

Definition at line 11035 of file regs.h.

#define NVIC_PERIPHID7_PERIPHID_BIT   (0)

Definition at line 11037 of file regs.h.

#define NVIC_PERIPHID7_PERIPHID_BITS   (32)

Definition at line 11038 of file regs.h.

#define NVIC_PERIPHID7_PERIPHID_MASK   (0xFFFFFFFFu)

Definition at line 11036 of file regs.h.

#define NVIC_PERIPHID7_REG   *((volatile int32u *)0xE000EFDCu)

Definition at line 11031 of file regs.h.

#define NVIC_PERIPHID7_RESET   (0x00000000u)

Definition at line 11033 of file regs.h.

#define NVIC_STIR   *((volatile int32u *)0xE000EF00u)

Definition at line 10990 of file regs.h.

#define NVIC_STIR_ADDR   (0xE000EF00u)

Definition at line 10992 of file regs.h.

#define NVIC_STIR_INTID   (0x000003FFu)

Definition at line 10995 of file regs.h.

#define NVIC_STIR_INTID_BIT   (0)

Definition at line 10997 of file regs.h.

#define NVIC_STIR_INTID_BITS   (10)

Definition at line 10998 of file regs.h.

#define NVIC_STIR_INTID_MASK   (0x000003FFu)

Definition at line 10996 of file regs.h.

#define NVIC_STIR_REG   *((volatile int32u *)0xE000EF00u)

Definition at line 10991 of file regs.h.

#define NVIC_STIR_RESET   (0x00000000u)

Definition at line 10993 of file regs.h.

#define OPT_BYTE   *((volatile int32u *)0x4000801Cu)

Definition at line 3100 of file regs.h.

#define OPT_BYTE_ADDR   (0x4000801Cu)

Definition at line 3102 of file regs.h.

#define OPT_BYTE_OBR   (0x07FFFFFCu)

Definition at line 3110 of file regs.h.

#define OPT_BYTE_OBR_BIT   (2)

Definition at line 3112 of file regs.h.

#define OPT_BYTE_OBR_BITS   (25)

Definition at line 3113 of file regs.h.

#define OPT_BYTE_OBR_MASK   (0x07FFFFFCu)

Definition at line 3111 of file regs.h.

#define OPT_BYTE_OPT_ERR   (0x00000001u)

Definition at line 3120 of file regs.h.

#define OPT_BYTE_OPT_ERR_BIT   (0)

Definition at line 3122 of file regs.h.

#define OPT_BYTE_OPT_ERR_BITS   (1)

Definition at line 3123 of file regs.h.

#define OPT_BYTE_OPT_ERR_MASK   (0x00000001u)

Definition at line 3121 of file regs.h.

#define OPT_BYTE_RDPROT   (0x00000002u)

Definition at line 3115 of file regs.h.

#define OPT_BYTE_RDPROT_BIT   (1)

Definition at line 3117 of file regs.h.

#define OPT_BYTE_RDPROT_BITS   (1)

Definition at line 3118 of file regs.h.

#define OPT_BYTE_RDPROT_MASK   (0x00000002u)

Definition at line 3116 of file regs.h.

#define OPT_BYTE_REG   *((volatile int32u *)0x4000801Cu)

Definition at line 3101 of file regs.h.

#define OPT_BYTE_RESET   (0xFBFFFFFEu)

Definition at line 3103 of file regs.h.

#define OPT_BYTE_RSVD   (0xF8000000u)

Definition at line 3105 of file regs.h.

#define OPT_BYTE_RSVD_BIT   (27)

Definition at line 3107 of file regs.h.

#define OPT_BYTE_RSVD_BITS   (5)

Definition at line 3108 of file regs.h.

#define OPT_BYTE_RSVD_MASK   (0xF8000000u)

Definition at line 3106 of file regs.h.

#define OPT_ERR_MAINTAIN_WAKE   *((volatile int32u *)0x40000044u)

Definition at line 370 of file regs.h.

#define OPT_ERR_MAINTAIN_WAKE_ADDR   (0x40000044u)

Definition at line 372 of file regs.h.

#define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE   (0x00000001u)

Definition at line 375 of file regs.h.

#define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE_BIT   (0)

Definition at line 377 of file regs.h.

#define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE_BITS   (1)

Definition at line 378 of file regs.h.

#define OPT_ERR_MAINTAIN_WAKE_OPT_ERR_MAINTAIN_WAKE_MASK   (0x00000001u)

Definition at line 376 of file regs.h.

#define OPT_ERR_MAINTAIN_WAKE_REG   *((volatile int32u *)0x40000044u)

Definition at line 371 of file regs.h.

#define OPT_ERR_MAINTAIN_WAKE_RESET   (0x00000000u)

Definition at line 373 of file regs.h.

#define OPT_KEY   *((volatile int32u *)0x40008008u)

Definition at line 2975 of file regs.h.

#define OPT_KEY_ADDR   (0x40008008u)

Definition at line 2977 of file regs.h.

#define OPT_KEY_OPTKEYR   (0xFFFFFFFFu)

Definition at line 2980 of file regs.h.

#define OPT_KEY_OPTKEYR_BIT   (0)

Definition at line 2982 of file regs.h.

#define OPT_KEY_OPTKEYR_BITS   (32)

Definition at line 2983 of file regs.h.

#define OPT_KEY_OPTKEYR_MASK   (0xFFFFFFFFu)

Definition at line 2981 of file regs.h.

#define OPT_KEY_REG   *((volatile int32u *)0x40008008u)

Definition at line 2976 of file regs.h.

#define OPT_KEY_RESET   (0x00000000u)

Definition at line 2978 of file regs.h.

#define OSC24M_BIASTRIM   *((volatile int32u *)0x40004004u)

Definition at line 2475 of file regs.h.

#define OSC24M_BIASTRIM_ADDR   (0x40004004u)

Definition at line 2477 of file regs.h.

#define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM   (0x0000000Fu)

Definition at line 2480 of file regs.h.

#define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_BIT   (0)

Definition at line 2482 of file regs.h.

#define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_BITS   (4)

Definition at line 2483 of file regs.h.

#define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_MASK   (0x0000000Fu)

Definition at line 2481 of file regs.h.

#define OSC24M_BIASTRIM_REG   *((volatile int32u *)0x40004004u)

Definition at line 2476 of file regs.h.

#define OSC24M_BIASTRIM_RESET   (0x0000000Fu)

Definition at line 2478 of file regs.h.

#define OSC24M_COMP   *((volatile int32u *)0x4000400Cu)

Definition at line 2495 of file regs.h.

#define OSC24M_COMP_ADDR   (0x4000400Cu)

Definition at line 2497 of file regs.h.

#define OSC24M_COMP_REG   *((volatile int32u *)0x4000400Cu)

Definition at line 2496 of file regs.h.

#define OSC24M_COMP_RESET   (0x00000000u)

Definition at line 2498 of file regs.h.

#define OSC24M_CTRL   *((volatile int32u *)0x4000401Cu)

Definition at line 2540 of file regs.h.

#define OSC24M_CTRL_ADDR   (0x4000401Cu)

Definition at line 2542 of file regs.h.

#define OSC24M_CTRL_OSC24M_EN   (0x00000002u)

Definition at line 2545 of file regs.h.

#define OSC24M_CTRL_OSC24M_EN_BIT   (1)

Definition at line 2547 of file regs.h.

#define OSC24M_CTRL_OSC24M_EN_BITS   (1)

Definition at line 2548 of file regs.h.

#define OSC24M_CTRL_OSC24M_EN_MASK   (0x00000002u)

Definition at line 2546 of file regs.h.

#define OSC24M_CTRL_OSC24M_SEL   (0x00000001u)

Definition at line 2550 of file regs.h.

#define OSC24M_CTRL_OSC24M_SEL_BIT   (0)

Definition at line 2552 of file regs.h.

#define OSC24M_CTRL_OSC24M_SEL_BITS   (1)

Definition at line 2553 of file regs.h.

#define OSC24M_CTRL_OSC24M_SEL_MASK   (0x00000001u)

Definition at line 2551 of file regs.h.

#define OSC24M_CTRL_REG   *((volatile int32u *)0x4000401Cu)

Definition at line 2541 of file regs.h.

#define OSC24M_CTRL_RESET   (0x00000000u)

Definition at line 2543 of file regs.h.

#define OSC24M_HI   (0x00000002u)

Definition at line 2500 of file regs.h.

#define OSC24M_HI_BIT   (1)

Definition at line 2502 of file regs.h.

#define OSC24M_HI_BITS   (1)

Definition at line 2503 of file regs.h.

#define OSC24M_HI_MASK   (0x00000002u)

Definition at line 2501 of file regs.h.

#define OSC24M_LO   (0x00000001u)

Definition at line 2505 of file regs.h.

#define OSC24M_LO_BIT   (0)

Definition at line 2507 of file regs.h.

#define OSC24M_LO_BITS   (1)

Definition at line 2508 of file regs.h.

#define OSC24M_LO_MASK   (0x00000001u)

Definition at line 2506 of file regs.h.

#define OSCHF_TUNE   *((volatile int32u *)0x40004008u)

Definition at line 2485 of file regs.h.

#define OSCHF_TUNE_ADDR   (0x40004008u)

Definition at line 2487 of file regs.h.

#define OSCHF_TUNE_FIELD   (0x0000001Fu)

Definition at line 2490 of file regs.h.

#define OSCHF_TUNE_FIELD_BIT   (0)

Definition at line 2492 of file regs.h.

#define OSCHF_TUNE_FIELD_BITS   (5)

Definition at line 2493 of file regs.h.

#define OSCHF_TUNE_FIELD_MASK   (0x0000001Fu)

Definition at line 2491 of file regs.h.

#define OSCHF_TUNE_REG   *((volatile int32u *)0x40004008u)

Definition at line 2486 of file regs.h.

#define OSCHF_TUNE_RESET   (0x00000017u)

Definition at line 2488 of file regs.h.

#define PA0   (0x00000001u)

Definition at line 5356 of file regs.h.

#define PA0   (0x00000001u)

Definition at line 5356 of file regs.h.

#define PA0   (0x00000001u)

Definition at line 5356 of file regs.h.

#define PA0   (0x00000001u)

Definition at line 5356 of file regs.h.

#define PA0   (0x00000001u)

Definition at line 5356 of file regs.h.

#define PA0_BIT   (0)

Definition at line 5358 of file regs.h.

#define PA0_BIT   (0)

Definition at line 5358 of file regs.h.

#define PA0_BIT   (0)

Definition at line 5358 of file regs.h.

#define PA0_BIT   (0)

Definition at line 5358 of file regs.h.

#define PA0_BIT   (0)

Definition at line 5358 of file regs.h.

#define PA0_BITS   (1)

Definition at line 5359 of file regs.h.

#define PA0_BITS   (1)

Definition at line 5359 of file regs.h.

#define PA0_BITS   (1)

Definition at line 5359 of file regs.h.

#define PA0_BITS   (1)

Definition at line 5359 of file regs.h.

#define PA0_BITS   (1)

Definition at line 5359 of file regs.h.

#define PA0_CFG   (0x0000000Fu)

Definition at line 4580 of file regs.h.

#define PA0_CFG_BIT   (0)

Definition at line 4582 of file regs.h.

#define PA0_CFG_BITS   (4)

Definition at line 4583 of file regs.h.

#define PA0_CFG_MASK   (0x0000000Fu)

Definition at line 4581 of file regs.h.

#define PA0_MASK   (0x00000001u)

Definition at line 5357 of file regs.h.

#define PA0_MASK   (0x00000001u)

Definition at line 5357 of file regs.h.

#define PA0_MASK   (0x00000001u)

Definition at line 5357 of file regs.h.

#define PA0_MASK   (0x00000001u)

Definition at line 5357 of file regs.h.

#define PA0_MASK   (0x00000001u)

Definition at line 5357 of file regs.h.

#define PA1   (0x00000002u)

Definition at line 5351 of file regs.h.

#define PA1   (0x00000002u)

Definition at line 5351 of file regs.h.

#define PA1   (0x00000002u)

Definition at line 5351 of file regs.h.

#define PA1   (0x00000002u)

Definition at line 5351 of file regs.h.

#define PA1   (0x00000002u)

Definition at line 5351 of file regs.h.

#define PA1_BIT   (1)

Definition at line 5353 of file regs.h.

#define PA1_BIT   (1)

Definition at line 5353 of file regs.h.

#define PA1_BIT   (1)

Definition at line 5353 of file regs.h.

#define PA1_BIT   (1)

Definition at line 5353 of file regs.h.

#define PA1_BIT   (1)

Definition at line 5353 of file regs.h.

#define PA1_BITS   (1)

Definition at line 5354 of file regs.h.

#define PA1_BITS   (1)

Definition at line 5354 of file regs.h.

#define PA1_BITS   (1)

Definition at line 5354 of file regs.h.

#define PA1_BITS   (1)

Definition at line 5354 of file regs.h.

#define PA1_BITS   (1)

Definition at line 5354 of file regs.h.

#define PA1_CFG   (0x000000F0u)

Definition at line 4575 of file regs.h.

#define PA1_CFG_BIT   (4)

Definition at line 4577 of file regs.h.

#define PA1_CFG_BITS   (4)

Definition at line 4578 of file regs.h.

#define PA1_CFG_MASK   (0x000000F0u)

Definition at line 4576 of file regs.h.

#define PA1_MASK   (0x00000002u)

Definition at line 5352 of file regs.h.

#define PA1_MASK   (0x00000002u)

Definition at line 5352 of file regs.h.

#define PA1_MASK   (0x00000002u)

Definition at line 5352 of file regs.h.

#define PA1_MASK   (0x00000002u)

Definition at line 5352 of file regs.h.

#define PA1_MASK   (0x00000002u)

Definition at line 5352 of file regs.h.

#define PA2   (0x00000004u)

Definition at line 5346 of file regs.h.

#define PA2   (0x00000004u)

Definition at line 5346 of file regs.h.

#define PA2   (0x00000004u)

Definition at line 5346 of file regs.h.

#define PA2   (0x00000004u)

Definition at line 5346 of file regs.h.

#define PA2   (0x00000004u)

Definition at line 5346 of file regs.h.

#define PA2_BIT   (2)

Definition at line 5348 of file regs.h.

#define PA2_BIT   (2)

Definition at line 5348 of file regs.h.

#define PA2_BIT   (2)

Definition at line 5348 of file regs.h.

#define PA2_BIT   (2)

Definition at line 5348 of file regs.h.

#define PA2_BIT   (2)

Definition at line 5348 of file regs.h.

#define PA2_BITS   (1)

Definition at line 5349 of file regs.h.

#define PA2_BITS   (1)

Definition at line 5349 of file regs.h.

#define PA2_BITS   (1)

Definition at line 5349 of file regs.h.

#define PA2_BITS   (1)

Definition at line 5349 of file regs.h.

#define PA2_BITS   (1)

Definition at line 5349 of file regs.h.

#define PA2_CFG   (0x00000F00u)

Definition at line 4570 of file regs.h.

#define PA2_CFG_BIT   (8)

Definition at line 4572 of file regs.h.

#define PA2_CFG_BITS   (4)

Definition at line 4573 of file regs.h.

#define PA2_CFG_MASK   (0x00000F00u)

Definition at line 4571 of file regs.h.

#define PA2_MASK   (0x00000004u)

Definition at line 5347 of file regs.h.

#define PA2_MASK   (0x00000004u)

Definition at line 5347 of file regs.h.

#define PA2_MASK   (0x00000004u)

Definition at line 5347 of file regs.h.

#define PA2_MASK   (0x00000004u)

Definition at line 5347 of file regs.h.

#define PA2_MASK   (0x00000004u)

Definition at line 5347 of file regs.h.

#define PA3   (0x00000008u)

Definition at line 5341 of file regs.h.

#define PA3   (0x00000008u)

Definition at line 5341 of file regs.h.

#define PA3   (0x00000008u)

Definition at line 5341 of file regs.h.

#define PA3   (0x00000008u)

Definition at line 5341 of file regs.h.

#define PA3   (0x00000008u)

Definition at line 5341 of file regs.h.

#define PA3_BIT   (3)

Definition at line 5343 of file regs.h.

#define PA3_BIT   (3)

Definition at line 5343 of file regs.h.

#define PA3_BIT   (3)

Definition at line 5343 of file regs.h.

#define PA3_BIT   (3)

Definition at line 5343 of file regs.h.

#define PA3_BIT   (3)

Definition at line 5343 of file regs.h.

#define PA3_BITS   (1)

Definition at line 5344 of file regs.h.

#define PA3_BITS   (1)

Definition at line 5344 of file regs.h.

#define PA3_BITS   (1)

Definition at line 5344 of file regs.h.

#define PA3_BITS   (1)

Definition at line 5344 of file regs.h.

#define PA3_BITS   (1)

Definition at line 5344 of file regs.h.

#define PA3_CFG   (0x0000F000u)

Definition at line 4565 of file regs.h.

#define PA3_CFG_BIT   (12)

Definition at line 4567 of file regs.h.

#define PA3_CFG_BITS   (4)

Definition at line 4568 of file regs.h.

#define PA3_CFG_MASK   (0x0000F000u)

Definition at line 4566 of file regs.h.

#define PA3_MASK   (0x00000008u)

Definition at line 5342 of file regs.h.

#define PA3_MASK   (0x00000008u)

Definition at line 5342 of file regs.h.

#define PA3_MASK   (0x00000008u)

Definition at line 5342 of file regs.h.

#define PA3_MASK   (0x00000008u)

Definition at line 5342 of file regs.h.

#define PA3_MASK   (0x00000008u)

Definition at line 5342 of file regs.h.

#define PA4   (0x00000010u)

Definition at line 5336 of file regs.h.

#define PA4   (0x00000010u)

Definition at line 5336 of file regs.h.

#define PA4   (0x00000010u)

Definition at line 5336 of file regs.h.

#define PA4   (0x00000010u)

Definition at line 5336 of file regs.h.

#define PA4   (0x00000010u)

Definition at line 5336 of file regs.h.

#define PA4_BIT   (4)

Definition at line 5338 of file regs.h.

#define PA4_BIT   (4)

Definition at line 5338 of file regs.h.

#define PA4_BIT   (4)

Definition at line 5338 of file regs.h.

#define PA4_BIT   (4)

Definition at line 5338 of file regs.h.

#define PA4_BIT   (4)

Definition at line 5338 of file regs.h.

#define PA4_BITS   (1)

Definition at line 5339 of file regs.h.

#define PA4_BITS   (1)

Definition at line 5339 of file regs.h.

#define PA4_BITS   (1)

Definition at line 5339 of file regs.h.

#define PA4_BITS   (1)

Definition at line 5339 of file regs.h.

#define PA4_BITS   (1)

Definition at line 5339 of file regs.h.

#define PA4_CFG   (0x0000000Fu)

Definition at line 4613 of file regs.h.

#define PA4_CFG_BIT   (0)

Definition at line 4615 of file regs.h.

#define PA4_CFG_BITS   (4)

Definition at line 4616 of file regs.h.

#define PA4_CFG_MASK   (0x0000000Fu)

Definition at line 4614 of file regs.h.

#define PA4_MASK   (0x00000010u)

Definition at line 5337 of file regs.h.

#define PA4_MASK   (0x00000010u)

Definition at line 5337 of file regs.h.

#define PA4_MASK   (0x00000010u)

Definition at line 5337 of file regs.h.

#define PA4_MASK   (0x00000010u)

Definition at line 5337 of file regs.h.

#define PA4_MASK   (0x00000010u)

Definition at line 5337 of file regs.h.

#define PA5   (0x00000020u)

Definition at line 5331 of file regs.h.

#define PA5   (0x00000020u)

Definition at line 5331 of file regs.h.

#define PA5   (0x00000020u)

Definition at line 5331 of file regs.h.

#define PA5   (0x00000020u)

Definition at line 5331 of file regs.h.

#define PA5   (0x00000020u)

Definition at line 5331 of file regs.h.

#define PA5_BIT   (5)

Definition at line 5333 of file regs.h.

#define PA5_BIT   (5)

Definition at line 5333 of file regs.h.

#define PA5_BIT   (5)

Definition at line 5333 of file regs.h.

#define PA5_BIT   (5)

Definition at line 5333 of file regs.h.

#define PA5_BIT   (5)

Definition at line 5333 of file regs.h.

#define PA5_BITS   (1)

Definition at line 5334 of file regs.h.

#define PA5_BITS   (1)

Definition at line 5334 of file regs.h.

#define PA5_BITS   (1)

Definition at line 5334 of file regs.h.

#define PA5_BITS   (1)

Definition at line 5334 of file regs.h.

#define PA5_BITS   (1)

Definition at line 5334 of file regs.h.

#define PA5_CFG   (0x000000F0u)

Definition at line 4608 of file regs.h.

#define PA5_CFG_BIT   (4)

Definition at line 4610 of file regs.h.

#define PA5_CFG_BITS   (4)

Definition at line 4611 of file regs.h.

#define PA5_CFG_MASK   (0x000000F0u)

Definition at line 4609 of file regs.h.

#define PA5_MASK   (0x00000020u)

Definition at line 5332 of file regs.h.

#define PA5_MASK   (0x00000020u)

Definition at line 5332 of file regs.h.

#define PA5_MASK   (0x00000020u)

Definition at line 5332 of file regs.h.

#define PA5_MASK   (0x00000020u)

Definition at line 5332 of file regs.h.

#define PA5_MASK   (0x00000020u)

Definition at line 5332 of file regs.h.

#define PA6   (0x00000040u)

Definition at line 5326 of file regs.h.

#define PA6   (0x00000040u)

Definition at line 5326 of file regs.h.

#define PA6   (0x00000040u)

Definition at line 5326 of file regs.h.

#define PA6   (0x00000040u)

Definition at line 5326 of file regs.h.

#define PA6   (0x00000040u)

Definition at line 5326 of file regs.h.

#define PA6_BIT   (6)

Definition at line 5328 of file regs.h.

#define PA6_BIT   (6)

Definition at line 5328 of file regs.h.

#define PA6_BIT   (6)

Definition at line 5328 of file regs.h.

#define PA6_BIT   (6)

Definition at line 5328 of file regs.h.

#define PA6_BIT   (6)

Definition at line 5328 of file regs.h.

#define PA6_BITS   (1)

Definition at line 5329 of file regs.h.

#define PA6_BITS   (1)

Definition at line 5329 of file regs.h.

#define PA6_BITS   (1)

Definition at line 5329 of file regs.h.

#define PA6_BITS   (1)

Definition at line 5329 of file regs.h.

#define PA6_BITS   (1)

Definition at line 5329 of file regs.h.

#define PA6_CFG   (0x00000F00u)

Definition at line 4603 of file regs.h.

#define PA6_CFG_BIT   (8)

Definition at line 4605 of file regs.h.

#define PA6_CFG_BITS   (4)

Definition at line 4606 of file regs.h.

#define PA6_CFG_MASK   (0x00000F00u)

Definition at line 4604 of file regs.h.

#define PA6_MASK   (0x00000040u)

Definition at line 5327 of file regs.h.

#define PA6_MASK   (0x00000040u)

Definition at line 5327 of file regs.h.

#define PA6_MASK   (0x00000040u)

Definition at line 5327 of file regs.h.

#define PA6_MASK   (0x00000040u)

Definition at line 5327 of file regs.h.

#define PA6_MASK   (0x00000040u)

Definition at line 5327 of file regs.h.

#define PA7   (0x00000080u)

Definition at line 5321 of file regs.h.

#define PA7   (0x00000080u)

Definition at line 5321 of file regs.h.

#define PA7   (0x00000080u)

Definition at line 5321 of file regs.h.

#define PA7   (0x00000080u)

Definition at line 5321 of file regs.h.

#define PA7   (0x00000080u)

Definition at line 5321 of file regs.h.

#define PA7_BIT   (7)

Definition at line 5323 of file regs.h.

#define PA7_BIT   (7)

Definition at line 5323 of file regs.h.

#define PA7_BIT   (7)

Definition at line 5323 of file regs.h.

#define PA7_BIT   (7)

Definition at line 5323 of file regs.h.

#define PA7_BIT   (7)

Definition at line 5323 of file regs.h.

#define PA7_BITS   (1)

Definition at line 5324 of file regs.h.

#define PA7_BITS   (1)

Definition at line 5324 of file regs.h.

#define PA7_BITS   (1)

Definition at line 5324 of file regs.h.

#define PA7_BITS   (1)

Definition at line 5324 of file regs.h.

#define PA7_BITS   (1)

Definition at line 5324 of file regs.h.

#define PA7_CFG   (0x0000F000u)

Definition at line 4598 of file regs.h.

#define PA7_CFG_BIT   (12)

Definition at line 4600 of file regs.h.

#define PA7_CFG_BITS   (4)

Definition at line 4601 of file regs.h.

#define PA7_CFG_MASK   (0x0000F000u)

Definition at line 4599 of file regs.h.

#define PA7_MASK   (0x00000080u)

Definition at line 5322 of file regs.h.

#define PA7_MASK   (0x00000080u)

Definition at line 5322 of file regs.h.

#define PA7_MASK   (0x00000080u)

Definition at line 5322 of file regs.h.

#define PA7_MASK   (0x00000080u)

Definition at line 5322 of file regs.h.

#define PA7_MASK   (0x00000080u)

Definition at line 5322 of file regs.h.

#define PAN_ID   *((volatile int32u *)0x40002090u)

Definition at line 2085 of file regs.h.

#define PAN_ID_ADDR   (0x40002090u)

Definition at line 2087 of file regs.h.

#define PAN_ID_PAN_ID   (0x0000FFFFu)

Definition at line 2090 of file regs.h.

#define PAN_ID_PAN_ID_BIT   (0)

Definition at line 2092 of file regs.h.

#define PAN_ID_PAN_ID_BITS   (16)

Definition at line 2093 of file regs.h.

#define PAN_ID_PAN_ID_MASK   (0x0000FFFFu)

Definition at line 2091 of file regs.h.

#define PAN_ID_REG   *((volatile int32u *)0x40002090u)

Definition at line 2086 of file regs.h.

#define PAN_ID_RESET   (0x00000000u)

Definition at line 2088 of file regs.h.

#define PANID_COUNT   *((volatile int32u *)0x400020C4u)

Definition at line 2255 of file regs.h.

#define PANID_COUNT_ADDR   (0x400020C4u)

Definition at line 2257 of file regs.h.

#define PANID_COUNT_PANID_COUNT   (0x0000FFFFu)

Definition at line 2260 of file regs.h.

#define PANID_COUNT_PANID_COUNT_BIT   (0)

Definition at line 2262 of file regs.h.

#define PANID_COUNT_PANID_COUNT_BITS   (16)

Definition at line 2263 of file regs.h.

#define PANID_COUNT_PANID_COUNT_MASK   (0x0000FFFFu)

Definition at line 2261 of file regs.h.

#define PANID_COUNT_REG   *((volatile int32u *)0x400020C4u)

Definition at line 2256 of file regs.h.

#define PANID_COUNT_RESET   (0x00000000u)

Definition at line 2258 of file regs.h.

#define PB0   (0x00000001u)

Definition at line 5401 of file regs.h.

#define PB0   (0x00000001u)

Definition at line 5401 of file regs.h.

#define PB0   (0x00000001u)

Definition at line 5401 of file regs.h.

#define PB0   (0x00000001u)

Definition at line 5401 of file regs.h.

#define PB0   (0x00000001u)

Definition at line 5401 of file regs.h.

#define PB0_BIT   (0)

Definition at line 5403 of file regs.h.

#define PB0_BIT   (0)

Definition at line 5403 of file regs.h.

#define PB0_BIT   (0)

Definition at line 5403 of file regs.h.

#define PB0_BIT   (0)

Definition at line 5403 of file regs.h.

#define PB0_BIT   (0)

Definition at line 5403 of file regs.h.

#define PB0_BITS   (1)

Definition at line 5404 of file regs.h.

#define PB0_BITS   (1)

Definition at line 5404 of file regs.h.

#define PB0_BITS   (1)

Definition at line 5404 of file regs.h.

#define PB0_BITS   (1)

Definition at line 5404 of file regs.h.

#define PB0_BITS   (1)

Definition at line 5404 of file regs.h.

#define PB0_CFG   (0x0000000Fu)

Definition at line 4826 of file regs.h.

#define PB0_CFG_BIT   (0)

Definition at line 4828 of file regs.h.

#define PB0_CFG_BITS   (4)

Definition at line 4829 of file regs.h.

#define PB0_CFG_MASK   (0x0000000Fu)

Definition at line 4827 of file regs.h.

#define PB0_MASK   (0x00000001u)

Definition at line 5402 of file regs.h.

#define PB0_MASK   (0x00000001u)

Definition at line 5402 of file regs.h.

#define PB0_MASK   (0x00000001u)

Definition at line 5402 of file regs.h.

#define PB0_MASK   (0x00000001u)

Definition at line 5402 of file regs.h.

#define PB0_MASK   (0x00000001u)

Definition at line 5402 of file regs.h.

#define PB1   (0x00000002u)

Definition at line 5396 of file regs.h.

#define PB1   (0x00000002u)

Definition at line 5396 of file regs.h.

#define PB1   (0x00000002u)

Definition at line 5396 of file regs.h.

#define PB1   (0x00000002u)

Definition at line 5396 of file regs.h.

#define PB1   (0x00000002u)

Definition at line 5396 of file regs.h.

#define PB1_BIT   (1)

Definition at line 5398 of file regs.h.

#define PB1_BIT   (1)

Definition at line 5398 of file regs.h.

#define PB1_BIT   (1)

Definition at line 5398 of file regs.h.

#define PB1_BIT   (1)

Definition at line 5398 of file regs.h.

#define PB1_BIT   (1)

Definition at line 5398 of file regs.h.

#define PB1_BITS   (1)

Definition at line 5399 of file regs.h.

#define PB1_BITS   (1)

Definition at line 5399 of file regs.h.

#define PB1_BITS   (1)

Definition at line 5399 of file regs.h.

#define PB1_BITS   (1)

Definition at line 5399 of file regs.h.

#define PB1_BITS   (1)

Definition at line 5399 of file regs.h.

#define PB1_CFG   (0x000000F0u)

Definition at line 4821 of file regs.h.

#define PB1_CFG_BIT   (4)

Definition at line 4823 of file regs.h.

#define PB1_CFG_BITS   (4)

Definition at line 4824 of file regs.h.

#define PB1_CFG_MASK   (0x000000F0u)

Definition at line 4822 of file regs.h.

#define PB1_MASK   (0x00000002u)

Definition at line 5397 of file regs.h.

#define PB1_MASK   (0x00000002u)

Definition at line 5397 of file regs.h.

#define PB1_MASK   (0x00000002u)

Definition at line 5397 of file regs.h.

#define PB1_MASK   (0x00000002u)

Definition at line 5397 of file regs.h.

#define PB1_MASK   (0x00000002u)

Definition at line 5397 of file regs.h.

#define PB2   (0x00000004u)

Definition at line 5391 of file regs.h.

#define PB2   (0x00000004u)

Definition at line 5391 of file regs.h.

#define PB2   (0x00000004u)

Definition at line 5391 of file regs.h.

#define PB2   (0x00000004u)

Definition at line 5391 of file regs.h.

#define PB2   (0x00000004u)

Definition at line 5391 of file regs.h.

#define PB2_BIT   (2)

Definition at line 5393 of file regs.h.

#define PB2_BIT   (2)

Definition at line 5393 of file regs.h.

#define PB2_BIT   (2)

Definition at line 5393 of file regs.h.

#define PB2_BIT   (2)

Definition at line 5393 of file regs.h.

#define PB2_BIT   (2)

Definition at line 5393 of file regs.h.

#define PB2_BITS   (1)

Definition at line 5394 of file regs.h.

#define PB2_BITS   (1)

Definition at line 5394 of file regs.h.

#define PB2_BITS   (1)

Definition at line 5394 of file regs.h.

#define PB2_BITS   (1)

Definition at line 5394 of file regs.h.

#define PB2_BITS   (1)

Definition at line 5394 of file regs.h.

#define PB2_CFG   (0x00000F00u)

Definition at line 4816 of file regs.h.

#define PB2_CFG_BIT   (8)

Definition at line 4818 of file regs.h.

#define PB2_CFG_BITS   (4)

Definition at line 4819 of file regs.h.

#define PB2_CFG_MASK   (0x00000F00u)

Definition at line 4817 of file regs.h.

#define PB2_MASK   (0x00000004u)

Definition at line 5392 of file regs.h.

#define PB2_MASK   (0x00000004u)

Definition at line 5392 of file regs.h.

#define PB2_MASK   (0x00000004u)

Definition at line 5392 of file regs.h.

#define PB2_MASK   (0x00000004u)

Definition at line 5392 of file regs.h.

#define PB2_MASK   (0x00000004u)

Definition at line 5392 of file regs.h.

#define PB3   (0x00000008u)

Definition at line 5386 of file regs.h.

#define PB3   (0x00000008u)

Definition at line 5386 of file regs.h.

#define PB3   (0x00000008u)

Definition at line 5386 of file regs.h.

#define PB3   (0x00000008u)

Definition at line 5386 of file regs.h.

#define PB3   (0x00000008u)

Definition at line 5386 of file regs.h.

#define PB3_BIT   (3)

Definition at line 5388 of file regs.h.

#define PB3_BIT   (3)

Definition at line 5388 of file regs.h.

#define PB3_BIT   (3)

Definition at line 5388 of file regs.h.

#define PB3_BIT   (3)

Definition at line 5388 of file regs.h.

#define PB3_BIT   (3)

Definition at line 5388 of file regs.h.

#define PB3_BITS   (1)

Definition at line 5389 of file regs.h.

#define PB3_BITS   (1)

Definition at line 5389 of file regs.h.

#define PB3_BITS   (1)

Definition at line 5389 of file regs.h.

#define PB3_BITS   (1)

Definition at line 5389 of file regs.h.

#define PB3_BITS   (1)

Definition at line 5389 of file regs.h.

#define PB3_CFG   (0x0000F000u)

Definition at line 4811 of file regs.h.

#define PB3_CFG_BIT   (12)

Definition at line 4813 of file regs.h.

#define PB3_CFG_BITS   (4)

Definition at line 4814 of file regs.h.

#define PB3_CFG_MASK   (0x0000F000u)

Definition at line 4812 of file regs.h.

#define PB3_MASK   (0x00000008u)

Definition at line 5387 of file regs.h.

#define PB3_MASK   (0x00000008u)

Definition at line 5387 of file regs.h.

#define PB3_MASK   (0x00000008u)

Definition at line 5387 of file regs.h.

#define PB3_MASK   (0x00000008u)

Definition at line 5387 of file regs.h.

#define PB3_MASK   (0x00000008u)

Definition at line 5387 of file regs.h.

#define PB4   (0x00000010u)

Definition at line 5381 of file regs.h.

#define PB4   (0x00000010u)

Definition at line 5381 of file regs.h.

#define PB4   (0x00000010u)

Definition at line 5381 of file regs.h.

#define PB4   (0x00000010u)

Definition at line 5381 of file regs.h.

#define PB4   (0x00000010u)

Definition at line 5381 of file regs.h.

#define PB4_BIT   (4)

Definition at line 5383 of file regs.h.

#define PB4_BIT   (4)

Definition at line 5383 of file regs.h.

#define PB4_BIT   (4)

Definition at line 5383 of file regs.h.

#define PB4_BIT   (4)

Definition at line 5383 of file regs.h.

#define PB4_BIT   (4)

Definition at line 5383 of file regs.h.

#define PB4_BITS   (1)

Definition at line 5384 of file regs.h.

#define PB4_BITS   (1)

Definition at line 5384 of file regs.h.

#define PB4_BITS   (1)

Definition at line 5384 of file regs.h.

#define PB4_BITS   (1)

Definition at line 5384 of file regs.h.

#define PB4_BITS   (1)

Definition at line 5384 of file regs.h.

#define PB4_CFG   (0x0000000Fu)

Definition at line 4851 of file regs.h.

#define PB4_CFG_BIT   (0)

Definition at line 4853 of file regs.h.

#define PB4_CFG_BITS   (4)

Definition at line 4854 of file regs.h.

#define PB4_CFG_MASK   (0x0000000Fu)

Definition at line 4852 of file regs.h.

#define PB4_MASK   (0x00000010u)

Definition at line 5382 of file regs.h.

#define PB4_MASK   (0x00000010u)

Definition at line 5382 of file regs.h.

#define PB4_MASK   (0x00000010u)

Definition at line 5382 of file regs.h.

#define PB4_MASK   (0x00000010u)

Definition at line 5382 of file regs.h.

#define PB4_MASK   (0x00000010u)

Definition at line 5382 of file regs.h.

#define PB5   (0x00000020u)

Definition at line 5376 of file regs.h.

#define PB5   (0x00000020u)

Definition at line 5376 of file regs.h.

#define PB5   (0x00000020u)

Definition at line 5376 of file regs.h.

#define PB5   (0x00000020u)

Definition at line 5376 of file regs.h.

#define PB5   (0x00000020u)

Definition at line 5376 of file regs.h.

#define PB5_BIT   (5)

Definition at line 5378 of file regs.h.

#define PB5_BIT   (5)

Definition at line 5378 of file regs.h.

#define PB5_BIT   (5)

Definition at line 5378 of file regs.h.

#define PB5_BIT   (5)

Definition at line 5378 of file regs.h.

#define PB5_BIT   (5)

Definition at line 5378 of file regs.h.

#define PB5_BITS   (1)

Definition at line 5379 of file regs.h.

#define PB5_BITS   (1)

Definition at line 5379 of file regs.h.

#define PB5_BITS   (1)

Definition at line 5379 of file regs.h.

#define PB5_BITS   (1)

Definition at line 5379 of file regs.h.

#define PB5_BITS   (1)

Definition at line 5379 of file regs.h.

#define PB5_CFG   (0x000000F0u)

Definition at line 4846 of file regs.h.

#define PB5_CFG_BIT   (4)

Definition at line 4848 of file regs.h.

#define PB5_CFG_BITS   (4)

Definition at line 4849 of file regs.h.

#define PB5_CFG_MASK   (0x000000F0u)

Definition at line 4847 of file regs.h.

#define PB5_MASK   (0x00000020u)

Definition at line 5377 of file regs.h.

#define PB5_MASK   (0x00000020u)

Definition at line 5377 of file regs.h.

#define PB5_MASK   (0x00000020u)

Definition at line 5377 of file regs.h.

#define PB5_MASK   (0x00000020u)

Definition at line 5377 of file regs.h.

#define PB5_MASK   (0x00000020u)

Definition at line 5377 of file regs.h.

#define PB6   (0x00000040u)

Definition at line 5371 of file regs.h.

#define PB6   (0x00000040u)

Definition at line 5371 of file regs.h.

#define PB6   (0x00000040u)

Definition at line 5371 of file regs.h.

#define PB6   (0x00000040u)

Definition at line 5371 of file regs.h.

#define PB6   (0x00000040u)

Definition at line 5371 of file regs.h.

#define PB6_BIT   (6)

Definition at line 5373 of file regs.h.

#define PB6_BIT   (6)

Definition at line 5373 of file regs.h.

#define PB6_BIT   (6)

Definition at line 5373 of file regs.h.

#define PB6_BIT   (6)

Definition at line 5373 of file regs.h.

#define PB6_BIT   (6)

Definition at line 5373 of file regs.h.

#define PB6_BITS   (1)

Definition at line 5374 of file regs.h.

#define PB6_BITS   (1)

Definition at line 5374 of file regs.h.

#define PB6_BITS   (1)

Definition at line 5374 of file regs.h.

#define PB6_BITS   (1)

Definition at line 5374 of file regs.h.

#define PB6_BITS   (1)

Definition at line 5374 of file regs.h.

#define PB6_CFG   (0x00000F00u)

Definition at line 4841 of file regs.h.

#define PB6_CFG_BIT   (8)

Definition at line 4843 of file regs.h.

#define PB6_CFG_BITS   (4)

Definition at line 4844 of file regs.h.

#define PB6_CFG_MASK   (0x00000F00u)

Definition at line 4842 of file regs.h.

#define PB6_MASK   (0x00000040u)

Definition at line 5372 of file regs.h.

#define PB6_MASK   (0x00000040u)

Definition at line 5372 of file regs.h.

#define PB6_MASK   (0x00000040u)

Definition at line 5372 of file regs.h.

#define PB6_MASK   (0x00000040u)

Definition at line 5372 of file regs.h.

#define PB6_MASK   (0x00000040u)

Definition at line 5372 of file regs.h.

#define PB7   (0x00000080u)

Definition at line 5366 of file regs.h.

#define PB7   (0x00000080u)

Definition at line 5366 of file regs.h.

#define PB7   (0x00000080u)

Definition at line 5366 of file regs.h.

#define PB7   (0x00000080u)

Definition at line 5366 of file regs.h.

#define PB7   (0x00000080u)

Definition at line 5366 of file regs.h.

#define PB7_BIT   (7)

Definition at line 5368 of file regs.h.

#define PB7_BIT   (7)

Definition at line 5368 of file regs.h.

#define PB7_BIT   (7)

Definition at line 5368 of file regs.h.

#define PB7_BIT   (7)

Definition at line 5368 of file regs.h.

#define PB7_BIT   (7)

Definition at line 5368 of file regs.h.

#define PB7_BITS   (1)

Definition at line 5369 of file regs.h.

#define PB7_BITS   (1)

Definition at line 5369 of file regs.h.

#define PB7_BITS   (1)

Definition at line 5369 of file regs.h.

#define PB7_BITS   (1)

Definition at line 5369 of file regs.h.

#define PB7_BITS   (1)

Definition at line 5369 of file regs.h.

#define PB7_CFG   (0x0000F000u)

Definition at line 4836 of file regs.h.

#define PB7_CFG_BIT   (12)

Definition at line 4838 of file regs.h.

#define PB7_CFG_BITS   (4)

Definition at line 4839 of file regs.h.

#define PB7_CFG_MASK   (0x0000F000u)

Definition at line 4837 of file regs.h.

#define PB7_MASK   (0x00000080u)

Definition at line 5367 of file regs.h.

#define PB7_MASK   (0x00000080u)

Definition at line 5367 of file regs.h.

#define PB7_MASK   (0x00000080u)

Definition at line 5367 of file regs.h.

#define PB7_MASK   (0x00000080u)

Definition at line 5367 of file regs.h.

#define PB7_MASK   (0x00000080u)

Definition at line 5367 of file regs.h.

#define PC0   (0x00000001u)

Definition at line 5446 of file regs.h.

#define PC0   (0x00000001u)

Definition at line 5446 of file regs.h.

#define PC0   (0x00000001u)

Definition at line 5446 of file regs.h.

#define PC0   (0x00000001u)

Definition at line 5446 of file regs.h.

#define PC0   (0x00000001u)

Definition at line 5446 of file regs.h.

#define PC0_BIT   (0)

Definition at line 5448 of file regs.h.

#define PC0_BIT   (0)

Definition at line 5448 of file regs.h.

#define PC0_BIT   (0)

Definition at line 5448 of file regs.h.

#define PC0_BIT   (0)

Definition at line 5448 of file regs.h.

#define PC0_BIT   (0)

Definition at line 5448 of file regs.h.

#define PC0_BITS   (1)

Definition at line 5449 of file regs.h.

#define PC0_BITS   (1)

Definition at line 5449 of file regs.h.

#define PC0_BITS   (1)

Definition at line 5449 of file regs.h.

#define PC0_BITS   (1)

Definition at line 5449 of file regs.h.

#define PC0_BITS   (1)

Definition at line 5449 of file regs.h.

#define PC0_CFG   (0x0000000Fu)

Definition at line 5061 of file regs.h.

#define PC0_CFG_BIT   (0)

Definition at line 5063 of file regs.h.

#define PC0_CFG_BITS   (4)

Definition at line 5064 of file regs.h.

#define PC0_CFG_MASK   (0x0000000Fu)

Definition at line 5062 of file regs.h.

#define PC0_MASK   (0x00000001u)

Definition at line 5447 of file regs.h.

#define PC0_MASK   (0x00000001u)

Definition at line 5447 of file regs.h.

#define PC0_MASK   (0x00000001u)

Definition at line 5447 of file regs.h.

#define PC0_MASK   (0x00000001u)

Definition at line 5447 of file regs.h.

#define PC0_MASK   (0x00000001u)

Definition at line 5447 of file regs.h.

#define PC1   (0x00000002u)

Definition at line 5441 of file regs.h.

#define PC1   (0x00000002u)

Definition at line 5441 of file regs.h.

#define PC1   (0x00000002u)

Definition at line 5441 of file regs.h.

#define PC1   (0x00000002u)

Definition at line 5441 of file regs.h.

#define PC1   (0x00000002u)

Definition at line 5441 of file regs.h.

#define PC1_BIT   (1)

Definition at line 5443 of file regs.h.

#define PC1_BIT   (1)

Definition at line 5443 of file regs.h.

#define PC1_BIT   (1)

Definition at line 5443 of file regs.h.

#define PC1_BIT   (1)

Definition at line 5443 of file regs.h.

#define PC1_BIT   (1)

Definition at line 5443 of file regs.h.

#define PC1_BITS   (1)

Definition at line 5444 of file regs.h.

#define PC1_BITS   (1)

Definition at line 5444 of file regs.h.

#define PC1_BITS   (1)

Definition at line 5444 of file regs.h.

#define PC1_BITS   (1)

Definition at line 5444 of file regs.h.

#define PC1_BITS   (1)

Definition at line 5444 of file regs.h.

#define PC1_CFG   (0x000000F0u)

Definition at line 5056 of file regs.h.

#define PC1_CFG_BIT   (4)

Definition at line 5058 of file regs.h.

#define PC1_CFG_BITS   (4)

Definition at line 5059 of file regs.h.

#define PC1_CFG_MASK   (0x000000F0u)

Definition at line 5057 of file regs.h.

#define PC1_MASK   (0x00000002u)

Definition at line 5442 of file regs.h.

#define PC1_MASK   (0x00000002u)

Definition at line 5442 of file regs.h.

#define PC1_MASK   (0x00000002u)

Definition at line 5442 of file regs.h.

#define PC1_MASK   (0x00000002u)

Definition at line 5442 of file regs.h.

#define PC1_MASK   (0x00000002u)

Definition at line 5442 of file regs.h.

#define PC2   (0x00000004u)

Definition at line 5436 of file regs.h.

#define PC2   (0x00000004u)

Definition at line 5436 of file regs.h.

#define PC2   (0x00000004u)

Definition at line 5436 of file regs.h.

#define PC2   (0x00000004u)

Definition at line 5436 of file regs.h.

#define PC2   (0x00000004u)

Definition at line 5436 of file regs.h.

#define PC2_BIT   (2)

Definition at line 5438 of file regs.h.

#define PC2_BIT   (2)

Definition at line 5438 of file regs.h.

#define PC2_BIT   (2)

Definition at line 5438 of file regs.h.

#define PC2_BIT   (2)

Definition at line 5438 of file regs.h.

#define PC2_BIT   (2)

Definition at line 5438 of file regs.h.

#define PC2_BITS   (1)

Definition at line 5439 of file regs.h.

#define PC2_BITS   (1)

Definition at line 5439 of file regs.h.

#define PC2_BITS   (1)

Definition at line 5439 of file regs.h.

#define PC2_BITS   (1)

Definition at line 5439 of file regs.h.

#define PC2_BITS   (1)

Definition at line 5439 of file regs.h.

#define PC2_CFG   (0x00000F00u)

Definition at line 5051 of file regs.h.

#define PC2_CFG_BIT   (8)

Definition at line 5053 of file regs.h.

#define PC2_CFG_BITS   (4)

Definition at line 5054 of file regs.h.

#define PC2_CFG_MASK   (0x00000F00u)

Definition at line 5052 of file regs.h.

#define PC2_MASK   (0x00000004u)

Definition at line 5437 of file regs.h.

#define PC2_MASK   (0x00000004u)

Definition at line 5437 of file regs.h.

#define PC2_MASK   (0x00000004u)

Definition at line 5437 of file regs.h.

#define PC2_MASK   (0x00000004u)

Definition at line 5437 of file regs.h.

#define PC2_MASK   (0x00000004u)

Definition at line 5437 of file regs.h.

#define PC3   (0x00000008u)

Definition at line 5431 of file regs.h.

#define PC3   (0x00000008u)

Definition at line 5431 of file regs.h.

#define PC3   (0x00000008u)

Definition at line 5431 of file regs.h.

#define PC3   (0x00000008u)

Definition at line 5431 of file regs.h.

#define PC3   (0x00000008u)

Definition at line 5431 of file regs.h.

#define PC3_BIT   (3)

Definition at line 5433 of file regs.h.

#define PC3_BIT   (3)

Definition at line 5433 of file regs.h.

#define PC3_BIT   (3)

Definition at line 5433 of file regs.h.

#define PC3_BIT   (3)

Definition at line 5433 of file regs.h.

#define PC3_BIT   (3)

Definition at line 5433 of file regs.h.

#define PC3_BITS   (1)

Definition at line 5434 of file regs.h.

#define PC3_BITS   (1)

Definition at line 5434 of file regs.h.

#define PC3_BITS   (1)

Definition at line 5434 of file regs.h.

#define PC3_BITS   (1)

Definition at line 5434 of file regs.h.

#define PC3_BITS   (1)

Definition at line 5434 of file regs.h.

#define PC3_CFG   (0x0000F000u)

Definition at line 5046 of file regs.h.

#define PC3_CFG_BIT   (12)

Definition at line 5048 of file regs.h.

#define PC3_CFG_BITS   (4)

Definition at line 5049 of file regs.h.

#define PC3_CFG_MASK   (0x0000F000u)

Definition at line 5047 of file regs.h.

#define PC3_MASK   (0x00000008u)

Definition at line 5432 of file regs.h.

#define PC3_MASK   (0x00000008u)

Definition at line 5432 of file regs.h.

#define PC3_MASK   (0x00000008u)

Definition at line 5432 of file regs.h.

#define PC3_MASK   (0x00000008u)

Definition at line 5432 of file regs.h.

#define PC3_MASK   (0x00000008u)

Definition at line 5432 of file regs.h.

#define PC4   (0x00000010u)

Definition at line 5426 of file regs.h.

#define PC4   (0x00000010u)

Definition at line 5426 of file regs.h.

#define PC4   (0x00000010u)

Definition at line 5426 of file regs.h.

#define PC4   (0x00000010u)

Definition at line 5426 of file regs.h.

#define PC4   (0x00000010u)

Definition at line 5426 of file regs.h.

#define PC4_BIT   (4)

Definition at line 5428 of file regs.h.

#define PC4_BIT   (4)

Definition at line 5428 of file regs.h.

#define PC4_BIT   (4)

Definition at line 5428 of file regs.h.

#define PC4_BIT   (4)

Definition at line 5428 of file regs.h.

#define PC4_BIT   (4)

Definition at line 5428 of file regs.h.

#define PC4_BITS   (1)

Definition at line 5429 of file regs.h.

#define PC4_BITS   (1)

Definition at line 5429 of file regs.h.

#define PC4_BITS   (1)

Definition at line 5429 of file regs.h.

#define PC4_BITS   (1)

Definition at line 5429 of file regs.h.

#define PC4_BITS   (1)

Definition at line 5429 of file regs.h.

#define PC4_CFG   (0x0000000Fu)

Definition at line 5086 of file regs.h.

#define PC4_CFG_BIT   (0)

Definition at line 5088 of file regs.h.

#define PC4_CFG_BITS   (4)

Definition at line 5089 of file regs.h.

#define PC4_CFG_MASK   (0x0000000Fu)

Definition at line 5087 of file regs.h.

#define PC4_MASK   (0x00000010u)

Definition at line 5427 of file regs.h.

#define PC4_MASK   (0x00000010u)

Definition at line 5427 of file regs.h.

#define PC4_MASK   (0x00000010u)

Definition at line 5427 of file regs.h.

#define PC4_MASK   (0x00000010u)

Definition at line 5427 of file regs.h.

#define PC4_MASK   (0x00000010u)

Definition at line 5427 of file regs.h.

#define PC5   (0x00000020u)

Definition at line 5421 of file regs.h.

#define PC5   (0x00000020u)

Definition at line 5421 of file regs.h.

#define PC5   (0x00000020u)

Definition at line 5421 of file regs.h.

#define PC5   (0x00000020u)

Definition at line 5421 of file regs.h.

#define PC5   (0x00000020u)

Definition at line 5421 of file regs.h.

#define PC5_BIT   (5)

Definition at line 5423 of file regs.h.

#define PC5_BIT   (5)

Definition at line 5423 of file regs.h.

#define PC5_BIT   (5)

Definition at line 5423 of file regs.h.

#define PC5_BIT   (5)

Definition at line 5423 of file regs.h.

#define PC5_BIT   (5)

Definition at line 5423 of file regs.h.

#define PC5_BITS   (1)

Definition at line 5424 of file regs.h.

#define PC5_BITS   (1)

Definition at line 5424 of file regs.h.

#define PC5_BITS   (1)

Definition at line 5424 of file regs.h.

#define PC5_BITS   (1)

Definition at line 5424 of file regs.h.

#define PC5_BITS   (1)

Definition at line 5424 of file regs.h.

#define PC5_CFG   (0x000000F0u)

Definition at line 5081 of file regs.h.

#define PC5_CFG_BIT   (4)

Definition at line 5083 of file regs.h.

#define PC5_CFG_BITS   (4)

Definition at line 5084 of file regs.h.

#define PC5_CFG_MASK   (0x000000F0u)

Definition at line 5082 of file regs.h.

#define PC5_MASK   (0x00000020u)

Definition at line 5422 of file regs.h.

#define PC5_MASK   (0x00000020u)

Definition at line 5422 of file regs.h.

#define PC5_MASK   (0x00000020u)

Definition at line 5422 of file regs.h.

#define PC5_MASK   (0x00000020u)

Definition at line 5422 of file regs.h.

#define PC5_MASK   (0x00000020u)

Definition at line 5422 of file regs.h.

#define PC6   (0x00000040u)

Definition at line 5416 of file regs.h.

#define PC6   (0x00000040u)

Definition at line 5416 of file regs.h.

#define PC6   (0x00000040u)

Definition at line 5416 of file regs.h.

#define PC6   (0x00000040u)

Definition at line 5416 of file regs.h.

#define PC6   (0x00000040u)

Definition at line 5416 of file regs.h.

#define PC6_BIT   (6)

Definition at line 5418 of file regs.h.

#define PC6_BIT   (6)

Definition at line 5418 of file regs.h.

#define PC6_BIT   (6)

Definition at line 5418 of file regs.h.

#define PC6_BIT   (6)

Definition at line 5418 of file regs.h.

#define PC6_BIT   (6)

Definition at line 5418 of file regs.h.

#define PC6_BITS   (1)

Definition at line 5419 of file regs.h.

#define PC6_BITS   (1)

Definition at line 5419 of file regs.h.

#define PC6_BITS   (1)

Definition at line 5419 of file regs.h.

#define PC6_BITS   (1)

Definition at line 5419 of file regs.h.

#define PC6_BITS   (1)

Definition at line 5419 of file regs.h.

#define PC6_CFG   (0x00000F00u)

Definition at line 5076 of file regs.h.

#define PC6_CFG_BIT   (8)

Definition at line 5078 of file regs.h.

#define PC6_CFG_BITS   (4)

Definition at line 5079 of file regs.h.

#define PC6_CFG_MASK   (0x00000F00u)

Definition at line 5077 of file regs.h.

#define PC6_MASK   (0x00000040u)

Definition at line 5417 of file regs.h.

#define PC6_MASK   (0x00000040u)

Definition at line 5417 of file regs.h.

#define PC6_MASK   (0x00000040u)

Definition at line 5417 of file regs.h.

#define PC6_MASK   (0x00000040u)

Definition at line 5417 of file regs.h.

#define PC6_MASK   (0x00000040u)

Definition at line 5417 of file regs.h.

#define PC7   (0x00000080u)

Definition at line 5411 of file regs.h.

#define PC7   (0x00000080u)

Definition at line 5411 of file regs.h.

#define PC7   (0x00000080u)

Definition at line 5411 of file regs.h.

#define PC7   (0x00000080u)

Definition at line 5411 of file regs.h.

#define PC7   (0x00000080u)

Definition at line 5411 of file regs.h.

#define PC7_BIT   (7)

Definition at line 5413 of file regs.h.

#define PC7_BIT   (7)

Definition at line 5413 of file regs.h.

#define PC7_BIT   (7)

Definition at line 5413 of file regs.h.

#define PC7_BIT   (7)

Definition at line 5413 of file regs.h.

#define PC7_BIT   (7)

Definition at line 5413 of file regs.h.

#define PC7_BITS   (1)

Definition at line 5414 of file regs.h.

#define PC7_BITS   (1)

Definition at line 5414 of file regs.h.

#define PC7_BITS   (1)

Definition at line 5414 of file regs.h.

#define PC7_BITS   (1)

Definition at line 5414 of file regs.h.

#define PC7_BITS   (1)

Definition at line 5414 of file regs.h.

#define PC7_CFG   (0x0000F000u)

Definition at line 5071 of file regs.h.

#define PC7_CFG_BIT   (12)

Definition at line 5073 of file regs.h.

#define PC7_CFG_BITS   (4)

Definition at line 5074 of file regs.h.

#define PC7_CFG_MASK   (0x0000F000u)

Definition at line 5072 of file regs.h.

#define PC7_MASK   (0x00000080u)

Definition at line 5412 of file regs.h.

#define PC7_MASK   (0x00000080u)

Definition at line 5412 of file regs.h.

#define PC7_MASK   (0x00000080u)

Definition at line 5412 of file regs.h.

#define PC7_MASK   (0x00000080u)

Definition at line 5412 of file regs.h.

#define PC7_MASK   (0x00000080u)

Definition at line 5412 of file regs.h.

#define PCTRACE_SEL   *((volatile int32u *)0x40004028u)

Definition at line 2590 of file regs.h.

#define PCTRACE_SEL_ADDR   (0x40004028u)

Definition at line 2592 of file regs.h.

#define PCTRACE_SEL_FIELD   (0x00000001u)

Definition at line 2595 of file regs.h.

#define PCTRACE_SEL_FIELD_BIT   (0)

Definition at line 2597 of file regs.h.

#define PCTRACE_SEL_FIELD_BITS   (1)

Definition at line 2598 of file regs.h.

#define PCTRACE_SEL_FIELD_MASK   (0x00000001u)

Definition at line 2596 of file regs.h.

#define PCTRACE_SEL_REG   *((volatile int32u *)0x40004028u)

Definition at line 2591 of file regs.h.

#define PCTRACE_SEL_RESET   (0x00000000u)

Definition at line 2593 of file regs.h.

#define PD_DITHER_EN   *((volatile int32u *)0x40001048u)

Definition at line 620 of file regs.h.

#define PD_DITHER_EN_ADDR   (0x40001048u)

Definition at line 622 of file regs.h.

#define PD_DITHER_EN_PD_DITHER_EN   (0x00000001u)

Definition at line 625 of file regs.h.

#define PD_DITHER_EN_PD_DITHER_EN_BIT   (0)

Definition at line 627 of file regs.h.

#define PD_DITHER_EN_PD_DITHER_EN_BITS   (1)

Definition at line 628 of file regs.h.

#define PD_DITHER_EN_PD_DITHER_EN_MASK   (0x00000001u)

Definition at line 626 of file regs.h.

#define PD_DITHER_EN_REG   *((volatile int32u *)0x40001048u)

Definition at line 621 of file regs.h.

#define PD_DITHER_EN_RESET   (0x00000001u)

Definition at line 623 of file regs.h.

#define PREAMBLE_ABORT_THRESH   *((volatile int32u *)0x400010B4u)

Definition at line 1035 of file regs.h.

#define PREAMBLE_ABORT_THRESH_ADDR   (0x400010B4u)

Definition at line 1037 of file regs.h.

#define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH   (0x000000FFu)

Definition at line 1040 of file regs.h.

#define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_BIT   (0)

Definition at line 1042 of file regs.h.

#define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_BITS   (8)

Definition at line 1043 of file regs.h.

#define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_MASK   (0x000000FFu)

Definition at line 1041 of file regs.h.

#define PREAMBLE_ABORT_THRESH_REG   *((volatile int32u *)0x400010B4u)

Definition at line 1036 of file regs.h.

#define PREAMBLE_ABORT_THRESH_RESET   (0x00000071u)

Definition at line 1038 of file regs.h.

#define PREAMBLE_ACCEPT_WINDOW   *((volatile int32u *)0x400010B8u)

Definition at line 1045 of file regs.h.

#define PREAMBLE_ACCEPT_WINDOW_ADDR   (0x400010B8u)

Definition at line 1047 of file regs.h.

#define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW   (0x0000007Fu)

Definition at line 1050 of file regs.h.

#define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_BIT   (0)

Definition at line 1052 of file regs.h.

#define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_BITS   (7)

Definition at line 1053 of file regs.h.

#define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_MASK   (0x0000007Fu)

Definition at line 1051 of file regs.h.

#define PREAMBLE_ACCEPT_WINDOW_REG   *((volatile int32u *)0x400010B8u)

Definition at line 1046 of file regs.h.

#define PREAMBLE_ACCEPT_WINDOW_RESET   (0x00000003u)

Definition at line 1048 of file regs.h.

#define PREAMBLE_EVENT   *((volatile int32u *)0x400010B0u)

Definition at line 1020 of file regs.h.

#define PREAMBLE_EVENT_ADDR   (0x400010B0u)

Definition at line 1022 of file regs.h.

#define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH   (0x0000FF00u)

Definition at line 1025 of file regs.h.

#define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH_BIT   (8)

Definition at line 1027 of file regs.h.

#define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH_BITS   (8)

Definition at line 1028 of file regs.h.

#define PREAMBLE_EVENT_PREAMBLE_CONFIRM_THRESH_MASK   (0x0000FF00u)

Definition at line 1026 of file regs.h.

#define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH   (0x000000FFu)

Definition at line 1030 of file regs.h.

#define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_BIT   (0)

Definition at line 1032 of file regs.h.

#define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_BITS   (8)

Definition at line 1033 of file regs.h.

#define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_MASK   (0x000000FFu)

Definition at line 1031 of file regs.h.

#define PREAMBLE_EVENT_REG   *((volatile int32u *)0x400010B0u)

Definition at line 1021 of file regs.h.

#define PREAMBLE_EVENT_RESET   (0x00005877u)

Definition at line 1023 of file regs.h.

#define PRESCALE_CTRL   *((volatile int32u *)0x4000102Cu)

Definition at line 525 of file regs.h.

#define PRESCALE_CTRL_ADDR   (0x4000102Cu)

Definition at line 527 of file regs.h.

#define PRESCALE_CTRL_PRESCALE_SET   (0x00008000u)

Definition at line 530 of file regs.h.

#define PRESCALE_CTRL_PRESCALE_SET_BIT   (15)

Definition at line 532 of file regs.h.

#define PRESCALE_CTRL_PRESCALE_SET_BITS   (1)

Definition at line 533 of file regs.h.

#define PRESCALE_CTRL_PRESCALE_SET_MASK   (0x00008000u)

Definition at line 531 of file regs.h.

#define PRESCALE_CTRL_PRESCALE_VAL   (0x00000007u)

Definition at line 535 of file regs.h.

#define PRESCALE_CTRL_PRESCALE_VAL_BIT   (0)

Definition at line 537 of file regs.h.

#define PRESCALE_CTRL_PRESCALE_VAL_BITS   (3)

Definition at line 538 of file regs.h.

#define PRESCALE_CTRL_PRESCALE_VAL_MASK   (0x00000007u)

Definition at line 536 of file regs.h.

#define PRESCALE_CTRL_REG   *((volatile int32u *)0x4000102Cu)

Definition at line 526 of file regs.h.

#define PRESCALE_CTRL_RESET   (0x00000000u)

Definition at line 528 of file regs.h.

#define PT   *((volatile int32u *)0x40003028u)

Definition at line 2375 of file regs.h.

#define PT_ADDR   (0x40003028u)

Definition at line 2377 of file regs.h.

#define PT_PT   (0xFFFFFFFFu)

Definition at line 2380 of file regs.h.

#define PT_PT_BIT   (0)

Definition at line 2382 of file regs.h.

#define PT_PT_BITS   (32)

Definition at line 2383 of file regs.h.

#define PT_PT_MASK   (0xFFFFFFFFu)

Definition at line 2381 of file regs.h.

#define PT_REG   *((volatile int32u *)0x40003028u)

Definition at line 2376 of file regs.h.

#define PT_RESET   (0x00000000u)

Definition at line 2378 of file regs.h.

#define PWRUP_CDBGPWRUPREQ   (0x00000100u)

Definition at line 230 of file regs.h.

#define PWRUP_CDBGPWRUPREQ_BIT   (8)

Definition at line 232 of file regs.h.

#define PWRUP_CDBGPWRUPREQ_BITS   (1)

Definition at line 233 of file regs.h.

#define PWRUP_CDBGPWRUPREQ_MASK   (0x00000100u)

Definition at line 231 of file regs.h.

#define PWRUP_CSYSPWRUPREQ   (0x00000200u)

Definition at line 225 of file regs.h.

#define PWRUP_CSYSPWRUPREQ_BIT   (9)

Definition at line 227 of file regs.h.

#define PWRUP_CSYSPWRUPREQ_BITS   (1)

Definition at line 228 of file regs.h.

#define PWRUP_CSYSPWRUPREQ_MASK   (0x00000200u)

Definition at line 226 of file regs.h.

#define PWRUP_EVENT   *((volatile int32u *)0x40000028u)

Definition at line 220 of file regs.h.

#define PWRUP_EVENT_ADDR   (0x40000028u)

Definition at line 222 of file regs.h.

#define PWRUP_EVENT_REG   *((volatile int32u *)0x40000028u)

Definition at line 221 of file regs.h.

#define PWRUP_EVENT_RESET   (0x00000000u)

Definition at line 223 of file regs.h.

#define PWRUP_GPIO   (0x00000001u)

Definition at line 270 of file regs.h.

#define PWRUP_GPIO_BIT   (0)

Definition at line 272 of file regs.h.

#define PWRUP_GPIO_BITS   (1)

Definition at line 273 of file regs.h.

#define PWRUP_GPIO_MASK   (0x00000001u)

Definition at line 271 of file regs.h.

#define PWRUP_IRQD   (0x00000008u)

Definition at line 255 of file regs.h.

#define PWRUP_IRQD_BIT   (3)

Definition at line 257 of file regs.h.

#define PWRUP_IRQD_BITS   (1)

Definition at line 258 of file regs.h.

#define PWRUP_IRQD_MASK   (0x00000008u)

Definition at line 256 of file regs.h.

#define PWRUP_SC1   (0x00000002u)

Definition at line 265 of file regs.h.

#define PWRUP_SC1_BIT   (1)

Definition at line 267 of file regs.h.

#define PWRUP_SC1_BITS   (1)

Definition at line 268 of file regs.h.

#define PWRUP_SC1_MASK   (0x00000002u)

Definition at line 266 of file regs.h.

#define PWRUP_SC2   (0x00000004u)

Definition at line 260 of file regs.h.

#define PWRUP_SC2_BIT   (2)

Definition at line 262 of file regs.h.

#define PWRUP_SC2_BITS   (1)

Definition at line 263 of file regs.h.

#define PWRUP_SC2_MASK   (0x00000004u)

Definition at line 261 of file regs.h.

#define PWRUP_SLEEPTMRCOMPA   (0x00000010u)

Definition at line 250 of file regs.h.

#define PWRUP_SLEEPTMRCOMPA_BIT   (4)

Definition at line 252 of file regs.h.

#define PWRUP_SLEEPTMRCOMPA_BITS   (1)

Definition at line 253 of file regs.h.

#define PWRUP_SLEEPTMRCOMPA_MASK   (0x00000010u)

Definition at line 251 of file regs.h.

#define PWRUP_SLEEPTMRCOMPB   (0x00000020u)

Definition at line 245 of file regs.h.

#define PWRUP_SLEEPTMRCOMPB_BIT   (5)

Definition at line 247 of file regs.h.

#define PWRUP_SLEEPTMRCOMPB_BITS   (1)

Definition at line 248 of file regs.h.

#define PWRUP_SLEEPTMRCOMPB_MASK   (0x00000020u)

Definition at line 246 of file regs.h.

#define PWRUP_SLEEPTMRWRAP   (0x00000040u)

Definition at line 240 of file regs.h.

#define PWRUP_SLEEPTMRWRAP_BIT   (6)

Definition at line 242 of file regs.h.

#define PWRUP_SLEEPTMRWRAP_BITS   (1)

Definition at line 243 of file regs.h.

#define PWRUP_SLEEPTMRWRAP_MASK   (0x00000040u)

Definition at line 241 of file regs.h.

#define PWRUP_WAKECORE   (0x00000080u)

Definition at line 235 of file regs.h.

#define PWRUP_WAKECORE_BIT   (7)

Definition at line 237 of file regs.h.

#define PWRUP_WAKECORE_BITS   (1)

Definition at line 238 of file regs.h.

#define PWRUP_WAKECORE_MASK   (0x00000080u)

Definition at line 236 of file regs.h.

#define REGEN_DSLEEP   *((volatile int32u *)0x40000014u)

Definition at line 100 of file regs.h.

#define REGEN_DSLEEP_ADDR   (0x40000014u)

Definition at line 102 of file regs.h.

#define REGEN_DSLEEP_FIELD   (0x00000001u)

Definition at line 105 of file regs.h.

#define REGEN_DSLEEP_FIELD_BIT   (0)

Definition at line 107 of file regs.h.

#define REGEN_DSLEEP_FIELD_BITS   (1)

Definition at line 108 of file regs.h.

#define REGEN_DSLEEP_FIELD_MASK   (0x00000001u)

Definition at line 106 of file regs.h.

#define REGEN_DSLEEP_REG   *((volatile int32u *)0x40000014u)

Definition at line 101 of file regs.h.

#define REGEN_DSLEEP_RESET   (0x00000001u)

Definition at line 103 of file regs.h.

#define RESET_CPULOCKUP   (0x00000080u)

Definition at line 280 of file regs.h.

#define RESET_CPULOCKUP_BIT   (7)

Definition at line 282 of file regs.h.

#define RESET_CPULOCKUP_BITS   (1)

Definition at line 283 of file regs.h.

#define RESET_CPULOCKUP_MASK   (0x00000080u)

Definition at line 281 of file regs.h.

#define RESET_DSLEEP   (0x00000020u)

Definition at line 290 of file regs.h.

#define RESET_DSLEEP_BIT   (5)

Definition at line 292 of file regs.h.

#define RESET_DSLEEP_BITS   (1)

Definition at line 293 of file regs.h.

#define RESET_DSLEEP_MASK   (0x00000020u)

Definition at line 291 of file regs.h.

#define RESET_EVENT   *((volatile int32u *)0x4000002Cu)

Definition at line 275 of file regs.h.

#define RESET_EVENT_ADDR   (0x4000002Cu)

Definition at line 277 of file regs.h.

#define RESET_EVENT_REG   *((volatile int32u *)0x4000002Cu)

Definition at line 276 of file regs.h.

#define RESET_EVENT_RESET   (0x00000001u)

Definition at line 278 of file regs.h.

#define RESET_NRESET   (0x00000004u)

Definition at line 305 of file regs.h.

#define RESET_NRESET_BIT   (2)

Definition at line 307 of file regs.h.

#define RESET_NRESET_BITS   (1)

Definition at line 308 of file regs.h.

#define RESET_NRESET_MASK   (0x00000004u)

Definition at line 306 of file regs.h.

#define RESET_OPTBYTEFAIL   (0x00000040u)

Definition at line 285 of file regs.h.

#define RESET_OPTBYTEFAIL_BIT   (6)

Definition at line 287 of file regs.h.

#define RESET_OPTBYTEFAIL_BITS   (1)

Definition at line 288 of file regs.h.

#define RESET_OPTBYTEFAIL_MASK   (0x00000040u)

Definition at line 286 of file regs.h.

#define RESET_PWRHV   (0x00000001u)

Definition at line 315 of file regs.h.

#define RESET_PWRHV_BIT   (0)

Definition at line 317 of file regs.h.

#define RESET_PWRHV_BITS   (1)

Definition at line 318 of file regs.h.

#define RESET_PWRHV_MASK   (0x00000001u)

Definition at line 316 of file regs.h.

#define RESET_PWRLV   (0x00000002u)

Definition at line 310 of file regs.h.

#define RESET_PWRLV_BIT   (1)

Definition at line 312 of file regs.h.

#define RESET_PWRLV_BITS   (1)

Definition at line 313 of file regs.h.

#define RESET_PWRLV_MASK   (0x00000002u)

Definition at line 311 of file regs.h.

#define RESET_SW   (0x00000010u)

Definition at line 295 of file regs.h.

#define RESET_SW_BIT   (4)

Definition at line 297 of file regs.h.

#define RESET_SW_BITS   (1)

Definition at line 298 of file regs.h.

#define RESET_SW_MASK   (0x00000010u)

Definition at line 296 of file regs.h.

#define RESET_WDOG   (0x00000008u)

Definition at line 300 of file regs.h.

#define RESET_WDOG_BIT   (3)

Definition at line 302 of file regs.h.

#define RESET_WDOG_BITS   (1)

Definition at line 303 of file regs.h.

#define RESET_WDOG_MASK   (0x00000008u)

Definition at line 301 of file regs.h.

#define ROM_CID0   *((volatile int32u *)0xE00FFFF0u)

Definition at line 11495 of file regs.h.

#define ROM_CID0_ADDR   (0xE00FFFF0u)

Definition at line 11497 of file regs.h.

#define ROM_CID0_CID   (0x000000FFu)

Definition at line 11500 of file regs.h.

#define ROM_CID0_CID_BIT   (0)

Definition at line 11502 of file regs.h.

#define ROM_CID0_CID_BITS   (8)

Definition at line 11503 of file regs.h.

#define ROM_CID0_CID_MASK   (0x000000FFu)

Definition at line 11501 of file regs.h.

#define ROM_CID0_REG   *((volatile int32u *)0xE00FFFF0u)

Definition at line 11496 of file regs.h.

#define ROM_CID0_RESET   (0x0000000Du)

Definition at line 11498 of file regs.h.

#define ROM_CID1   *((volatile int32u *)0xE00FFFF4u)

Definition at line 11505 of file regs.h.

#define ROM_CID1_ADDR   (0xE00FFFF4u)

Definition at line 11507 of file regs.h.

#define ROM_CID1_CID   (0x000000FFu)

Definition at line 11510 of file regs.h.

#define ROM_CID1_CID_BIT   (0)

Definition at line 11512 of file regs.h.

#define ROM_CID1_CID_BITS   (8)

Definition at line 11513 of file regs.h.

#define ROM_CID1_CID_MASK   (0x000000FFu)

Definition at line 11511 of file regs.h.

#define ROM_CID1_REG   *((volatile int32u *)0xE00FFFF4u)

Definition at line 11506 of file regs.h.

#define ROM_CID1_RESET   (0x00000010u)

Definition at line 11508 of file regs.h.

#define ROM_CID2   *((volatile int32u *)0xE00FFFF8u)

Definition at line 11515 of file regs.h.

#define ROM_CID2_ADDR   (0xE00FFFF8u)

Definition at line 11517 of file regs.h.

#define ROM_CID2_CID   (0x000000FFu)

Definition at line 11520 of file regs.h.

#define ROM_CID2_CID_BIT   (0)

Definition at line 11522 of file regs.h.

#define ROM_CID2_CID_BITS   (8)

Definition at line 11523 of file regs.h.

#define ROM_CID2_CID_MASK   (0x000000FFu)

Definition at line 11521 of file regs.h.

#define ROM_CID2_REG   *((volatile int32u *)0xE00FFFF8u)

Definition at line 11516 of file regs.h.

#define ROM_CID2_RESET   (0x00000005u)

Definition at line 11518 of file regs.h.

#define ROM_CID3   *((volatile int32u *)0xE00FFFFCu)

Definition at line 11525 of file regs.h.

#define ROM_CID3_ADDR   (0xE00FFFFCu)

Definition at line 11527 of file regs.h.

#define ROM_CID3_CID   (0x000000FFu)

Definition at line 11530 of file regs.h.

#define ROM_CID3_CID_BIT   (0)

Definition at line 11532 of file regs.h.

#define ROM_CID3_CID_BITS   (8)

Definition at line 11533 of file regs.h.

#define ROM_CID3_CID_MASK   (0x000000FFu)

Definition at line 11531 of file regs.h.

#define ROM_CID3_REG   *((volatile int32u *)0xE00FFFFCu)

Definition at line 11526 of file regs.h.

#define ROM_CID3_RESET   (0x000000B1u)

Definition at line 11528 of file regs.h.

#define ROM_DWT   *((volatile int32u *)0xE00FF004u)

Definition at line 11295 of file regs.h.

#define ROM_DWT_ADDR   (0xE00FF004u)

Definition at line 11297 of file regs.h.

#define ROM_DWT_ADDR_OFF   (0xFFFFF000u)

Definition at line 11300 of file regs.h.

#define ROM_DWT_ADDR_OFF_BIT   (12)

Definition at line 11302 of file regs.h.

#define ROM_DWT_ADDR_OFF_BITS   (20)

Definition at line 11303 of file regs.h.

#define ROM_DWT_ADDR_OFF_MASK   (0xFFFFF000u)

Definition at line 11301 of file regs.h.

#define ROM_DWT_ENTRY_PRES   (0x00000001u)

Definition at line 11310 of file regs.h.

#define ROM_DWT_ENTRY_PRES_BIT   (0)

Definition at line 11312 of file regs.h.

#define ROM_DWT_ENTRY_PRES_BITS   (1)

Definition at line 11313 of file regs.h.

#define ROM_DWT_ENTRY_PRES_MASK   (0x00000001u)

Definition at line 11311 of file regs.h.

#define ROM_DWT_FORMAT   (0x00000002u)

Definition at line 11305 of file regs.h.

#define ROM_DWT_FORMAT_BIT   (1)

Definition at line 11307 of file regs.h.

#define ROM_DWT_FORMAT_BITS   (1)

Definition at line 11308 of file regs.h.

#define ROM_DWT_FORMAT_MASK   (0x00000002u)

Definition at line 11306 of file regs.h.

#define ROM_DWT_REG   *((volatile int32u *)0xE00FF004u)

Definition at line 11296 of file regs.h.

#define ROM_DWT_RESET   (0xFFF02003u)

Definition at line 11298 of file regs.h.

#define ROM_END   *((volatile int32u *)0xE00FF018u)

Definition at line 11395 of file regs.h.

#define ROM_END_ADDR   (0xE00FF018u)

Definition at line 11397 of file regs.h.

#define ROM_END_END   (0xFFFFFFFFu)

Definition at line 11400 of file regs.h.

#define ROM_END_END_BIT   (0)

Definition at line 11402 of file regs.h.

#define ROM_END_END_BITS   (32)

Definition at line 11403 of file regs.h.

#define ROM_END_END_MASK   (0xFFFFFFFFu)

Definition at line 11401 of file regs.h.

#define ROM_END_REG   *((volatile int32u *)0xE00FF018u)

Definition at line 11396 of file regs.h.

#define ROM_END_RESET   (0x00000000u)

Definition at line 11398 of file regs.h.

#define ROM_ETM   *((volatile int32u *)0xE00FF014u)

Definition at line 11375 of file regs.h.

#define ROM_ETM_ADDR   (0xE00FF014u)

Definition at line 11377 of file regs.h.

#define ROM_ETM_ADDR_OFF   (0xFFFFF000u)

Definition at line 11380 of file regs.h.

#define ROM_ETM_ADDR_OFF_BIT   (12)

Definition at line 11382 of file regs.h.

#define ROM_ETM_ADDR_OFF_BITS   (20)

Definition at line 11383 of file regs.h.

#define ROM_ETM_ADDR_OFF_MASK   (0xFFFFF000u)

Definition at line 11381 of file regs.h.

#define ROM_ETM_ENTRY_PRES   (0x00000001u)

Definition at line 11390 of file regs.h.

#define ROM_ETM_ENTRY_PRES_BIT   (0)

Definition at line 11392 of file regs.h.

#define ROM_ETM_ENTRY_PRES_BITS   (1)

Definition at line 11393 of file regs.h.

#define ROM_ETM_ENTRY_PRES_MASK   (0x00000001u)

Definition at line 11391 of file regs.h.

#define ROM_ETM_FORMAT   (0x00000002u)

Definition at line 11385 of file regs.h.

#define ROM_ETM_FORMAT_BIT   (1)

Definition at line 11387 of file regs.h.

#define ROM_ETM_FORMAT_BITS   (1)

Definition at line 11388 of file regs.h.

#define ROM_ETM_FORMAT_MASK   (0x00000002u)

Definition at line 11386 of file regs.h.

#define ROM_ETM_REG   *((volatile int32u *)0xE00FF014u)

Definition at line 11376 of file regs.h.

#define ROM_ETM_RESET   (0xFFF0F002u)

Definition at line 11378 of file regs.h.

#define ROM_FPB   *((volatile int32u *)0xE00FF008u)

Definition at line 11315 of file regs.h.

#define ROM_FPB_ADDR   (0xE00FF008u)

Definition at line 11317 of file regs.h.

#define ROM_FPB_ADDR_OFF   (0xFFFFF000u)

Definition at line 11320 of file regs.h.

#define ROM_FPB_ADDR_OFF_BIT   (12)

Definition at line 11322 of file regs.h.

#define ROM_FPB_ADDR_OFF_BITS   (20)

Definition at line 11323 of file regs.h.

#define ROM_FPB_ADDR_OFF_MASK   (0xFFFFF000u)

Definition at line 11321 of file regs.h.

#define ROM_FPB_ENTRY_PRES   (0x00000001u)

Definition at line 11330 of file regs.h.

#define ROM_FPB_ENTRY_PRES_BIT   (0)

Definition at line 11332 of file regs.h.

#define ROM_FPB_ENTRY_PRES_BITS   (1)

Definition at line 11333 of file regs.h.

#define ROM_FPB_ENTRY_PRES_MASK   (0x00000001u)

Definition at line 11331 of file regs.h.

#define ROM_FPB_FORMAT   (0x00000002u)

Definition at line 11325 of file regs.h.

#define ROM_FPB_FORMAT_BIT   (1)

Definition at line 11327 of file regs.h.

#define ROM_FPB_FORMAT_BITS   (1)

Definition at line 11328 of file regs.h.

#define ROM_FPB_FORMAT_MASK   (0x00000002u)

Definition at line 11326 of file regs.h.

#define ROM_FPB_REG   *((volatile int32u *)0xE00FF008u)

Definition at line 11316 of file regs.h.

#define ROM_FPB_RESET   (0xFFF03003u)

Definition at line 11318 of file regs.h.

#define ROM_ITM   *((volatile int32u *)0xE00FF00Cu)

Definition at line 11335 of file regs.h.

#define ROM_ITM_ADDR   (0xE00FF00Cu)

Definition at line 11337 of file regs.h.

#define ROM_ITM_ADDR_OFF   (0xFFFFF000u)

Definition at line 11340 of file regs.h.

#define ROM_ITM_ADDR_OFF_BIT   (12)

Definition at line 11342 of file regs.h.

#define ROM_ITM_ADDR_OFF_BITS   (20)

Definition at line 11343 of file regs.h.

#define ROM_ITM_ADDR_OFF_MASK   (0xFFFFF000u)

Definition at line 11341 of file regs.h.

#define ROM_ITM_ENTRY_PRES   (0x00000001u)

Definition at line 11350 of file regs.h.

#define ROM_ITM_ENTRY_PRES_BIT   (0)

Definition at line 11352 of file regs.h.

#define ROM_ITM_ENTRY_PRES_BITS   (1)

Definition at line 11353 of file regs.h.

#define ROM_ITM_ENTRY_PRES_MASK   (0x00000001u)

Definition at line 11351 of file regs.h.

#define ROM_ITM_FORMAT   (0x00000002u)

Definition at line 11345 of file regs.h.

#define ROM_ITM_FORMAT_BIT   (1)

Definition at line 11347 of file regs.h.

#define ROM_ITM_FORMAT_BITS   (1)

Definition at line 11348 of file regs.h.

#define ROM_ITM_FORMAT_MASK   (0x00000002u)

Definition at line 11346 of file regs.h.

#define ROM_ITM_REG   *((volatile int32u *)0xE00FF00Cu)

Definition at line 11336 of file regs.h.

#define ROM_ITM_RESET   (0xFFF01003u)

Definition at line 11338 of file regs.h.

#define ROM_MEMTYPE   *((volatile int32u *)0xE00FFFCCu)

Definition at line 11405 of file regs.h.

#define ROM_MEMTYPE_ADDR   (0xE00FFFCCu)

Definition at line 11407 of file regs.h.

#define ROM_MEMTYPE_MEMTYPE   (0x00000001u)

Definition at line 11410 of file regs.h.

#define ROM_MEMTYPE_MEMTYPE_BIT   (0)

Definition at line 11412 of file regs.h.

#define ROM_MEMTYPE_MEMTYPE_BITS   (1)

Definition at line 11413 of file regs.h.

#define ROM_MEMTYPE_MEMTYPE_MASK   (0x00000001u)

Definition at line 11411 of file regs.h.

#define ROM_MEMTYPE_REG   *((volatile int32u *)0xE00FFFCCu)

Definition at line 11406 of file regs.h.

#define ROM_MEMTYPE_RESET   (0x00000001u)

Definition at line 11408 of file regs.h.

#define ROM_PID0   *((volatile int32u *)0xE00FFFE0u)

Definition at line 11455 of file regs.h.

#define ROM_PID0_ADDR   (0xE00FFFE0u)

Definition at line 11457 of file regs.h.

#define ROM_PID0_PID   (0x0000000Fu)

Definition at line 11460 of file regs.h.

#define ROM_PID0_PID_BIT   (0)

Definition at line 11462 of file regs.h.

#define ROM_PID0_PID_BITS   (4)

Definition at line 11463 of file regs.h.

#define ROM_PID0_PID_MASK   (0x0000000Fu)

Definition at line 11461 of file regs.h.

#define ROM_PID0_REG   *((volatile int32u *)0xE00FFFE0u)

Definition at line 11456 of file regs.h.

#define ROM_PID0_RESET   (0x00000000u)

Definition at line 11458 of file regs.h.

#define ROM_PID1   *((volatile int32u *)0xE00FFFE4u)

Definition at line 11465 of file regs.h.

#define ROM_PID1_ADDR   (0xE00FFFE4u)

Definition at line 11467 of file regs.h.

#define ROM_PID1_PID   (0x0000000Fu)

Definition at line 11470 of file regs.h.

#define ROM_PID1_PID_BIT   (0)

Definition at line 11472 of file regs.h.

#define ROM_PID1_PID_BITS   (4)

Definition at line 11473 of file regs.h.

#define ROM_PID1_PID_MASK   (0x0000000Fu)

Definition at line 11471 of file regs.h.

#define ROM_PID1_REG   *((volatile int32u *)0xE00FFFE4u)

Definition at line 11466 of file regs.h.

#define ROM_PID1_RESET   (0x00000000u)

Definition at line 11468 of file regs.h.

#define ROM_PID2   *((volatile int32u *)0xE00FFFE8u)

Definition at line 11475 of file regs.h.

#define ROM_PID2_ADDR   (0xE00FFFE8u)

Definition at line 11477 of file regs.h.

#define ROM_PID2_PID   (0x0000000Fu)

Definition at line 11480 of file regs.h.

#define ROM_PID2_PID_BIT   (0)

Definition at line 11482 of file regs.h.

#define ROM_PID2_PID_BITS   (4)

Definition at line 11483 of file regs.h.

#define ROM_PID2_PID_MASK   (0x0000000Fu)

Definition at line 11481 of file regs.h.

#define ROM_PID2_REG   *((volatile int32u *)0xE00FFFE8u)

Definition at line 11476 of file regs.h.

#define ROM_PID2_RESET   (0x00000000u)

Definition at line 11478 of file regs.h.

#define ROM_PID3   *((volatile int32u *)0xE00FFFECu)

Definition at line 11485 of file regs.h.

#define ROM_PID3_ADDR   (0xE00FFFECu)

Definition at line 11487 of file regs.h.

#define ROM_PID3_PID   (0x0000000Fu)

Definition at line 11490 of file regs.h.

#define ROM_PID3_PID_BIT   (0)

Definition at line 11492 of file regs.h.

#define ROM_PID3_PID_BITS   (4)

Definition at line 11493 of file regs.h.

#define ROM_PID3_PID_MASK   (0x0000000Fu)

Definition at line 11491 of file regs.h.

#define ROM_PID3_REG   *((volatile int32u *)0xE00FFFECu)

Definition at line 11486 of file regs.h.

#define ROM_PID3_RESET   (0x00000000u)

Definition at line 11488 of file regs.h.

#define ROM_PID4   *((volatile int32u *)0xE00FFFD0u)

Definition at line 11415 of file regs.h.

#define ROM_PID4_ADDR   (0xE00FFFD0u)

Definition at line 11417 of file regs.h.

#define ROM_PID4_PID   (0x0000000Fu)

Definition at line 11420 of file regs.h.

#define ROM_PID4_PID_BIT   (0)

Definition at line 11422 of file regs.h.

#define ROM_PID4_PID_BITS   (4)

Definition at line 11423 of file regs.h.

#define ROM_PID4_PID_MASK   (0x0000000Fu)

Definition at line 11421 of file regs.h.

#define ROM_PID4_REG   *((volatile int32u *)0xE00FFFD0u)

Definition at line 11416 of file regs.h.

#define ROM_PID4_RESET   (0x00000000u)

Definition at line 11418 of file regs.h.

#define ROM_PID5   *((volatile int32u *)0xE00FFFD4u)

Definition at line 11425 of file regs.h.

#define ROM_PID5_ADDR   (0xE00FFFD4u)

Definition at line 11427 of file regs.h.

#define ROM_PID5_PID   (0x0000000Fu)

Definition at line 11430 of file regs.h.

#define ROM_PID5_PID_BIT   (0)

Definition at line 11432 of file regs.h.

#define ROM_PID5_PID_BITS   (4)

Definition at line 11433 of file regs.h.

#define ROM_PID5_PID_MASK   (0x0000000Fu)

Definition at line 11431 of file regs.h.

#define ROM_PID5_REG   *((volatile int32u *)0xE00FFFD4u)

Definition at line 11426 of file regs.h.

#define ROM_PID5_RESET   (0x00000000u)

Definition at line 11428 of file regs.h.

#define ROM_PID6   *((volatile int32u *)0xE00FFFD8u)

Definition at line 11435 of file regs.h.

#define ROM_PID6_ADDR   (0xE00FFFD8u)

Definition at line 11437 of file regs.h.

#define ROM_PID6_PID   (0x0000000Fu)

Definition at line 11440 of file regs.h.

#define ROM_PID6_PID_BIT   (0)

Definition at line 11442 of file regs.h.

#define ROM_PID6_PID_BITS   (4)

Definition at line 11443 of file regs.h.

#define ROM_PID6_PID_MASK   (0x0000000Fu)

Definition at line 11441 of file regs.h.

#define ROM_PID6_REG   *((volatile int32u *)0xE00FFFD8u)

Definition at line 11436 of file regs.h.

#define ROM_PID6_RESET   (0x00000000u)

Definition at line 11438 of file regs.h.

#define ROM_PID7   *((volatile int32u *)0xE00FFFDCu)

Definition at line 11445 of file regs.h.

#define ROM_PID7_ADDR   (0xE00FFFDCu)

Definition at line 11447 of file regs.h.

#define ROM_PID7_PID   (0x0000000Fu)

Definition at line 11450 of file regs.h.

#define ROM_PID7_PID_BIT   (0)

Definition at line 11452 of file regs.h.

#define ROM_PID7_PID_BITS   (4)

Definition at line 11453 of file regs.h.

#define ROM_PID7_PID_MASK   (0x0000000Fu)

Definition at line 11451 of file regs.h.

#define ROM_PID7_REG   *((volatile int32u *)0xE00FFFDCu)

Definition at line 11446 of file regs.h.

#define ROM_PID7_RESET   (0x00000000u)

Definition at line 11448 of file regs.h.

#define ROM_SCS   *((volatile int32u *)0xE00FF000u)

Definition at line 11275 of file regs.h.

#define ROM_SCS_ADDR   (0xE00FF000u)

Definition at line 11277 of file regs.h.

#define ROM_SCS_ADDR_OFF   (0xFFFFF000u)

Definition at line 11280 of file regs.h.

#define ROM_SCS_ADDR_OFF_BIT   (12)

Definition at line 11282 of file regs.h.

#define ROM_SCS_ADDR_OFF_BITS   (20)

Definition at line 11283 of file regs.h.

#define ROM_SCS_ADDR_OFF_MASK   (0xFFFFF000u)

Definition at line 11281 of file regs.h.

#define ROM_SCS_ENTRY_PRES   (0x00000001u)

Definition at line 11290 of file regs.h.

#define ROM_SCS_ENTRY_PRES_BIT   (0)

Definition at line 11292 of file regs.h.

#define ROM_SCS_ENTRY_PRES_BITS   (1)

Definition at line 11293 of file regs.h.

#define ROM_SCS_ENTRY_PRES_MASK   (0x00000001u)

Definition at line 11291 of file regs.h.

#define ROM_SCS_FORMAT   (0x00000002u)

Definition at line 11285 of file regs.h.

#define ROM_SCS_FORMAT_BIT   (1)

Definition at line 11287 of file regs.h.

#define ROM_SCS_FORMAT_BITS   (1)

Definition at line 11288 of file regs.h.

#define ROM_SCS_FORMAT_MASK   (0x00000002u)

Definition at line 11286 of file regs.h.

#define ROM_SCS_REG   *((volatile int32u *)0xE00FF000u)

Definition at line 11276 of file regs.h.

#define ROM_SCS_RESET   (0xFFF0F003u)

Definition at line 11278 of file regs.h.

#define ROM_TPIU   *((volatile int32u *)0xE00FF010u)

Definition at line 11355 of file regs.h.

#define ROM_TPIU_ADDR   (0xE00FF010u)

Definition at line 11357 of file regs.h.

#define ROM_TPIU_ADDR_OFF   (0xFFFFF000u)

Definition at line 11360 of file regs.h.

#define ROM_TPIU_ADDR_OFF_BIT   (12)

Definition at line 11362 of file regs.h.

#define ROM_TPIU_ADDR_OFF_BITS   (20)

Definition at line 11363 of file regs.h.

#define ROM_TPIU_ADDR_OFF_MASK   (0xFFFFF000u)

Definition at line 11361 of file regs.h.

#define ROM_TPIU_ENTRY_PRES   (0x00000001u)

Definition at line 11370 of file regs.h.

#define ROM_TPIU_ENTRY_PRES_BIT   (0)

Definition at line 11372 of file regs.h.

#define ROM_TPIU_ENTRY_PRES_BITS   (1)

Definition at line 11373 of file regs.h.

#define ROM_TPIU_ENTRY_PRES_MASK   (0x00000001u)

Definition at line 11371 of file regs.h.

#define ROM_TPIU_FORMAT   (0x00000002u)

Definition at line 11365 of file regs.h.

#define ROM_TPIU_FORMAT_BIT   (1)

Definition at line 11367 of file regs.h.

#define ROM_TPIU_FORMAT_BITS   (1)

Definition at line 11368 of file regs.h.

#define ROM_TPIU_FORMAT_MASK   (0x00000002u)

Definition at line 11366 of file regs.h.

#define ROM_TPIU_REG   *((volatile int32u *)0xE00FF010u)

Definition at line 11356 of file regs.h.

#define ROM_TPIU_RESET   (0xFFF0F003u)

Definition at line 11358 of file regs.h.

#define RSSI_INST   *((volatile int32u *)0x400010CCu)

Definition at line 1100 of file regs.h.

#define RSSI_INST_ADDR   (0x400010CCu)

Definition at line 1102 of file regs.h.

#define RSSI_INST_NEW_RSSI_INST   (0x00000200u)

Definition at line 1105 of file regs.h.

#define RSSI_INST_NEW_RSSI_INST_BIT   (9)

Definition at line 1107 of file regs.h.

#define RSSI_INST_NEW_RSSI_INST_BITS   (1)

Definition at line 1108 of file regs.h.

#define RSSI_INST_NEW_RSSI_INST_MASK   (0x00000200u)

Definition at line 1106 of file regs.h.

#define RSSI_INST_REG   *((volatile int32u *)0x400010CCu)

Definition at line 1101 of file regs.h.

#define RSSI_INST_RESET   (0x00000000u)

Definition at line 1103 of file regs.h.

#define RSSI_INST_RSSI_INST   (0x000001FFu)

Definition at line 1110 of file regs.h.

#define RSSI_INST_RSSI_INST_BIT   (0)

Definition at line 1112 of file regs.h.

#define RSSI_INST_RSSI_INST_BITS   (9)

Definition at line 1113 of file regs.h.

#define RSSI_INST_RSSI_INST_MASK   (0x000001FFu)

Definition at line 1111 of file regs.h.

#define RSSI_PKT   *((volatile int32u *)0x40001010u)

Definition at line 435 of file regs.h.

#define RSSI_PKT_ADDR   (0x40001010u)

Definition at line 437 of file regs.h.

#define RSSI_PKT_REG   *((volatile int32u *)0x40001010u)

Definition at line 436 of file regs.h.

#define RSSI_PKT_RESET   (0x00000000u)

Definition at line 438 of file regs.h.

#define RSSI_PKT_RSSI_PKT   (0x000000FFu)

Definition at line 440 of file regs.h.

#define RSSI_PKT_RSSI_PKT_BIT   (0)

Definition at line 442 of file regs.h.

#define RSSI_PKT_RSSI_PKT_BITS   (8)

Definition at line 443 of file regs.h.

#define RSSI_PKT_RSSI_PKT_MASK   (0x000000FFu)

Definition at line 441 of file regs.h.

#define RSSI_ROLLING   *((volatile int32u *)0x4000100Cu)

Definition at line 425 of file regs.h.

#define RSSI_ROLLING_ADDR   (0x4000100Cu)

Definition at line 427 of file regs.h.

#define RSSI_ROLLING_REG   *((volatile int32u *)0x4000100Cu)

Definition at line 426 of file regs.h.

#define RSSI_ROLLING_RESET   (0x00000000u)

Definition at line 428 of file regs.h.

#define RSSI_ROLLING_RSSI_ROLLING   (0x00003FFFu)

Definition at line 430 of file regs.h.

#define RSSI_ROLLING_RSSI_ROLLING_BIT   (0)

Definition at line 432 of file regs.h.

#define RSSI_ROLLING_RSSI_ROLLING_BITS   (14)

Definition at line 433 of file regs.h.

#define RSSI_ROLLING_RSSI_ROLLING_MASK   (0x00003FFFu)

Definition at line 431 of file regs.h.

#define RSSI_THRESH   *((volatile int32u *)0x40001054u)

Definition at line 665 of file regs.h.

#define RSSI_THRESH_ADDR   (0x40001054u)

Definition at line 667 of file regs.h.

#define RSSI_THRESH_REG   *((volatile int32u *)0x40001054u)

Definition at line 666 of file regs.h.

#define RSSI_THRESH_RESET   (0x00000100u)

Definition at line 668 of file regs.h.

#define RSSI_THRESH_RSSI_THRESH   (0x0000FFFFu)

Definition at line 670 of file regs.h.

#define RSSI_THRESH_RSSI_THRESH_BIT   (0)

Definition at line 672 of file regs.h.

#define RSSI_THRESH_RSSI_THRESH_BITS   (16)

Definition at line 673 of file regs.h.

#define RSSI_THRESH_RSSI_THRESH_MASK   (0x0000FFFFu)

Definition at line 671 of file regs.h.

#define RX_A_COUNT   *((volatile int32u *)0x40002020u)

Definition at line 1575 of file regs.h.

#define RX_A_COUNT_ADDR   (0x40002020u)

Definition at line 1577 of file regs.h.

#define RX_A_COUNT_REG   *((volatile int32u *)0x40002020u)

Definition at line 1576 of file regs.h.

#define RX_A_COUNT_RESET   (0x00000000u)

Definition at line 1578 of file regs.h.

#define RX_A_COUNT_RX_A_COUNT   (0x000007FFu)

Definition at line 1580 of file regs.h.

#define RX_A_COUNT_RX_A_COUNT_BIT   (0)

Definition at line 1582 of file regs.h.

#define RX_A_COUNT_RX_A_COUNT_BITS   (11)

Definition at line 1583 of file regs.h.

#define RX_A_COUNT_RX_A_COUNT_MASK   (0x000007FFu)

Definition at line 1581 of file regs.h.

#define RX_ADC   *((volatile int32u *)0x40001014u)

Definition at line 445 of file regs.h.

#define RX_ADC_ADDR   (0x40001014u)

Definition at line 447 of file regs.h.

#define RX_ADC_REG   *((volatile int32u *)0x40001014u)

Definition at line 446 of file regs.h.

#define RX_ADC_RESET   (0x00000024u)

Definition at line 448 of file regs.h.

#define RX_ADC_RX_ADC   (0x0000007Fu)

Definition at line 450 of file regs.h.

#define RX_ADC_RX_ADC_BIT   (0)

Definition at line 452 of file regs.h.

#define RX_ADC_RX_ADC_BITS   (7)

Definition at line 453 of file regs.h.

#define RX_ADC_RX_ADC_MASK   (0x0000007Fu)

Definition at line 451 of file regs.h.

#define RX_B_COUNT   *((volatile int32u *)0x40002024u)

Definition at line 1585 of file regs.h.

#define RX_B_COUNT_ADDR   (0x40002024u)

Definition at line 1587 of file regs.h.

#define RX_B_COUNT_REG   *((volatile int32u *)0x40002024u)

Definition at line 1586 of file regs.h.

#define RX_B_COUNT_RESET   (0x00000000u)

Definition at line 1588 of file regs.h.

#define RX_B_COUNT_RX_B_COUNT   (0x000007FFu)

Definition at line 1590 of file regs.h.

#define RX_B_COUNT_RX_B_COUNT_BIT   (0)

Definition at line 1592 of file regs.h.

#define RX_B_COUNT_RX_B_COUNT_BITS   (11)

Definition at line 1593 of file regs.h.

#define RX_B_COUNT_RX_B_COUNT_MASK   (0x000007FFu)

Definition at line 1591 of file regs.h.

#define RX_CRC   *((volatile int32u *)0x40002070u)

Definition at line 1870 of file regs.h.

#define RX_CRC_ADDR   (0x40002070u)

Definition at line 1872 of file regs.h.

#define RX_CRC_REG   *((volatile int32u *)0x40002070u)

Definition at line 1871 of file regs.h.

#define RX_CRC_RESET   (0x00000000u)

Definition at line 1873 of file regs.h.

#define RX_CRC_RX_CRC   (0x0000FFFFu)

Definition at line 1875 of file regs.h.

#define RX_CRC_RX_CRC_BIT   (0)

Definition at line 1877 of file regs.h.

#define RX_CRC_RX_CRC_BITS   (16)

Definition at line 1878 of file regs.h.

#define RX_CRC_RX_CRC_MASK   (0x0000FFFFu)

Definition at line 1876 of file regs.h.

#define RX_ERR_THRESH   *((volatile int32u *)0x4000104Cu)

Definition at line 630 of file regs.h.

#define RX_ERR_THRESH_ADDR   (0x4000104Cu)

Definition at line 632 of file regs.h.

#define RX_ERR_THRESH_LPF_RX_ERR_COEFF   (0x0000E000u)

Definition at line 635 of file regs.h.

#define RX_ERR_THRESH_LPF_RX_ERR_COEFF_BIT   (13)

Definition at line 637 of file regs.h.

#define RX_ERR_THRESH_LPF_RX_ERR_COEFF_BITS   (3)

Definition at line 638 of file regs.h.

#define RX_ERR_THRESH_LPF_RX_ERR_COEFF_MASK   (0x0000E000u)

Definition at line 636 of file regs.h.

#define RX_ERR_THRESH_LPF_RX_ERR_THRESH   (0x00001F00u)

Definition at line 640 of file regs.h.

#define RX_ERR_THRESH_LPF_RX_ERR_THRESH_BIT   (8)

Definition at line 642 of file regs.h.

#define RX_ERR_THRESH_LPF_RX_ERR_THRESH_BITS   (5)

Definition at line 643 of file regs.h.

#define RX_ERR_THRESH_LPF_RX_ERR_THRESH_MASK   (0x00001F00u)

Definition at line 641 of file regs.h.

#define RX_ERR_THRESH_REG   *((volatile int32u *)0x4000104Cu)

Definition at line 631 of file regs.h.

#define RX_ERR_THRESH_RESET   (0x00004608u)

Definition at line 633 of file regs.h.

#define RX_ERR_THRESH_RX_ERR_THRESH   (0x0000001Fu)

Definition at line 645 of file regs.h.

#define RX_ERR_THRESH_RX_ERR_THRESH_BIT   (0)

Definition at line 647 of file regs.h.

#define RX_ERR_THRESH_RX_ERR_THRESH_BITS   (5)

Definition at line 648 of file regs.h.

#define RX_ERR_THRESH_RX_ERR_THRESH_MASK   (0x0000001Fu)

Definition at line 646 of file regs.h.

#define RX_GAIN_CTRL   *((volatile int32u *)0x40001044u)

Definition at line 590 of file regs.h.

#define RX_GAIN_CTRL_ADDR   (0x40001044u)

Definition at line 592 of file regs.h.

#define RX_GAIN_CTRL_REG   *((volatile int32u *)0x40001044u)

Definition at line 591 of file regs.h.

#define RX_GAIN_CTRL_RESET   (0x00000000u)

Definition at line 593 of file regs.h.

#define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST   (0x00000030u)

Definition at line 610 of file regs.h.

#define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST_BIT   (4)

Definition at line 612 of file regs.h.

#define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST_BITS   (2)

Definition at line 613 of file regs.h.

#define RX_GAIN_CTRL_RX_FILTER_GAIN_TEST_MASK   (0x00000030u)

Definition at line 611 of file regs.h.

#define RX_GAIN_CTRL_RX_GAIN_MUX   (0x00008000u)

Definition at line 595 of file regs.h.

#define RX_GAIN_CTRL_RX_GAIN_MUX_BIT   (15)

Definition at line 597 of file regs.h.

#define RX_GAIN_CTRL_RX_GAIN_MUX_BITS   (1)

Definition at line 598 of file regs.h.

#define RX_GAIN_CTRL_RX_GAIN_MUX_MASK   (0x00008000u)

Definition at line 596 of file regs.h.

#define RX_GAIN_CTRL_RX_IF_GAIN_TEST   (0x0000000Fu)

Definition at line 615 of file regs.h.

#define RX_GAIN_CTRL_RX_IF_GAIN_TEST_BIT   (0)

Definition at line 617 of file regs.h.

#define RX_GAIN_CTRL_RX_IF_GAIN_TEST_BITS   (4)

Definition at line 618 of file regs.h.

#define RX_GAIN_CTRL_RX_IF_GAIN_TEST_MASK   (0x0000000Fu)

Definition at line 616 of file regs.h.

#define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST   (0x00000040u)

Definition at line 605 of file regs.h.

#define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST_BIT   (6)

Definition at line 607 of file regs.h.

#define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST_BITS   (1)

Definition at line 608 of file regs.h.

#define RX_GAIN_CTRL_RX_MIXER_GAIN_TEST_MASK   (0x00000040u)

Definition at line 606 of file regs.h.

#define RX_GAIN_CTRL_RX_RF_GAIN_TEST   (0x00000080u)

Definition at line 600 of file regs.h.

#define RX_GAIN_CTRL_RX_RF_GAIN_TEST_BIT   (7)

Definition at line 602 of file regs.h.

#define RX_GAIN_CTRL_RX_RF_GAIN_TEST_BITS   (1)

Definition at line 603 of file regs.h.

#define RX_GAIN_CTRL_RX_RF_GAIN_TEST_MASK   (0x00000080u)

Definition at line 601 of file regs.h.

#define RX_STATE   *((volatile int32u *)0x400020ACu)

Definition at line 2170 of file regs.h.

#define RX_STATE_ADDR   (0x400020ACu)

Definition at line 2172 of file regs.h.

#define RX_STATE_REG   *((volatile int32u *)0x400020ACu)

Definition at line 2171 of file regs.h.

#define RX_STATE_RESET   (0x00000000u)

Definition at line 2173 of file regs.h.

#define RX_STATE_RX_BUFFER_STATE   (0x000001E0u)

Definition at line 2175 of file regs.h.

#define RX_STATE_RX_BUFFER_STATE_BIT   (5)

Definition at line 2177 of file regs.h.

#define RX_STATE_RX_BUFFER_STATE_BITS   (4)

Definition at line 2178 of file regs.h.

#define RX_STATE_RX_BUFFER_STATE_MASK   (0x000001E0u)

Definition at line 2176 of file regs.h.

#define RX_STATE_RX_TOP_STATE   (0x0000001Fu)

Definition at line 2180 of file regs.h.

#define RX_STATE_RX_TOP_STATE_BIT   (0)

Definition at line 2182 of file regs.h.

#define RX_STATE_RX_TOP_STATE_BITS   (5)

Definition at line 2183 of file regs.h.

#define RX_STATE_RX_TOP_STATE_MASK   (0x0000001Fu)

Definition at line 2181 of file regs.h.

#define SC1_DATA   *((volatile int32u *)0x4000C83Cu)

Definition at line 6185 of file regs.h.

#define SC1_DATA_ADDR   (0x4000C83Cu)

Definition at line 6187 of file regs.h.

#define SC1_DATA_REG   *((volatile int32u *)0x4000C83Cu)

Definition at line 6186 of file regs.h.

#define SC1_DATA_RESET   (0x00000000u)

Definition at line 6188 of file regs.h.

#define SC1_DMACTRL   *((volatile int32u *)0x4000C830u)

Definition at line 6130 of file regs.h.

#define SC1_DMACTRL_ADDR   (0x4000C830u)

Definition at line 6132 of file regs.h.

#define SC1_DMACTRL_REG   *((volatile int32u *)0x4000C830u)

Definition at line 6131 of file regs.h.

#define SC1_DMACTRL_RESET   (0x00000000u)

Definition at line 6133 of file regs.h.

#define SC1_DMASTAT   *((volatile int32u *)0x4000C82Cu)

Definition at line 6070 of file regs.h.

#define SC1_DMASTAT_ADDR   (0x4000C82Cu)

Definition at line 6072 of file regs.h.

#define SC1_DMASTAT_REG   *((volatile int32u *)0x4000C82Cu)

Definition at line 6071 of file regs.h.

#define SC1_DMASTAT_RESET   (0x00000000u)

Definition at line 6073 of file regs.h.

#define SC1_INTMODE   *((volatile int32u *)0x4000A854u)

Definition at line 4455 of file regs.h.

#define SC1_INTMODE_ADDR   (0x4000A854u)

Definition at line 4457 of file regs.h.

#define SC1_INTMODE_REG   *((volatile int32u *)0x4000A854u)

Definition at line 4456 of file regs.h.

#define SC1_INTMODE_RESET   (0x00000000u)

Definition at line 4458 of file regs.h.

#define SC1_MODE   *((volatile int32u *)0x4000C854u)

Definition at line 6320 of file regs.h.

#define SC1_MODE_ADDR   (0x4000C854u)

Definition at line 6322 of file regs.h.

#define SC1_MODE_DISABLED   (0)

Definition at line 6330 of file regs.h.

#define SC1_MODE_I2C   (3)

Definition at line 6333 of file regs.h.

#define SC1_MODE_REG   *((volatile int32u *)0x4000C854u)

Definition at line 6321 of file regs.h.

#define SC1_MODE_RESET   (0x00000000u)

Definition at line 6323 of file regs.h.

#define SC1_MODE_SPI   (2)

Definition at line 6332 of file regs.h.

#define SC1_MODE_UART   (1)

Definition at line 6331 of file regs.h.

#define SC1_RATEEXP   *((volatile int32u *)0x4000C864u)

Definition at line 6420 of file regs.h.

#define SC1_RATEEXP_ADDR   (0x4000C864u)

Definition at line 6422 of file regs.h.

#define SC1_RATEEXP_REG   *((volatile int32u *)0x4000C864u)

Definition at line 6421 of file regs.h.

#define SC1_RATEEXP_RESET   (0x00000000u)

Definition at line 6423 of file regs.h.

#define SC1_RATELIN   *((volatile int32u *)0x4000C860u)

Definition at line 6410 of file regs.h.

#define SC1_RATELIN_ADDR   (0x4000C860u)

Definition at line 6412 of file regs.h.

#define SC1_RATELIN_REG   *((volatile int32u *)0x4000C860u)

Definition at line 6411 of file regs.h.

#define SC1_RATELIN_RESET   (0x00000000u)

Definition at line 6413 of file regs.h.

#define SC1_RXBEGA   *((volatile int32u *)0x4000C800u)

Definition at line 5920 of file regs.h.

#define SC1_RXBEGA_ADDR   (0x4000C800u)

Definition at line 5922 of file regs.h.

#define SC1_RXBEGA_FIXED   (0xFFFFE000u)

Definition at line 5925 of file regs.h.

#define SC1_RXBEGA_FIXED_BIT   (13)

Definition at line 5927 of file regs.h.

#define SC1_RXBEGA_FIXED_BITS   (19)

Definition at line 5928 of file regs.h.

#define SC1_RXBEGA_FIXED_MASK   (0xFFFFE000u)

Definition at line 5926 of file regs.h.

#define SC1_RXBEGA_REG   *((volatile int32u *)0x4000C800u)

Definition at line 5921 of file regs.h.

#define SC1_RXBEGA_RESET   (0x20000000u)

Definition at line 5923 of file regs.h.

#define SC1_RXBEGB   *((volatile int32u *)0x4000C808u)

Definition at line 5950 of file regs.h.

#define SC1_RXBEGB_ADDR   (0x4000C808u)

Definition at line 5952 of file regs.h.

#define SC1_RXBEGB_FIXED   (0xFFFFE000u)

Definition at line 5955 of file regs.h.

#define SC1_RXBEGB_FIXED_BIT   (13)

Definition at line 5957 of file regs.h.

#define SC1_RXBEGB_FIXED_BITS   (19)

Definition at line 5958 of file regs.h.

#define SC1_RXBEGB_FIXED_MASK   (0xFFFFE000u)

Definition at line 5956 of file regs.h.

#define SC1_RXBEGB_REG   *((volatile int32u *)0x4000C808u)

Definition at line 5951 of file regs.h.

#define SC1_RXBEGB_RESET   (0x20000000u)

Definition at line 5953 of file regs.h.

#define SC1_RXCNTA   *((volatile int32u *)0x4000C820u)

Definition at line 6040 of file regs.h.

#define SC1_RXCNTA_ADDR   (0x4000C820u)

Definition at line 6042 of file regs.h.

#define SC1_RXCNTA_REG   *((volatile int32u *)0x4000C820u)

Definition at line 6041 of file regs.h.

#define SC1_RXCNTA_RESET   (0x00000000u)

Definition at line 6043 of file regs.h.

#define SC1_RXCNTB   *((volatile int32u *)0x4000C824u)

Definition at line 6050 of file regs.h.

#define SC1_RXCNTB_ADDR   (0x4000C824u)

Definition at line 6052 of file regs.h.

#define SC1_RXCNTB_REG   *((volatile int32u *)0x4000C824u)

Definition at line 6051 of file regs.h.

#define SC1_RXCNTB_RESET   (0x00000000u)

Definition at line 6053 of file regs.h.

#define SC1_RXCNTSAVED   *((volatile int32u *)0x4000C870u)

Definition at line 6450 of file regs.h.

#define SC1_RXCNTSAVED_ADDR   (0x4000C870u)

Definition at line 6452 of file regs.h.

#define SC1_RXCNTSAVED_REG   *((volatile int32u *)0x4000C870u)

Definition at line 6451 of file regs.h.

#define SC1_RXCNTSAVED_RESET   (0x00000000u)

Definition at line 6453 of file regs.h.

#define SC1_RXENDA   *((volatile int32u *)0x4000C804u)

Definition at line 5935 of file regs.h.

#define SC1_RXENDA_ADDR   (0x4000C804u)

Definition at line 5937 of file regs.h.

#define SC1_RXENDA_FIXED   (0xFFFFE000u)

Definition at line 5940 of file regs.h.

#define SC1_RXENDA_FIXED_BIT   (13)

Definition at line 5942 of file regs.h.

#define SC1_RXENDA_FIXED_BITS   (19)

Definition at line 5943 of file regs.h.

#define SC1_RXENDA_FIXED_MASK   (0xFFFFE000u)

Definition at line 5941 of file regs.h.

#define SC1_RXENDA_REG   *((volatile int32u *)0x4000C804u)

Definition at line 5936 of file regs.h.

#define SC1_RXENDA_RESET   (0x20000000u)

Definition at line 5938 of file regs.h.

#define SC1_RXENDB   *((volatile int32u *)0x4000C80Cu)

Definition at line 5965 of file regs.h.

#define SC1_RXENDB_ADDR   (0x4000C80Cu)

Definition at line 5967 of file regs.h.

#define SC1_RXENDB_FIXED   (0xFFFFE000u)

Definition at line 5970 of file regs.h.

#define SC1_RXENDB_FIXED_BIT   (13)

Definition at line 5972 of file regs.h.

#define SC1_RXENDB_FIXED_BITS   (19)

Definition at line 5973 of file regs.h.

#define SC1_RXENDB_FIXED_MASK   (0xFFFFE000u)

Definition at line 5971 of file regs.h.

#define SC1_RXENDB_REG   *((volatile int32u *)0x4000C80Cu)

Definition at line 5966 of file regs.h.

#define SC1_RXENDB_RESET   (0x20000000u)

Definition at line 5968 of file regs.h.

#define SC1_RXERRA   *((volatile int32u *)0x4000C834u)

Definition at line 6165 of file regs.h.

#define SC1_RXERRA_ADDR   (0x4000C834u)

Definition at line 6167 of file regs.h.

#define SC1_RXERRA_REG   *((volatile int32u *)0x4000C834u)

Definition at line 6166 of file regs.h.

#define SC1_RXERRA_RESET   (0x00000000u)

Definition at line 6168 of file regs.h.

#define SC1_RXERRB   *((volatile int32u *)0x4000C838u)

Definition at line 6175 of file regs.h.

#define SC1_RXERRB_ADDR   (0x4000C838u)

Definition at line 6177 of file regs.h.

#define SC1_RXERRB_REG   *((volatile int32u *)0x4000C838u)

Definition at line 6176 of file regs.h.

#define SC1_RXERRB_RESET   (0x00000000u)

Definition at line 6178 of file regs.h.

#define SC1_SPICFG   *((volatile int32u *)0x4000C858u)

Definition at line 6335 of file regs.h.

#define SC1_SPICFG_ADDR   (0x4000C858u)

Definition at line 6337 of file regs.h.

#define SC1_SPICFG_REG   *((volatile int32u *)0x4000C858u)

Definition at line 6336 of file regs.h.

#define SC1_SPICFG_RESET   (0x00000000u)

Definition at line 6338 of file regs.h.

#define SC1_SPISTAT   *((volatile int32u *)0x4000C840u)

Definition at line 6195 of file regs.h.

#define SC1_SPISTAT_ADDR   (0x4000C840u)

Definition at line 6197 of file regs.h.

#define SC1_SPISTAT_REG   *((volatile int32u *)0x4000C840u)

Definition at line 6196 of file regs.h.

#define SC1_SPISTAT_RESET   (0x00000000u)

Definition at line 6198 of file regs.h.

#define SC1_TWICTRL1   *((volatile int32u *)0x4000C84Cu)

Definition at line 6285 of file regs.h.

#define SC1_TWICTRL1_ADDR   (0x4000C84Cu)

Definition at line 6287 of file regs.h.

#define SC1_TWICTRL1_REG   *((volatile int32u *)0x4000C84Cu)

Definition at line 6286 of file regs.h.

#define SC1_TWICTRL1_RESET   (0x00000000u)

Definition at line 6288 of file regs.h.

#define SC1_TWICTRL2   *((volatile int32u *)0x4000C850u)

Definition at line 6310 of file regs.h.

#define SC1_TWICTRL2_ADDR   (0x4000C850u)

Definition at line 6312 of file regs.h.

#define SC1_TWICTRL2_REG   *((volatile int32u *)0x4000C850u)

Definition at line 6311 of file regs.h.

#define SC1_TWICTRL2_RESET   (0x00000000u)

Definition at line 6313 of file regs.h.

#define SC1_TWISTAT   *((volatile int32u *)0x4000C844u)

Definition at line 6220 of file regs.h.

#define SC1_TWISTAT_ADDR   (0x4000C844u)

Definition at line 6222 of file regs.h.

#define SC1_TWISTAT_REG   *((volatile int32u *)0x4000C844u)

Definition at line 6221 of file regs.h.

#define SC1_TWISTAT_RESET   (0x00000000u)

Definition at line 6223 of file regs.h.

#define SC1_TXBEGA   *((volatile int32u *)0x4000C810u)

Definition at line 5980 of file regs.h.

#define SC1_TXBEGA_ADDR   (0x4000C810u)

Definition at line 5982 of file regs.h.

#define SC1_TXBEGA_FIXED   (0xFFFFE000u)

Definition at line 5985 of file regs.h.

#define SC1_TXBEGA_FIXED_BIT   (13)

Definition at line 5987 of file regs.h.

#define SC1_TXBEGA_FIXED_BITS   (19)

Definition at line 5988 of file regs.h.

#define SC1_TXBEGA_FIXED_MASK   (0xFFFFE000u)

Definition at line 5986 of file regs.h.

#define SC1_TXBEGA_REG   *((volatile int32u *)0x4000C810u)

Definition at line 5981 of file regs.h.

#define SC1_TXBEGA_RESET   (0x20000000u)

Definition at line 5983 of file regs.h.

#define SC1_TXBEGB   *((volatile int32u *)0x4000C818u)

Definition at line 6010 of file regs.h.

#define SC1_TXBEGB_ADDR   (0x4000C818u)

Definition at line 6012 of file regs.h.

#define SC1_TXBEGB_FIXED   (0xFFFFE000u)

Definition at line 6015 of file regs.h.

#define SC1_TXBEGB_FIXED_BIT   (13)

Definition at line 6017 of file regs.h.

#define SC1_TXBEGB_FIXED_BITS   (19)

Definition at line 6018 of file regs.h.

#define SC1_TXBEGB_FIXED_MASK   (0xFFFFE000u)

Definition at line 6016 of file regs.h.

#define SC1_TXBEGB_REG   *((volatile int32u *)0x4000C818u)

Definition at line 6011 of file regs.h.

#define SC1_TXBEGB_RESET   (0x20000000u)

Definition at line 6013 of file regs.h.

#define SC1_TXCNT   *((volatile int32u *)0x4000C828u)

Definition at line 6060 of file regs.h.

#define SC1_TXCNT_ADDR   (0x4000C828u)

Definition at line 6062 of file regs.h.

#define SC1_TXCNT_REG   *((volatile int32u *)0x4000C828u)

Definition at line 6061 of file regs.h.

#define SC1_TXCNT_RESET   (0x00000000u)

Definition at line 6063 of file regs.h.

#define SC1_TXENDA   *((volatile int32u *)0x4000C814u)

Definition at line 5995 of file regs.h.

#define SC1_TXENDA_ADDR   (0x4000C814u)

Definition at line 5997 of file regs.h.

#define SC1_TXENDA_FIXED   (0xFFFFE000u)

Definition at line 6000 of file regs.h.

#define SC1_TXENDA_FIXED_BIT   (13)

Definition at line 6002 of file regs.h.

#define SC1_TXENDA_FIXED_BITS   (19)

Definition at line 6003 of file regs.h.

#define SC1_TXENDA_FIXED_MASK   (0xFFFFE000u)

Definition at line 6001 of file regs.h.

#define SC1_TXENDA_REG   *((volatile int32u *)0x4000C814u)

Definition at line 5996 of file regs.h.

#define SC1_TXENDA_RESET   (0x20000000u)

Definition at line 5998 of file regs.h.

#define SC1_TXENDB   *((volatile int32u *)0x4000C81Cu)

Definition at line 6025 of file regs.h.

#define SC1_TXENDB_ADDR   (0x4000C81Cu)

Definition at line 6027 of file regs.h.

#define SC1_TXENDB_FIXED   (0xFFFFE000u)

Definition at line 6030 of file regs.h.

#define SC1_TXENDB_FIXED_BIT   (13)

Definition at line 6032 of file regs.h.

#define SC1_TXENDB_FIXED_BITS   (19)

Definition at line 6033 of file regs.h.

#define SC1_TXENDB_FIXED_MASK   (0xFFFFE000u)

Definition at line 6031 of file regs.h.

#define SC1_TXENDB_REG   *((volatile int32u *)0x4000C81Cu)

Definition at line 6026 of file regs.h.

#define SC1_TXENDB_RESET   (0x20000000u)

Definition at line 6028 of file regs.h.

#define SC1_UARTCFG   *((volatile int32u *)0x4000C85Cu)

Definition at line 6370 of file regs.h.

#define SC1_UARTCFG_ADDR   (0x4000C85Cu)

Definition at line 6372 of file regs.h.

#define SC1_UARTCFG_REG   *((volatile int32u *)0x4000C85Cu)

Definition at line 6371 of file regs.h.

#define SC1_UARTCFG_RESET   (0x00000000u)

Definition at line 6373 of file regs.h.

#define SC1_UARTFRAC   *((volatile int32u *)0x4000C86Cu)

Definition at line 6440 of file regs.h.

#define SC1_UARTFRAC_ADDR   (0x4000C86Cu)

Definition at line 6442 of file regs.h.

#define SC1_UARTFRAC_REG   *((volatile int32u *)0x4000C86Cu)

Definition at line 6441 of file regs.h.

#define SC1_UARTFRAC_RESET   (0x00000000u)

Definition at line 6443 of file regs.h.

#define SC1_UARTPER   *((volatile int32u *)0x4000C868u)

Definition at line 6430 of file regs.h.

#define SC1_UARTPER_ADDR   (0x4000C868u)

Definition at line 6432 of file regs.h.

#define SC1_UARTPER_REG   *((volatile int32u *)0x4000C868u)

Definition at line 6431 of file regs.h.

#define SC1_UARTPER_RESET   (0x00000000u)

Definition at line 6433 of file regs.h.

#define SC1_UARTSTAT   *((volatile int32u *)0x4000C848u)

Definition at line 6245 of file regs.h.

#define SC1_UARTSTAT_ADDR   (0x4000C848u)

Definition at line 6247 of file regs.h.

#define SC1_UARTSTAT_REG   *((volatile int32u *)0x4000C848u)

Definition at line 6246 of file regs.h.

#define SC1_UARTSTAT_RESET   (0x00000040u)

Definition at line 6248 of file regs.h.

#define SC1_WAKE_FILTER   (0x00000002u)

Definition at line 5486 of file regs.h.

#define SC1_WAKE_FILTER_BIT   (1)

Definition at line 5488 of file regs.h.

#define SC1_WAKE_FILTER_BITS   (1)

Definition at line 5489 of file regs.h.

#define SC1_WAKE_FILTER_MASK   (0x00000002u)

Definition at line 5487 of file regs.h.

#define SC2_DATA   *((volatile int32u *)0x4000C03Cu)

Definition at line 5746 of file regs.h.

#define SC2_DATA_ADDR   (0x4000C03Cu)

Definition at line 5748 of file regs.h.

#define SC2_DATA_REG   *((volatile int32u *)0x4000C03Cu)

Definition at line 5747 of file regs.h.

#define SC2_DATA_RESET   (0x00000000u)

Definition at line 5749 of file regs.h.

#define SC2_DMACTRL   *((volatile int32u *)0x4000C030u)

Definition at line 5691 of file regs.h.

#define SC2_DMACTRL_ADDR   (0x4000C030u)

Definition at line 5693 of file regs.h.

#define SC2_DMACTRL_REG   *((volatile int32u *)0x4000C030u)

Definition at line 5692 of file regs.h.

#define SC2_DMACTRL_RESET   (0x00000000u)

Definition at line 5694 of file regs.h.

#define SC2_DMASTAT   *((volatile int32u *)0x4000C02Cu)

Definition at line 5651 of file regs.h.

#define SC2_DMASTAT_ADDR   (0x4000C02Cu)

Definition at line 5653 of file regs.h.

#define SC2_DMASTAT_REG   *((volatile int32u *)0x4000C02Cu)

Definition at line 5652 of file regs.h.

#define SC2_DMASTAT_RESET   (0x00000000u)

Definition at line 5654 of file regs.h.

#define SC2_INTMODE   *((volatile int32u *)0x4000A858u)

Definition at line 4475 of file regs.h.

#define SC2_INTMODE_ADDR   (0x4000A858u)

Definition at line 4477 of file regs.h.

#define SC2_INTMODE_REG   *((volatile int32u *)0x4000A858u)

Definition at line 4476 of file regs.h.

#define SC2_INTMODE_RESET   (0x00000000u)

Definition at line 4478 of file regs.h.

#define SC2_MODE   *((volatile int32u *)0x4000C054u)

Definition at line 5841 of file regs.h.

#define SC2_MODE_ADDR   (0x4000C054u)

Definition at line 5843 of file regs.h.

#define SC2_MODE_DISABLED   (0)

Definition at line 5851 of file regs.h.

#define SC2_MODE_I2C   (3)

Definition at line 5853 of file regs.h.

#define SC2_MODE_REG   *((volatile int32u *)0x4000C054u)

Definition at line 5842 of file regs.h.

#define SC2_MODE_RESET   (0x00000000u)

Definition at line 5844 of file regs.h.

#define SC2_MODE_SPI   (2)

Definition at line 5852 of file regs.h.

#define SC2_RATEEXP   *((volatile int32u *)0x4000C064u)

Definition at line 5900 of file regs.h.

#define SC2_RATEEXP_ADDR   (0x4000C064u)

Definition at line 5902 of file regs.h.

#define SC2_RATEEXP_REG   *((volatile int32u *)0x4000C064u)

Definition at line 5901 of file regs.h.

#define SC2_RATEEXP_RESET   (0x00000000u)

Definition at line 5903 of file regs.h.

#define SC2_RATELIN   *((volatile int32u *)0x4000C060u)

Definition at line 5890 of file regs.h.

#define SC2_RATELIN_ADDR   (0x4000C060u)

Definition at line 5892 of file regs.h.

#define SC2_RATELIN_REG   *((volatile int32u *)0x4000C060u)

Definition at line 5891 of file regs.h.

#define SC2_RATELIN_RESET   (0x00000000u)

Definition at line 5893 of file regs.h.

#define SC2_RXBEGA   *((volatile int32u *)0x4000C000u)

Definition at line 5501 of file regs.h.

#define SC2_RXBEGA_ADDR   (0x4000C000u)

Definition at line 5503 of file regs.h.

#define SC2_RXBEGA_FIXED   (0xFFFFE000u)

Definition at line 5506 of file regs.h.

#define SC2_RXBEGA_FIXED_BIT   (13)

Definition at line 5508 of file regs.h.

#define SC2_RXBEGA_FIXED_BITS   (19)

Definition at line 5509 of file regs.h.

#define SC2_RXBEGA_FIXED_MASK   (0xFFFFE000u)

Definition at line 5507 of file regs.h.

#define SC2_RXBEGA_REG   *((volatile int32u *)0x4000C000u)

Definition at line 5502 of file regs.h.

#define SC2_RXBEGA_RESET   (0x20000000u)

Definition at line 5504 of file regs.h.

#define SC2_RXBEGB   *((volatile int32u *)0x4000C008u)

Definition at line 5531 of file regs.h.

#define SC2_RXBEGB_ADDR   (0x4000C008u)

Definition at line 5533 of file regs.h.

#define SC2_RXBEGB_FIXED   (0xFFFFE000u)

Definition at line 5536 of file regs.h.

#define SC2_RXBEGB_FIXED_BIT   (13)

Definition at line 5538 of file regs.h.

#define SC2_RXBEGB_FIXED_BITS   (19)

Definition at line 5539 of file regs.h.

#define SC2_RXBEGB_FIXED_MASK   (0xFFFFE000u)

Definition at line 5537 of file regs.h.

#define SC2_RXBEGB_REG   *((volatile int32u *)0x4000C008u)

Definition at line 5532 of file regs.h.

#define SC2_RXBEGB_RESET   (0x20000000u)

Definition at line 5534 of file regs.h.

#define SC2_RXCNTA   *((volatile int32u *)0x4000C020u)

Definition at line 5621 of file regs.h.

#define SC2_RXCNTA_ADDR   (0x4000C020u)

Definition at line 5623 of file regs.h.

#define SC2_RXCNTA_REG   *((volatile int32u *)0x4000C020u)

Definition at line 5622 of file regs.h.

#define SC2_RXCNTA_RESET   (0x00000000u)

Definition at line 5624 of file regs.h.

#define SC2_RXCNTB   *((volatile int32u *)0x4000C024u)

Definition at line 5631 of file regs.h.

#define SC2_RXCNTB_ADDR   (0x4000C024u)

Definition at line 5633 of file regs.h.

#define SC2_RXCNTB_REG   *((volatile int32u *)0x4000C024u)

Definition at line 5632 of file regs.h.

#define SC2_RXCNTB_RESET   (0x00000000u)

Definition at line 5634 of file regs.h.

#define SC2_RXCNTSAVED   *((volatile int32u *)0x4000C070u)

Definition at line 5910 of file regs.h.

#define SC2_RXCNTSAVED_ADDR   (0x4000C070u)

Definition at line 5912 of file regs.h.

#define SC2_RXCNTSAVED_REG   *((volatile int32u *)0x4000C070u)

Definition at line 5911 of file regs.h.

#define SC2_RXCNTSAVED_RESET   (0x00000000u)

Definition at line 5913 of file regs.h.

#define SC2_RXENDA   *((volatile int32u *)0x4000C004u)

Definition at line 5516 of file regs.h.

#define SC2_RXENDA_ADDR   (0x4000C004u)

Definition at line 5518 of file regs.h.

#define SC2_RXENDA_FIXED   (0xFFFFE000u)

Definition at line 5521 of file regs.h.

#define SC2_RXENDA_FIXED_BIT   (13)

Definition at line 5523 of file regs.h.

#define SC2_RXENDA_FIXED_BITS   (19)

Definition at line 5524 of file regs.h.

#define SC2_RXENDA_FIXED_MASK   (0xFFFFE000u)

Definition at line 5522 of file regs.h.

#define SC2_RXENDA_REG   *((volatile int32u *)0x4000C004u)

Definition at line 5517 of file regs.h.

#define SC2_RXENDA_RESET   (0x20000000u)

Definition at line 5519 of file regs.h.

#define SC2_RXENDB   *((volatile int32u *)0x4000C00Cu)

Definition at line 5546 of file regs.h.

#define SC2_RXENDB_ADDR   (0x4000C00Cu)

Definition at line 5548 of file regs.h.

#define SC2_RXENDB_FIXED   (0xFFFFE000u)

Definition at line 5551 of file regs.h.

#define SC2_RXENDB_FIXED_BIT   (13)

Definition at line 5553 of file regs.h.

#define SC2_RXENDB_FIXED_BITS   (19)

Definition at line 5554 of file regs.h.

#define SC2_RXENDB_FIXED_MASK   (0xFFFFE000u)

Definition at line 5552 of file regs.h.

#define SC2_RXENDB_REG   *((volatile int32u *)0x4000C00Cu)

Definition at line 5547 of file regs.h.

#define SC2_RXENDB_RESET   (0x20000000u)

Definition at line 5549 of file regs.h.

#define SC2_RXERRA   *((volatile int32u *)0x4000C034u)

Definition at line 5726 of file regs.h.

#define SC2_RXERRA_ADDR   (0x4000C034u)

Definition at line 5728 of file regs.h.

#define SC2_RXERRA_REG   *((volatile int32u *)0x4000C034u)

Definition at line 5727 of file regs.h.

#define SC2_RXERRA_RESET   (0x00000000u)

Definition at line 5729 of file regs.h.

#define SC2_RXERRB   *((volatile int32u *)0x4000C038u)

Definition at line 5736 of file regs.h.

#define SC2_RXERRB_ADDR   (0x4000C038u)

Definition at line 5738 of file regs.h.

#define SC2_RXERRB_REG   *((volatile int32u *)0x4000C038u)

Definition at line 5737 of file regs.h.

#define SC2_RXERRB_RESET   (0x00000000u)

Definition at line 5739 of file regs.h.

#define SC2_SPICFG   *((volatile int32u *)0x4000C058u)

Definition at line 5855 of file regs.h.

#define SC2_SPICFG_ADDR   (0x4000C058u)

Definition at line 5857 of file regs.h.

#define SC2_SPICFG_REG   *((volatile int32u *)0x4000C058u)

Definition at line 5856 of file regs.h.

#define SC2_SPICFG_RESET   (0x00000000u)

Definition at line 5858 of file regs.h.

#define SC2_SPISTAT   *((volatile int32u *)0x4000C040u)

Definition at line 5756 of file regs.h.

#define SC2_SPISTAT_ADDR   (0x4000C040u)

Definition at line 5758 of file regs.h.

#define SC2_SPISTAT_REG   *((volatile int32u *)0x4000C040u)

Definition at line 5757 of file regs.h.

#define SC2_SPISTAT_RESET   (0x00000000u)

Definition at line 5759 of file regs.h.

#define SC2_TWICTRL1   *((volatile int32u *)0x4000C04Cu)

Definition at line 5806 of file regs.h.

#define SC2_TWICTRL1_ADDR   (0x4000C04Cu)

Definition at line 5808 of file regs.h.

#define SC2_TWICTRL1_REG   *((volatile int32u *)0x4000C04Cu)

Definition at line 5807 of file regs.h.

#define SC2_TWICTRL1_RESET   (0x00000000u)

Definition at line 5809 of file regs.h.

#define SC2_TWICTRL2   *((volatile int32u *)0x4000C050u)

Definition at line 5831 of file regs.h.

#define SC2_TWICTRL2_ADDR   (0x4000C050u)

Definition at line 5833 of file regs.h.

#define SC2_TWICTRL2_REG   *((volatile int32u *)0x4000C050u)

Definition at line 5832 of file regs.h.

#define SC2_TWICTRL2_RESET   (0x00000000u)

Definition at line 5834 of file regs.h.

#define SC2_TWISTAT   *((volatile int32u *)0x4000C044u)

Definition at line 5781 of file regs.h.

#define SC2_TWISTAT_ADDR   (0x4000C044u)

Definition at line 5783 of file regs.h.

#define SC2_TWISTAT_REG   *((volatile int32u *)0x4000C044u)

Definition at line 5782 of file regs.h.

#define SC2_TWISTAT_RESET   (0x00000000u)

Definition at line 5784 of file regs.h.

#define SC2_TXBEGA   *((volatile int32u *)0x4000C010u)

Definition at line 5561 of file regs.h.

#define SC2_TXBEGA_ADDR   (0x4000C010u)

Definition at line 5563 of file regs.h.

#define SC2_TXBEGA_FIXED   (0xFFFFE000u)

Definition at line 5566 of file regs.h.

#define SC2_TXBEGA_FIXED_BIT   (13)

Definition at line 5568 of file regs.h.

#define SC2_TXBEGA_FIXED_BITS   (19)

Definition at line 5569 of file regs.h.

#define SC2_TXBEGA_FIXED_MASK   (0xFFFFE000u)

Definition at line 5567 of file regs.h.

#define SC2_TXBEGA_REG   *((volatile int32u *)0x4000C010u)

Definition at line 5562 of file regs.h.

#define SC2_TXBEGA_RESET   (0x20000000u)

Definition at line 5564 of file regs.h.

#define SC2_TXBEGB   *((volatile int32u *)0x4000C018u)

Definition at line 5591 of file regs.h.

#define SC2_TXBEGB_ADDR   (0x4000C018u)

Definition at line 5593 of file regs.h.

#define SC2_TXBEGB_FIXED   (0xFFFFE000u)

Definition at line 5596 of file regs.h.

#define SC2_TXBEGB_FIXED_BIT   (13)

Definition at line 5598 of file regs.h.

#define SC2_TXBEGB_FIXED_BITS   (19)

Definition at line 5599 of file regs.h.

#define SC2_TXBEGB_FIXED_MASK   (0xFFFFE000u)

Definition at line 5597 of file regs.h.

#define SC2_TXBEGB_REG   *((volatile int32u *)0x4000C018u)

Definition at line 5592 of file regs.h.

#define SC2_TXBEGB_RESET   (0x20000000u)

Definition at line 5594 of file regs.h.

#define SC2_TXCNT   *((volatile int32u *)0x4000C028u)

Definition at line 5641 of file regs.h.

#define SC2_TXCNT_ADDR   (0x4000C028u)

Definition at line 5643 of file regs.h.

#define SC2_TXCNT_REG   *((volatile int32u *)0x4000C028u)

Definition at line 5642 of file regs.h.

#define SC2_TXCNT_RESET   (0x00000000u)

Definition at line 5644 of file regs.h.

#define SC2_TXENDA   *((volatile int32u *)0x4000C014u)

Definition at line 5576 of file regs.h.

#define SC2_TXENDA_ADDR   (0x4000C014u)

Definition at line 5578 of file regs.h.

#define SC2_TXENDA_FIXED   (0xFFFFE000u)

Definition at line 5581 of file regs.h.

#define SC2_TXENDA_FIXED_BIT   (13)

Definition at line 5583 of file regs.h.

#define SC2_TXENDA_FIXED_BITS   (19)

Definition at line 5584 of file regs.h.

#define SC2_TXENDA_FIXED_MASK   (0xFFFFE000u)

Definition at line 5582 of file regs.h.

#define SC2_TXENDA_REG   *((volatile int32u *)0x4000C014u)

Definition at line 5577 of file regs.h.

#define SC2_TXENDA_RESET   (0x20000000u)

Definition at line 5579 of file regs.h.

#define SC2_TXENDB   *((volatile int32u *)0x4000C01Cu)

Definition at line 5606 of file regs.h.

#define SC2_TXENDB_ADDR   (0x4000C01Cu)

Definition at line 5608 of file regs.h.

#define SC2_TXENDB_FIXED   (0xFFFFE000u)

Definition at line 5611 of file regs.h.

#define SC2_TXENDB_FIXED_BIT   (13)

Definition at line 5613 of file regs.h.

#define SC2_TXENDB_FIXED_BITS   (19)

Definition at line 5614 of file regs.h.

#define SC2_TXENDB_FIXED_MASK   (0xFFFFE000u)

Definition at line 5612 of file regs.h.

#define SC2_TXENDB_REG   *((volatile int32u *)0x4000C01Cu)

Definition at line 5607 of file regs.h.

#define SC2_TXENDB_RESET   (0x20000000u)

Definition at line 5609 of file regs.h.

#define SC2_WAKE_FILTER   (0x00000004u)

Definition at line 5481 of file regs.h.

#define SC2_WAKE_FILTER_BIT   (2)

Definition at line 5483 of file regs.h.

#define SC2_WAKE_FILTER_BITS   (1)

Definition at line 5484 of file regs.h.

#define SC2_WAKE_FILTER_MASK   (0x00000004u)

Definition at line 5482 of file regs.h.

#define SC_DATA   (0x000000FFu)

Definition at line 6190 of file regs.h.

#define SC_DATA   (0x000000FFu)

Definition at line 6190 of file regs.h.

#define SC_DATA_BIT   (0)

Definition at line 6192 of file regs.h.

#define SC_DATA_BIT   (0)

Definition at line 6192 of file regs.h.

#define SC_DATA_BITS   (8)

Definition at line 6193 of file regs.h.

#define SC_DATA_BITS   (8)

Definition at line 6193 of file regs.h.

#define SC_DATA_MASK   (0x000000FFu)

Definition at line 6191 of file regs.h.

#define SC_DATA_MASK   (0x000000FFu)

Definition at line 6191 of file regs.h.

#define SC_MODE   (0x00000003u)

Definition at line 6325 of file regs.h.

#define SC_MODE   (0x00000003u)

Definition at line 6325 of file regs.h.

#define SC_MODE_BIT   (0)

Definition at line 6327 of file regs.h.

#define SC_MODE_BIT   (0)

Definition at line 6327 of file regs.h.

#define SC_MODE_BITS   (2)

Definition at line 6328 of file regs.h.

#define SC_MODE_BITS   (2)

Definition at line 6328 of file regs.h.

#define SC_MODE_MASK   (0x00000003u)

Definition at line 6326 of file regs.h.

#define SC_MODE_MASK   (0x00000003u)

Definition at line 6326 of file regs.h.

#define SC_RATEEXP   (0x0000000Fu)

Definition at line 6425 of file regs.h.

#define SC_RATEEXP   (0x0000000Fu)

Definition at line 6425 of file regs.h.

#define SC_RATEEXP_BIT   (0)

Definition at line 6427 of file regs.h.

#define SC_RATEEXP_BIT   (0)

Definition at line 6427 of file regs.h.

#define SC_RATEEXP_BITS   (4)

Definition at line 6428 of file regs.h.

#define SC_RATEEXP_BITS   (4)

Definition at line 6428 of file regs.h.

#define SC_RATEEXP_MASK   (0x0000000Fu)

Definition at line 6426 of file regs.h.

#define SC_RATEEXP_MASK   (0x0000000Fu)

Definition at line 6426 of file regs.h.

#define SC_RATELIN   (0x0000000Fu)

Definition at line 6415 of file regs.h.

#define SC_RATELIN   (0x0000000Fu)

Definition at line 6415 of file regs.h.

#define SC_RATELIN_BIT   (0)

Definition at line 6417 of file regs.h.

#define SC_RATELIN_BIT   (0)

Definition at line 6417 of file regs.h.

#define SC_RATELIN_BITS   (4)

Definition at line 6418 of file regs.h.

#define SC_RATELIN_BITS   (4)

Definition at line 6418 of file regs.h.

#define SC_RATELIN_MASK   (0x0000000Fu)

Definition at line 6416 of file regs.h.

#define SC_RATELIN_MASK   (0x0000000Fu)

Definition at line 6416 of file regs.h.

#define SC_RXACTA   (0x00000001u)

Definition at line 6125 of file regs.h.

#define SC_RXACTA   (0x00000001u)

Definition at line 6125 of file regs.h.

#define SC_RXACTA_BIT   (0)

Definition at line 6127 of file regs.h.

#define SC_RXACTA_BIT   (0)

Definition at line 6127 of file regs.h.

#define SC_RXACTA_BITS   (1)

Definition at line 6128 of file regs.h.

#define SC_RXACTA_BITS   (1)

Definition at line 6128 of file regs.h.

#define SC_RXACTA_MASK   (0x00000001u)

Definition at line 6126 of file regs.h.

#define SC_RXACTA_MASK   (0x00000001u)

Definition at line 6126 of file regs.h.

#define SC_RXACTB   (0x00000002u)

Definition at line 6120 of file regs.h.

#define SC_RXACTB   (0x00000002u)

Definition at line 6120 of file regs.h.

#define SC_RXACTB_BIT   (1)

Definition at line 6122 of file regs.h.

#define SC_RXACTB_BIT   (1)

Definition at line 6122 of file regs.h.

#define SC_RXACTB_BITS   (1)

Definition at line 6123 of file regs.h.

#define SC_RXACTB_BITS   (1)

Definition at line 6123 of file regs.h.

#define SC_RXACTB_MASK   (0x00000002u)

Definition at line 6121 of file regs.h.

#define SC_RXACTB_MASK   (0x00000002u)

Definition at line 6121 of file regs.h.

#define SC_RXBEGA   (0x00001FFFu)

Definition at line 5930 of file regs.h.

#define SC_RXBEGA   (0x00001FFFu)

Definition at line 5930 of file regs.h.

#define SC_RXBEGA_BIT   (0)

Definition at line 5932 of file regs.h.

#define SC_RXBEGA_BIT   (0)

Definition at line 5932 of file regs.h.

#define SC_RXBEGA_BITS   (13)

Definition at line 5933 of file regs.h.

#define SC_RXBEGA_BITS   (13)

Definition at line 5933 of file regs.h.

#define SC_RXBEGA_MASK   (0x00001FFFu)

Definition at line 5931 of file regs.h.

#define SC_RXBEGA_MASK   (0x00001FFFu)

Definition at line 5931 of file regs.h.

#define SC_RXBEGB   (0x00001FFFu)

Definition at line 5960 of file regs.h.

#define SC_RXBEGB   (0x00001FFFu)

Definition at line 5960 of file regs.h.

#define SC_RXBEGB_BIT   (0)

Definition at line 5962 of file regs.h.

#define SC_RXBEGB_BIT   (0)

Definition at line 5962 of file regs.h.

#define SC_RXBEGB_BITS   (13)

Definition at line 5963 of file regs.h.

#define SC_RXBEGB_BITS   (13)

Definition at line 5963 of file regs.h.

#define SC_RXBEGB_MASK   (0x00001FFFu)

Definition at line 5961 of file regs.h.

#define SC_RXBEGB_MASK   (0x00001FFFu)

Definition at line 5961 of file regs.h.

#define SC_RXCNTA   (0x00001FFFu)

Definition at line 6045 of file regs.h.

#define SC_RXCNTA   (0x00001FFFu)

Definition at line 6045 of file regs.h.

#define SC_RXCNTA_BIT   (0)

Definition at line 6047 of file regs.h.

#define SC_RXCNTA_BIT   (0)

Definition at line 6047 of file regs.h.

#define SC_RXCNTA_BITS   (13)

Definition at line 6048 of file regs.h.

#define SC_RXCNTA_BITS   (13)

Definition at line 6048 of file regs.h.

#define SC_RXCNTA_MASK   (0x00001FFFu)

Definition at line 6046 of file regs.h.

#define SC_RXCNTA_MASK   (0x00001FFFu)

Definition at line 6046 of file regs.h.

#define SC_RXCNTB   (0x00001FFFu)

Definition at line 6055 of file regs.h.

#define SC_RXCNTB   (0x00001FFFu)

Definition at line 6055 of file regs.h.

#define SC_RXCNTB_BIT   (0)

Definition at line 6057 of file regs.h.

#define SC_RXCNTB_BIT   (0)

Definition at line 6057 of file regs.h.

#define SC_RXCNTB_BITS   (13)

Definition at line 6058 of file regs.h.

#define SC_RXCNTB_BITS   (13)

Definition at line 6058 of file regs.h.

#define SC_RXCNTB_MASK   (0x00001FFFu)

Definition at line 6056 of file regs.h.

#define SC_RXCNTB_MASK   (0x00001FFFu)

Definition at line 6056 of file regs.h.

#define SC_RXCNTSAVED   (0x00001FFFu)

Definition at line 6455 of file regs.h.

#define SC_RXCNTSAVED   (0x00001FFFu)

Definition at line 6455 of file regs.h.

#define SC_RXCNTSAVED_BIT   (0)

Definition at line 6457 of file regs.h.

#define SC_RXCNTSAVED_BIT   (0)

Definition at line 6457 of file regs.h.

#define SC_RXCNTSAVED_BITS   (13)

Definition at line 6458 of file regs.h.

#define SC_RXCNTSAVED_BITS   (13)

Definition at line 6458 of file regs.h.

#define SC_RXCNTSAVED_MASK   (0x00001FFFu)

Definition at line 6456 of file regs.h.

#define SC_RXCNTSAVED_MASK   (0x00001FFFu)

Definition at line 6456 of file regs.h.

#define SC_RXDMARST   (0x00000010u)

Definition at line 6140 of file regs.h.

#define SC_RXDMARST   (0x00000010u)

Definition at line 6140 of file regs.h.

#define SC_RXDMARST_BIT   (4)

Definition at line 6142 of file regs.h.

#define SC_RXDMARST_BIT   (4)

Definition at line 6142 of file regs.h.

#define SC_RXDMARST_BITS   (1)

Definition at line 6143 of file regs.h.

#define SC_RXDMARST_BITS   (1)

Definition at line 6143 of file regs.h.

#define SC_RXDMARST_MASK   (0x00000010u)

Definition at line 6141 of file regs.h.

#define SC_RXDMARST_MASK   (0x00000010u)

Definition at line 6141 of file regs.h.

#define SC_RXENDA   (0x00001FFFu)

Definition at line 5945 of file regs.h.

#define SC_RXENDA   (0x00001FFFu)

Definition at line 5945 of file regs.h.

#define SC_RXENDA_BIT   (0)

Definition at line 5947 of file regs.h.

#define SC_RXENDA_BIT   (0)

Definition at line 5947 of file regs.h.

#define SC_RXENDA_BITS   (13)

Definition at line 5948 of file regs.h.

#define SC_RXENDA_BITS   (13)

Definition at line 5948 of file regs.h.

#define SC_RXENDA_MASK   (0x00001FFFu)

Definition at line 5946 of file regs.h.

#define SC_RXENDA_MASK   (0x00001FFFu)

Definition at line 5946 of file regs.h.

#define SC_RXENDB   (0x00001FFFu)

Definition at line 5975 of file regs.h.

#define SC_RXENDB   (0x00001FFFu)

Definition at line 5975 of file regs.h.

#define SC_RXENDB_BIT   (0)

Definition at line 5977 of file regs.h.

#define SC_RXENDB_BIT   (0)

Definition at line 5977 of file regs.h.

#define SC_RXENDB_BITS   (13)

Definition at line 5978 of file regs.h.

#define SC_RXENDB_BITS   (13)

Definition at line 5978 of file regs.h.

#define SC_RXENDB_MASK   (0x00001FFFu)

Definition at line 5976 of file regs.h.

#define SC_RXENDB_MASK   (0x00001FFFu)

Definition at line 5976 of file regs.h.

#define SC_RXERRA   (0x00001FFFu)

Definition at line 6170 of file regs.h.

#define SC_RXERRA   (0x00001FFFu)

Definition at line 6170 of file regs.h.

#define SC_RXERRA_BIT   (0)

Definition at line 6172 of file regs.h.

#define SC_RXERRA_BIT   (0)

Definition at line 6172 of file regs.h.

#define SC_RXERRA_BITS   (13)

Definition at line 6173 of file regs.h.

#define SC_RXERRA_BITS   (13)

Definition at line 6173 of file regs.h.

#define SC_RXERRA_MASK   (0x00001FFFu)

Definition at line 6171 of file regs.h.

#define SC_RXERRA_MASK   (0x00001FFFu)

Definition at line 6171 of file regs.h.

#define SC_RXERRB   (0x00001FFFu)

Definition at line 6180 of file regs.h.

#define SC_RXERRB   (0x00001FFFu)

Definition at line 6180 of file regs.h.

#define SC_RXERRB_BIT   (0)

Definition at line 6182 of file regs.h.

#define SC_RXERRB_BIT   (0)

Definition at line 6182 of file regs.h.

#define SC_RXERRB_BITS   (13)

Definition at line 6183 of file regs.h.

#define SC_RXERRB_BITS   (13)

Definition at line 6183 of file regs.h.

#define SC_RXERRB_MASK   (0x00001FFFu)

Definition at line 6181 of file regs.h.

#define SC_RXERRB_MASK   (0x00001FFFu)

Definition at line 6181 of file regs.h.

#define SC_RXFRMA   (0x00000100u)

Definition at line 6085 of file regs.h.

#define SC_RXFRMA_BIT   (8)

Definition at line 6087 of file regs.h.

#define SC_RXFRMA_BITS   (1)

Definition at line 6088 of file regs.h.

#define SC_RXFRMA_MASK   (0x00000100u)

Definition at line 6086 of file regs.h.

#define SC_RXFRMB   (0x00000200u)

Definition at line 6080 of file regs.h.

#define SC_RXFRMB_BIT   (9)

Definition at line 6082 of file regs.h.

#define SC_RXFRMB_BITS   (1)

Definition at line 6083 of file regs.h.

#define SC_RXFRMB_MASK   (0x00000200u)

Definition at line 6081 of file regs.h.

#define SC_RXLODA   (0x00000001u)

Definition at line 6160 of file regs.h.

#define SC_RXLODA   (0x00000001u)

Definition at line 6160 of file regs.h.

#define SC_RXLODA_BIT   (0)

Definition at line 6162 of file regs.h.

#define SC_RXLODA_BIT   (0)

Definition at line 6162 of file regs.h.

#define SC_RXLODA_BITS   (1)

Definition at line 6163 of file regs.h.

#define SC_RXLODA_BITS   (1)

Definition at line 6163 of file regs.h.

#define SC_RXLODA_MASK   (0x00000001u)

Definition at line 6161 of file regs.h.

#define SC_RXLODA_MASK   (0x00000001u)

Definition at line 6161 of file regs.h.

#define SC_RXLODB   (0x00000002u)

Definition at line 6155 of file regs.h.

#define SC_RXLODB   (0x00000002u)

Definition at line 6155 of file regs.h.

#define SC_RXLODB_BIT   (1)

Definition at line 6157 of file regs.h.

#define SC_RXLODB_BIT   (1)

Definition at line 6157 of file regs.h.

#define SC_RXLODB_BITS   (1)

Definition at line 6158 of file regs.h.

#define SC_RXLODB_BITS   (1)

Definition at line 6158 of file regs.h.

#define SC_RXLODB_MASK   (0x00000002u)

Definition at line 6156 of file regs.h.

#define SC_RXLODB_MASK   (0x00000002u)

Definition at line 6156 of file regs.h.

#define SC_RXOVFA   (0x00000010u)

Definition at line 6105 of file regs.h.

#define SC_RXOVFA   (0x00000010u)

Definition at line 6105 of file regs.h.

#define SC_RXOVFA_BIT   (4)

Definition at line 6107 of file regs.h.

#define SC_RXOVFA_BIT   (4)

Definition at line 6107 of file regs.h.

#define SC_RXOVFA_BITS   (1)

Definition at line 6108 of file regs.h.

#define SC_RXOVFA_BITS   (1)

Definition at line 6108 of file regs.h.

#define SC_RXOVFA_MASK   (0x00000010u)

Definition at line 6106 of file regs.h.

#define SC_RXOVFA_MASK   (0x00000010u)

Definition at line 6106 of file regs.h.

#define SC_RXOVFB   (0x00000020u)

Definition at line 6100 of file regs.h.

#define SC_RXOVFB   (0x00000020u)

Definition at line 6100 of file regs.h.

#define SC_RXOVFB_BIT   (5)

Definition at line 6102 of file regs.h.

#define SC_RXOVFB_BIT   (5)

Definition at line 6102 of file regs.h.

#define SC_RXOVFB_BITS   (1)

Definition at line 6103 of file regs.h.

#define SC_RXOVFB_BITS   (1)

Definition at line 6103 of file regs.h.

#define SC_RXOVFB_MASK   (0x00000020u)

Definition at line 6101 of file regs.h.

#define SC_RXOVFB_MASK   (0x00000020u)

Definition at line 6101 of file regs.h.

#define SC_RXPARA   (0x00000040u)

Definition at line 6095 of file regs.h.

#define SC_RXPARA_BIT   (6)

Definition at line 6097 of file regs.h.

#define SC_RXPARA_BITS   (1)

Definition at line 6098 of file regs.h.

#define SC_RXPARA_MASK   (0x00000040u)

Definition at line 6096 of file regs.h.

#define SC_RXPARB   (0x00000080u)

Definition at line 6090 of file regs.h.

#define SC_RXPARB_BIT   (7)

Definition at line 6092 of file regs.h.

#define SC_RXPARB_BITS   (1)

Definition at line 6093 of file regs.h.

#define SC_RXPARB_MASK   (0x00000080u)

Definition at line 6091 of file regs.h.

#define SC_RXSSEL   (0x00001C00u)

Definition at line 6075 of file regs.h.

#define SC_RXSSEL   (0x00001C00u)

Definition at line 6075 of file regs.h.

#define SC_RXSSEL_BIT   (10)

Definition at line 6077 of file regs.h.

#define SC_RXSSEL_BIT   (10)

Definition at line 6077 of file regs.h.

#define SC_RXSSEL_BITS   (3)

Definition at line 6078 of file regs.h.

#define SC_RXSSEL_BITS   (3)

Definition at line 6078 of file regs.h.

#define SC_RXSSEL_MASK   (0x00001C00u)

Definition at line 6076 of file regs.h.

#define SC_RXSSEL_MASK   (0x00001C00u)

Definition at line 6076 of file regs.h.

#define SC_RXVALLEVEL   (0x00000001u)

Definition at line 4490 of file regs.h.

#define SC_RXVALLEVEL   (0x00000001u)

Definition at line 4490 of file regs.h.

#define SC_RXVALLEVEL_BIT   (0)

Definition at line 4492 of file regs.h.

#define SC_RXVALLEVEL_BIT   (0)

Definition at line 4492 of file regs.h.

#define SC_RXVALLEVEL_BITS   (1)

Definition at line 4493 of file regs.h.

#define SC_RXVALLEVEL_BITS   (1)

Definition at line 4493 of file regs.h.

#define SC_RXVALLEVEL_MASK   (0x00000001u)

Definition at line 4491 of file regs.h.

#define SC_RXVALLEVEL_MASK   (0x00000001u)

Definition at line 4491 of file regs.h.

#define SC_SPIMST   (0x00000010u)

Definition at line 6345 of file regs.h.

#define SC_SPIMST   (0x00000010u)

Definition at line 6345 of file regs.h.

#define SC_SPIMST_BIT   (4)

Definition at line 6347 of file regs.h.

#define SC_SPIMST_BIT   (4)

Definition at line 6347 of file regs.h.

#define SC_SPIMST_BITS   (1)

Definition at line 6348 of file regs.h.

#define SC_SPIMST_BITS   (1)

Definition at line 6348 of file regs.h.

#define SC_SPIMST_MASK   (0x00000010u)

Definition at line 6346 of file regs.h.

#define SC_SPIMST_MASK   (0x00000010u)

Definition at line 6346 of file regs.h.

#define SC_SPIORD   (0x00000004u)

Definition at line 6355 of file regs.h.

#define SC_SPIORD   (0x00000004u)

Definition at line 6355 of file regs.h.

#define SC_SPIORD_BIT   (2)

Definition at line 6357 of file regs.h.

#define SC_SPIORD_BIT   (2)

Definition at line 6357 of file regs.h.

#define SC_SPIORD_BITS   (1)

Definition at line 6358 of file regs.h.

#define SC_SPIORD_BITS   (1)

Definition at line 6358 of file regs.h.

#define SC_SPIORD_MASK   (0x00000004u)

Definition at line 6356 of file regs.h.

#define SC_SPIORD_MASK   (0x00000004u)

Definition at line 6356 of file regs.h.

#define SC_SPIPHA   (0x00000002u)

Definition at line 6360 of file regs.h.

#define SC_SPIPHA   (0x00000002u)

Definition at line 6360 of file regs.h.

#define SC_SPIPHA_BIT   (1)

Definition at line 6362 of file regs.h.

#define SC_SPIPHA_BIT   (1)

Definition at line 6362 of file regs.h.

#define SC_SPIPHA_BITS   (1)

Definition at line 6363 of file regs.h.

#define SC_SPIPHA_BITS   (1)

Definition at line 6363 of file regs.h.

#define SC_SPIPHA_MASK   (0x00000002u)

Definition at line 6361 of file regs.h.

#define SC_SPIPHA_MASK   (0x00000002u)

Definition at line 6361 of file regs.h.

#define SC_SPIPOL   (0x00000001u)

Definition at line 6365 of file regs.h.

#define SC_SPIPOL   (0x00000001u)

Definition at line 6365 of file regs.h.

#define SC_SPIPOL_BIT   (0)

Definition at line 6367 of file regs.h.

#define SC_SPIPOL_BIT   (0)

Definition at line 6367 of file regs.h.

#define SC_SPIPOL_BITS   (1)

Definition at line 6368 of file regs.h.

#define SC_SPIPOL_BITS   (1)

Definition at line 6368 of file regs.h.

#define SC_SPIPOL_MASK   (0x00000001u)

Definition at line 6366 of file regs.h.

#define SC_SPIPOL_MASK   (0x00000001u)

Definition at line 6366 of file regs.h.

#define SC_SPIRPT   (0x00000008u)

Definition at line 6350 of file regs.h.

#define SC_SPIRPT   (0x00000008u)

Definition at line 6350 of file regs.h.

#define SC_SPIRPT_BIT   (3)

Definition at line 6352 of file regs.h.

#define SC_SPIRPT_BIT   (3)

Definition at line 6352 of file regs.h.

#define SC_SPIRPT_BITS   (1)

Definition at line 6353 of file regs.h.

#define SC_SPIRPT_BITS   (1)

Definition at line 6353 of file regs.h.

#define SC_SPIRPT_MASK   (0x00000008u)

Definition at line 6351 of file regs.h.

#define SC_SPIRPT_MASK   (0x00000008u)

Definition at line 6351 of file regs.h.

#define SC_SPIRXDRV   (0x00000020u)

Definition at line 6340 of file regs.h.

#define SC_SPIRXDRV   (0x00000020u)

Definition at line 6340 of file regs.h.

#define SC_SPIRXDRV_BIT   (5)

Definition at line 6342 of file regs.h.

#define SC_SPIRXDRV_BIT   (5)

Definition at line 6342 of file regs.h.

#define SC_SPIRXDRV_BITS   (1)

Definition at line 6343 of file regs.h.

#define SC_SPIRXDRV_BITS   (1)

Definition at line 6343 of file regs.h.

#define SC_SPIRXDRV_MASK   (0x00000020u)

Definition at line 6341 of file regs.h.

#define SC_SPIRXDRV_MASK   (0x00000020u)

Definition at line 6341 of file regs.h.

#define SC_SPIRXOVF   (0x00000001u)

Definition at line 6215 of file regs.h.

#define SC_SPIRXOVF   (0x00000001u)

Definition at line 6215 of file regs.h.

#define SC_SPIRXOVF_BIT   (0)

Definition at line 6217 of file regs.h.

#define SC_SPIRXOVF_BIT   (0)

Definition at line 6217 of file regs.h.

#define SC_SPIRXOVF_BITS   (1)

Definition at line 6218 of file regs.h.

#define SC_SPIRXOVF_BITS   (1)

Definition at line 6218 of file regs.h.

#define SC_SPIRXOVF_MASK   (0x00000001u)

Definition at line 6216 of file regs.h.

#define SC_SPIRXOVF_MASK   (0x00000001u)

Definition at line 6216 of file regs.h.

#define SC_SPIRXVAL   (0x00000002u)

Definition at line 6210 of file regs.h.

#define SC_SPIRXVAL   (0x00000002u)

Definition at line 6210 of file regs.h.

#define SC_SPIRXVAL_BIT   (1)

Definition at line 6212 of file regs.h.

#define SC_SPIRXVAL_BIT   (1)

Definition at line 6212 of file regs.h.

#define SC_SPIRXVAL_BITS   (1)

Definition at line 6213 of file regs.h.

#define SC_SPIRXVAL_BITS   (1)

Definition at line 6213 of file regs.h.

#define SC_SPIRXVAL_MASK   (0x00000002u)

Definition at line 6211 of file regs.h.

#define SC_SPIRXVAL_MASK   (0x00000002u)

Definition at line 6211 of file regs.h.

#define SC_SPITXFREE   (0x00000004u)

Definition at line 6205 of file regs.h.

#define SC_SPITXFREE   (0x00000004u)

Definition at line 6205 of file regs.h.

#define SC_SPITXFREE_BIT   (2)

Definition at line 6207 of file regs.h.

#define SC_SPITXFREE_BIT   (2)

Definition at line 6207 of file regs.h.

#define SC_SPITXFREE_BITS   (1)

Definition at line 6208 of file regs.h.

#define SC_SPITXFREE_BITS   (1)

Definition at line 6208 of file regs.h.

#define SC_SPITXFREE_MASK   (0x00000004u)

Definition at line 6206 of file regs.h.

#define SC_SPITXFREE_MASK   (0x00000004u)

Definition at line 6206 of file regs.h.

#define SC_SPITXIDLE   (0x00000008u)

Definition at line 6200 of file regs.h.

#define SC_SPITXIDLE   (0x00000008u)

Definition at line 6200 of file regs.h.

#define SC_SPITXIDLE_BIT   (3)

Definition at line 6202 of file regs.h.

#define SC_SPITXIDLE_BIT   (3)

Definition at line 6202 of file regs.h.

#define SC_SPITXIDLE_BITS   (1)

Definition at line 6203 of file regs.h.

#define SC_SPITXIDLE_BITS   (1)

Definition at line 6203 of file regs.h.

#define SC_SPITXIDLE_MASK   (0x00000008u)

Definition at line 6201 of file regs.h.

#define SC_SPITXIDLE_MASK   (0x00000008u)

Definition at line 6201 of file regs.h.

#define SC_TWIACK   (0x00000001u)

Definition at line 6315 of file regs.h.

#define SC_TWIACK   (0x00000001u)

Definition at line 6315 of file regs.h.

#define SC_TWIACK_BIT   (0)

Definition at line 6317 of file regs.h.

#define SC_TWIACK_BIT   (0)

Definition at line 6317 of file regs.h.

#define SC_TWIACK_BITS   (1)

Definition at line 6318 of file regs.h.

#define SC_TWIACK_BITS   (1)

Definition at line 6318 of file regs.h.

#define SC_TWIACK_MASK   (0x00000001u)

Definition at line 6316 of file regs.h.

#define SC_TWIACK_MASK   (0x00000001u)

Definition at line 6316 of file regs.h.

#define SC_TWICMDFIN   (0x00000008u)

Definition at line 6225 of file regs.h.

#define SC_TWICMDFIN   (0x00000008u)

Definition at line 6225 of file regs.h.

#define SC_TWICMDFIN_BIT   (3)

Definition at line 6227 of file regs.h.

#define SC_TWICMDFIN_BIT   (3)

Definition at line 6227 of file regs.h.

#define SC_TWICMDFIN_BITS   (1)

Definition at line 6228 of file regs.h.

#define SC_TWICMDFIN_BITS   (1)

Definition at line 6228 of file regs.h.

#define SC_TWICMDFIN_MASK   (0x00000008u)

Definition at line 6226 of file regs.h.

#define SC_TWICMDFIN_MASK   (0x00000008u)

Definition at line 6226 of file regs.h.

#define SC_TWIRECV   (0x00000001u)

Definition at line 6305 of file regs.h.

#define SC_TWIRECV   (0x00000001u)

Definition at line 6305 of file regs.h.

#define SC_TWIRECV_BIT   (0)

Definition at line 6307 of file regs.h.

#define SC_TWIRECV_BIT   (0)

Definition at line 6307 of file regs.h.

#define SC_TWIRECV_BITS   (1)

Definition at line 6308 of file regs.h.

#define SC_TWIRECV_BITS   (1)

Definition at line 6308 of file regs.h.

#define SC_TWIRECV_MASK   (0x00000001u)

Definition at line 6306 of file regs.h.

#define SC_TWIRECV_MASK   (0x00000001u)

Definition at line 6306 of file regs.h.

#define SC_TWIRXFIN   (0x00000004u)

Definition at line 6230 of file regs.h.

#define SC_TWIRXFIN   (0x00000004u)

Definition at line 6230 of file regs.h.

#define SC_TWIRXFIN_BIT   (2)

Definition at line 6232 of file regs.h.

#define SC_TWIRXFIN_BIT   (2)

Definition at line 6232 of file regs.h.

#define SC_TWIRXFIN_BITS   (1)

Definition at line 6233 of file regs.h.

#define SC_TWIRXFIN_BITS   (1)

Definition at line 6233 of file regs.h.

#define SC_TWIRXFIN_MASK   (0x00000004u)

Definition at line 6231 of file regs.h.

#define SC_TWIRXFIN_MASK   (0x00000004u)

Definition at line 6231 of file regs.h.

#define SC_TWIRXNAK   (0x00000001u)

Definition at line 6240 of file regs.h.

#define SC_TWIRXNAK   (0x00000001u)

Definition at line 6240 of file regs.h.

#define SC_TWIRXNAK_BIT   (0)

Definition at line 6242 of file regs.h.

#define SC_TWIRXNAK_BIT   (0)

Definition at line 6242 of file regs.h.

#define SC_TWIRXNAK_BITS   (1)

Definition at line 6243 of file regs.h.

#define SC_TWIRXNAK_BITS   (1)

Definition at line 6243 of file regs.h.

#define SC_TWIRXNAK_MASK   (0x00000001u)

Definition at line 6241 of file regs.h.

#define SC_TWIRXNAK_MASK   (0x00000001u)

Definition at line 6241 of file regs.h.

#define SC_TWISEND   (0x00000002u)

Definition at line 6300 of file regs.h.

#define SC_TWISEND   (0x00000002u)

Definition at line 6300 of file regs.h.

#define SC_TWISEND_BIT   (1)

Definition at line 6302 of file regs.h.

#define SC_TWISEND_BIT   (1)

Definition at line 6302 of file regs.h.

#define SC_TWISEND_BITS   (1)

Definition at line 6303 of file regs.h.

#define SC_TWISEND_BITS   (1)

Definition at line 6303 of file regs.h.

#define SC_TWISEND_MASK   (0x00000002u)

Definition at line 6301 of file regs.h.

#define SC_TWISEND_MASK   (0x00000002u)

Definition at line 6301 of file regs.h.

#define SC_TWISTART   (0x00000004u)

Definition at line 6295 of file regs.h.

#define SC_TWISTART   (0x00000004u)

Definition at line 6295 of file regs.h.

#define SC_TWISTART_BIT   (2)

Definition at line 6297 of file regs.h.

#define SC_TWISTART_BIT   (2)

Definition at line 6297 of file regs.h.

#define SC_TWISTART_BITS   (1)

Definition at line 6298 of file regs.h.

#define SC_TWISTART_BITS   (1)

Definition at line 6298 of file regs.h.

#define SC_TWISTART_MASK   (0x00000004u)

Definition at line 6296 of file regs.h.

#define SC_TWISTART_MASK   (0x00000004u)

Definition at line 6296 of file regs.h.

#define SC_TWISTOP   (0x00000008u)

Definition at line 6290 of file regs.h.

#define SC_TWISTOP   (0x00000008u)

Definition at line 6290 of file regs.h.

#define SC_TWISTOP_BIT   (3)

Definition at line 6292 of file regs.h.

#define SC_TWISTOP_BIT   (3)

Definition at line 6292 of file regs.h.

#define SC_TWISTOP_BITS   (1)

Definition at line 6293 of file regs.h.

#define SC_TWISTOP_BITS   (1)

Definition at line 6293 of file regs.h.

#define SC_TWISTOP_MASK   (0x00000008u)

Definition at line 6291 of file regs.h.

#define SC_TWISTOP_MASK   (0x00000008u)

Definition at line 6291 of file regs.h.

#define SC_TWITXFIN   (0x00000002u)

Definition at line 6235 of file regs.h.

#define SC_TWITXFIN   (0x00000002u)

Definition at line 6235 of file regs.h.

#define SC_TWITXFIN_BIT   (1)

Definition at line 6237 of file regs.h.

#define SC_TWITXFIN_BIT   (1)

Definition at line 6237 of file regs.h.

#define SC_TWITXFIN_BITS   (1)

Definition at line 6238 of file regs.h.

#define SC_TWITXFIN_BITS   (1)

Definition at line 6238 of file regs.h.

#define SC_TWITXFIN_MASK   (0x00000002u)

Definition at line 6236 of file regs.h.

#define SC_TWITXFIN_MASK   (0x00000002u)

Definition at line 6236 of file regs.h.

#define SC_TXACTA   (0x00000004u)

Definition at line 6115 of file regs.h.

#define SC_TXACTA   (0x00000004u)

Definition at line 6115 of file regs.h.

#define SC_TXACTA_BIT   (2)

Definition at line 6117 of file regs.h.

#define SC_TXACTA_BIT   (2)

Definition at line 6117 of file regs.h.

#define SC_TXACTA_BITS   (1)

Definition at line 6118 of file regs.h.

#define SC_TXACTA_BITS   (1)

Definition at line 6118 of file regs.h.

#define SC_TXACTA_MASK   (0x00000004u)

Definition at line 6116 of file regs.h.

#define SC_TXACTA_MASK   (0x00000004u)

Definition at line 6116 of file regs.h.

#define SC_TXACTB   (0x00000008u)

Definition at line 6110 of file regs.h.

#define SC_TXACTB   (0x00000008u)

Definition at line 6110 of file regs.h.

#define SC_TXACTB_BIT   (3)

Definition at line 6112 of file regs.h.

#define SC_TXACTB_BIT   (3)

Definition at line 6112 of file regs.h.

#define SC_TXACTB_BITS   (1)

Definition at line 6113 of file regs.h.

#define SC_TXACTB_BITS   (1)

Definition at line 6113 of file regs.h.

#define SC_TXACTB_MASK   (0x00000008u)

Definition at line 6111 of file regs.h.

#define SC_TXACTB_MASK   (0x00000008u)

Definition at line 6111 of file regs.h.

#define SC_TXBEGA   (0x00001FFFu)

Definition at line 5990 of file regs.h.

#define SC_TXBEGA   (0x00001FFFu)

Definition at line 5990 of file regs.h.

#define SC_TXBEGA_BIT   (0)

Definition at line 5992 of file regs.h.

#define SC_TXBEGA_BIT   (0)

Definition at line 5992 of file regs.h.

#define SC_TXBEGA_BITS   (13)

Definition at line 5993 of file regs.h.

#define SC_TXBEGA_BITS   (13)

Definition at line 5993 of file regs.h.

#define SC_TXBEGA_MASK   (0x00001FFFu)

Definition at line 5991 of file regs.h.

#define SC_TXBEGA_MASK   (0x00001FFFu)

Definition at line 5991 of file regs.h.

#define SC_TXBEGB   (0x00001FFFu)

Definition at line 6020 of file regs.h.

#define SC_TXBEGB   (0x00001FFFu)

Definition at line 6020 of file regs.h.

#define SC_TXBEGB_BIT   (0)

Definition at line 6022 of file regs.h.

#define SC_TXBEGB_BIT   (0)

Definition at line 6022 of file regs.h.

#define SC_TXBEGB_BITS   (13)

Definition at line 6023 of file regs.h.

#define SC_TXBEGB_BITS   (13)

Definition at line 6023 of file regs.h.

#define SC_TXBEGB_MASK   (0x00001FFFu)

Definition at line 6021 of file regs.h.

#define SC_TXBEGB_MASK   (0x00001FFFu)

Definition at line 6021 of file regs.h.

#define SC_TXCNT   (0x00001FFFu)

Definition at line 6065 of file regs.h.

#define SC_TXCNT   (0x00001FFFu)

Definition at line 6065 of file regs.h.

#define SC_TXCNT_BIT   (0)

Definition at line 6067 of file regs.h.

#define SC_TXCNT_BIT   (0)

Definition at line 6067 of file regs.h.

#define SC_TXCNT_BITS   (13)

Definition at line 6068 of file regs.h.

#define SC_TXCNT_BITS   (13)

Definition at line 6068 of file regs.h.

#define SC_TXCNT_MASK   (0x00001FFFu)

Definition at line 6066 of file regs.h.

#define SC_TXCNT_MASK   (0x00001FFFu)

Definition at line 6066 of file regs.h.

#define SC_TXDMARST   (0x00000020u)

Definition at line 6135 of file regs.h.

#define SC_TXDMARST   (0x00000020u)

Definition at line 6135 of file regs.h.

#define SC_TXDMARST_BIT   (5)

Definition at line 6137 of file regs.h.

#define SC_TXDMARST_BIT   (5)

Definition at line 6137 of file regs.h.

#define SC_TXDMARST_BITS   (1)

Definition at line 6138 of file regs.h.

#define SC_TXDMARST_BITS   (1)

Definition at line 6138 of file regs.h.

#define SC_TXDMARST_MASK   (0x00000020u)

Definition at line 6136 of file regs.h.

#define SC_TXDMARST_MASK   (0x00000020u)

Definition at line 6136 of file regs.h.

#define SC_TXENDA   (0x00001FFFu)

Definition at line 6005 of file regs.h.

#define SC_TXENDA   (0x00001FFFu)

Definition at line 6005 of file regs.h.

#define SC_TXENDA_BIT   (0)

Definition at line 6007 of file regs.h.

#define SC_TXENDA_BIT   (0)

Definition at line 6007 of file regs.h.

#define SC_TXENDA_BITS   (13)

Definition at line 6008 of file regs.h.

#define SC_TXENDA_BITS   (13)

Definition at line 6008 of file regs.h.

#define SC_TXENDA_MASK   (0x00001FFFu)

Definition at line 6006 of file regs.h.

#define SC_TXENDA_MASK   (0x00001FFFu)

Definition at line 6006 of file regs.h.

#define SC_TXENDB   (0x00001FFFu)

Definition at line 6035 of file regs.h.

#define SC_TXENDB   (0x00001FFFu)

Definition at line 6035 of file regs.h.

#define SC_TXENDB_BIT   (0)

Definition at line 6037 of file regs.h.

#define SC_TXENDB_BIT   (0)

Definition at line 6037 of file regs.h.

#define SC_TXENDB_BITS   (13)

Definition at line 6038 of file regs.h.

#define SC_TXENDB_BITS   (13)

Definition at line 6038 of file regs.h.

#define SC_TXENDB_MASK   (0x00001FFFu)

Definition at line 6036 of file regs.h.

#define SC_TXENDB_MASK   (0x00001FFFu)

Definition at line 6036 of file regs.h.

#define SC_TXFREELEVEL   (0x00000002u)

Definition at line 4485 of file regs.h.

#define SC_TXFREELEVEL   (0x00000002u)

Definition at line 4485 of file regs.h.

#define SC_TXFREELEVEL_BIT   (1)

Definition at line 4487 of file regs.h.

#define SC_TXFREELEVEL_BIT   (1)

Definition at line 4487 of file regs.h.

#define SC_TXFREELEVEL_BITS   (1)

Definition at line 4488 of file regs.h.

#define SC_TXFREELEVEL_BITS   (1)

Definition at line 4488 of file regs.h.

#define SC_TXFREELEVEL_MASK   (0x00000002u)

Definition at line 4486 of file regs.h.

#define SC_TXFREELEVEL_MASK   (0x00000002u)

Definition at line 4486 of file regs.h.

#define SC_TXIDLELEVEL   (0x00000004u)

Definition at line 4480 of file regs.h.

#define SC_TXIDLELEVEL   (0x00000004u)

Definition at line 4480 of file regs.h.

#define SC_TXIDLELEVEL_BIT   (2)

Definition at line 4482 of file regs.h.

#define SC_TXIDLELEVEL_BIT   (2)

Definition at line 4482 of file regs.h.

#define SC_TXIDLELEVEL_BITS   (1)

Definition at line 4483 of file regs.h.

#define SC_TXIDLELEVEL_BITS   (1)

Definition at line 4483 of file regs.h.

#define SC_TXIDLELEVEL_MASK   (0x00000004u)

Definition at line 4481 of file regs.h.

#define SC_TXIDLELEVEL_MASK   (0x00000004u)

Definition at line 4481 of file regs.h.

#define SC_TXLODA   (0x00000004u)

Definition at line 6150 of file regs.h.

#define SC_TXLODA   (0x00000004u)

Definition at line 6150 of file regs.h.

#define SC_TXLODA_BIT   (2)

Definition at line 6152 of file regs.h.

#define SC_TXLODA_BIT   (2)

Definition at line 6152 of file regs.h.

#define SC_TXLODA_BITS   (1)

Definition at line 6153 of file regs.h.

#define SC_TXLODA_BITS   (1)

Definition at line 6153 of file regs.h.

#define SC_TXLODA_MASK   (0x00000004u)

Definition at line 6151 of file regs.h.

#define SC_TXLODA_MASK   (0x00000004u)

Definition at line 6151 of file regs.h.

#define SC_TXLODB   (0x00000008u)

Definition at line 6145 of file regs.h.

#define SC_TXLODB   (0x00000008u)

Definition at line 6145 of file regs.h.

#define SC_TXLODB_BIT   (3)

Definition at line 6147 of file regs.h.

#define SC_TXLODB_BIT   (3)

Definition at line 6147 of file regs.h.

#define SC_TXLODB_BITS   (1)

Definition at line 6148 of file regs.h.

#define SC_TXLODB_BITS   (1)

Definition at line 6148 of file regs.h.

#define SC_TXLODB_MASK   (0x00000008u)

Definition at line 6146 of file regs.h.

#define SC_TXLODB_MASK   (0x00000008u)

Definition at line 6146 of file regs.h.

#define SC_UART2STP   (0x00000004u)

Definition at line 6395 of file regs.h.

#define SC_UART2STP_BIT   (2)

Definition at line 6397 of file regs.h.

#define SC_UART2STP_BITS   (1)

Definition at line 6398 of file regs.h.

#define SC_UART2STP_MASK   (0x00000004u)

Definition at line 6396 of file regs.h.

#define SC_UART8BIT   (0x00000002u)

Definition at line 6400 of file regs.h.

#define SC_UART8BIT_BIT   (1)

Definition at line 6402 of file regs.h.

#define SC_UART8BIT_BITS   (1)

Definition at line 6403 of file regs.h.

#define SC_UART8BIT_MASK   (0x00000002u)

Definition at line 6401 of file regs.h.

#define SC_UARTAUTO   (0x00000040u)

Definition at line 6375 of file regs.h.

#define SC_UARTAUTO_BIT   (6)

Definition at line 6377 of file regs.h.

#define SC_UARTAUTO_BITS   (1)

Definition at line 6378 of file regs.h.

#define SC_UARTAUTO_MASK   (0x00000040u)

Definition at line 6376 of file regs.h.

#define SC_UARTCTS   (0x00000001u)

Definition at line 6280 of file regs.h.

#define SC_UARTCTS_BIT   (0)

Definition at line 6282 of file regs.h.

#define SC_UARTCTS_BITS   (1)

Definition at line 6283 of file regs.h.

#define SC_UARTCTS_MASK   (0x00000001u)

Definition at line 6281 of file regs.h.

#define SC_UARTFLOW   (0x00000020u)

Definition at line 6380 of file regs.h.

#define SC_UARTFLOW_BIT   (5)

Definition at line 6382 of file regs.h.

#define SC_UARTFLOW_BITS   (1)

Definition at line 6383 of file regs.h.

#define SC_UARTFLOW_MASK   (0x00000020u)

Definition at line 6381 of file regs.h.

#define SC_UARTFRAC   (0x00000001u)

Definition at line 6445 of file regs.h.

#define SC_UARTFRAC_BIT   (0)

Definition at line 6447 of file regs.h.

#define SC_UARTFRAC_BITS   (1)

Definition at line 6448 of file regs.h.

#define SC_UARTFRAC_MASK   (0x00000001u)

Definition at line 6446 of file regs.h.

#define SC_UARTFRMERR   (0x00000010u)

Definition at line 6260 of file regs.h.

#define SC_UARTFRMERR_BIT   (4)

Definition at line 6262 of file regs.h.

#define SC_UARTFRMERR_BITS   (1)

Definition at line 6263 of file regs.h.

#define SC_UARTFRMERR_MASK   (0x00000010u)

Definition at line 6261 of file regs.h.

#define SC_UARTODD   (0x00000010u)

Definition at line 6385 of file regs.h.

#define SC_UARTODD_BIT   (4)

Definition at line 6387 of file regs.h.

#define SC_UARTODD_BITS   (1)

Definition at line 6388 of file regs.h.

#define SC_UARTODD_MASK   (0x00000010u)

Definition at line 6386 of file regs.h.

#define SC_UARTPAR   (0x00000008u)

Definition at line 6390 of file regs.h.

#define SC_UARTPAR_BIT   (3)

Definition at line 6392 of file regs.h.

#define SC_UARTPAR_BITS   (1)

Definition at line 6393 of file regs.h.

#define SC_UARTPAR_MASK   (0x00000008u)

Definition at line 6391 of file regs.h.

#define SC_UARTPARERR   (0x00000020u)

Definition at line 6255 of file regs.h.

#define SC_UARTPARERR_BIT   (5)

Definition at line 6257 of file regs.h.

#define SC_UARTPARERR_BITS   (1)

Definition at line 6258 of file regs.h.

#define SC_UARTPARERR_MASK   (0x00000020u)

Definition at line 6256 of file regs.h.

#define SC_UARTPER   (0x0000FFFFu)

Definition at line 6435 of file regs.h.

#define SC_UARTPER_BIT   (0)

Definition at line 6437 of file regs.h.

#define SC_UARTPER_BITS   (16)

Definition at line 6438 of file regs.h.

#define SC_UARTPER_MASK   (0x0000FFFFu)

Definition at line 6436 of file regs.h.

#define SC_UARTRTS   (0x00000001u)

Definition at line 6405 of file regs.h.

#define SC_UARTRTS_BIT   (0)

Definition at line 6407 of file regs.h.

#define SC_UARTRTS_BITS   (1)

Definition at line 6408 of file regs.h.

#define SC_UARTRTS_MASK   (0x00000001u)

Definition at line 6406 of file regs.h.

#define SC_UARTRXOVF   (0x00000008u)

Definition at line 6265 of file regs.h.

#define SC_UARTRXOVF_BIT   (3)

Definition at line 6267 of file regs.h.

#define SC_UARTRXOVF_BITS   (1)

Definition at line 6268 of file regs.h.

#define SC_UARTRXOVF_MASK   (0x00000008u)

Definition at line 6266 of file regs.h.

#define SC_UARTRXVAL   (0x00000002u)

Definition at line 6275 of file regs.h.

#define SC_UARTRXVAL_BIT   (1)

Definition at line 6277 of file regs.h.

#define SC_UARTRXVAL_BITS   (1)

Definition at line 6278 of file regs.h.

#define SC_UARTRXVAL_MASK   (0x00000002u)

Definition at line 6276 of file regs.h.

#define SC_UARTTXFREE   (0x00000004u)

Definition at line 6270 of file regs.h.

#define SC_UARTTXFREE_BIT   (2)

Definition at line 6272 of file regs.h.

#define SC_UARTTXFREE_BITS   (1)

Definition at line 6273 of file regs.h.

#define SC_UARTTXFREE_MASK   (0x00000004u)

Definition at line 6271 of file regs.h.

#define SC_UARTTXIDLE   (0x00000040u)

Definition at line 6250 of file regs.h.

#define SC_UARTTXIDLE_BIT   (6)

Definition at line 6252 of file regs.h.

#define SC_UARTTXIDLE_BITS   (1)

Definition at line 6253 of file regs.h.

#define SC_UARTTXIDLE_MASK   (0x00000040u)

Definition at line 6251 of file regs.h.

#define SCR_ADDR   *((volatile int32u *)0x400010F0u)

Definition at line 1270 of file regs.h.

#define SCR_ADDR_ADDR   (0x400010F0u)

Definition at line 1272 of file regs.h.

#define SCR_ADDR_REG   *((volatile int32u *)0x400010F0u)

Definition at line 1271 of file regs.h.

#define SCR_ADDR_RESET   (0x00000000u)

Definition at line 1273 of file regs.h.

#define SCR_ADDR_SCR_ADDR   (0x000000FFu)

Definition at line 1275 of file regs.h.

#define SCR_ADDR_SCR_ADDR_BIT   (0)

Definition at line 1277 of file regs.h.

#define SCR_ADDR_SCR_ADDR_BITS   (8)

Definition at line 1278 of file regs.h.

#define SCR_ADDR_SCR_ADDR_MASK   (0x000000FFu)

Definition at line 1276 of file regs.h.

#define SCR_BUSY   *((volatile int32u *)0x400010ECu)

Definition at line 1260 of file regs.h.

#define SCR_BUSY_ADDR   (0x400010ECu)

Definition at line 1262 of file regs.h.

#define SCR_BUSY_REG   *((volatile int32u *)0x400010ECu)

Definition at line 1261 of file regs.h.

#define SCR_BUSY_RESET   (0x00000000u)

Definition at line 1263 of file regs.h.

#define SCR_BUSY_SCR_BUSY   (0x00000001u)

Definition at line 1265 of file regs.h.

#define SCR_BUSY_SCR_BUSY_BIT   (0)

Definition at line 1267 of file regs.h.

#define SCR_BUSY_SCR_BUSY_BITS   (1)

Definition at line 1268 of file regs.h.

#define SCR_BUSY_SCR_BUSY_MASK   (0x00000001u)

Definition at line 1266 of file regs.h.

#define SCR_CTRL   *((volatile int32u *)0x400010E8u)

Definition at line 1240 of file regs.h.

#define SCR_CTRL_ADDR   (0x400010E8u)

Definition at line 1242 of file regs.h.

#define SCR_CTRL_REG   *((volatile int32u *)0x400010E8u)

Definition at line 1241 of file regs.h.

#define SCR_CTRL_RESET   (0x00000004u)

Definition at line 1243 of file regs.h.

#define SCR_CTRL_SCR_READ   (0x00000001u)

Definition at line 1255 of file regs.h.

#define SCR_CTRL_SCR_READ_BIT   (0)

Definition at line 1257 of file regs.h.

#define SCR_CTRL_SCR_READ_BITS   (1)

Definition at line 1258 of file regs.h.

#define SCR_CTRL_SCR_READ_MASK   (0x00000001u)

Definition at line 1256 of file regs.h.

#define SCR_CTRL_SCR_RESET   (0x00000004u)

Definition at line 1245 of file regs.h.

#define SCR_CTRL_SCR_RESET_BIT   (2)

Definition at line 1247 of file regs.h.

#define SCR_CTRL_SCR_RESET_BITS   (1)

Definition at line 1248 of file regs.h.

#define SCR_CTRL_SCR_RESET_MASK   (0x00000004u)

Definition at line 1246 of file regs.h.

#define SCR_CTRL_SCR_WRITE   (0x00000002u)

Definition at line 1250 of file regs.h.

#define SCR_CTRL_SCR_WRITE_BIT   (1)

Definition at line 1252 of file regs.h.

#define SCR_CTRL_SCR_WRITE_BITS   (1)

Definition at line 1253 of file regs.h.

#define SCR_CTRL_SCR_WRITE_MASK   (0x00000002u)

Definition at line 1251 of file regs.h.

#define SCR_READ   *((volatile int32u *)0x400010F8u)

Definition at line 1290 of file regs.h.

#define SCR_READ_ADDR   (0x400010F8u)

Definition at line 1292 of file regs.h.

#define SCR_READ_REG   *((volatile int32u *)0x400010F8u)

Definition at line 1291 of file regs.h.

#define SCR_READ_RESET   (0x00000000u)

Definition at line 1293 of file regs.h.

#define SCR_READ_SCR_READ   (0x0000FFFFu)

Definition at line 1295 of file regs.h.

#define SCR_READ_SCR_READ_BIT   (0)

Definition at line 1297 of file regs.h.

#define SCR_READ_SCR_READ_BITS   (16)

Definition at line 1298 of file regs.h.

#define SCR_READ_SCR_READ_MASK   (0x0000FFFFu)

Definition at line 1296 of file regs.h.

#define SCR_WRITE   *((volatile int32u *)0x400010F4u)

Definition at line 1280 of file regs.h.

#define SCR_WRITE_ADDR   (0x400010F4u)

Definition at line 1282 of file regs.h.

#define SCR_WRITE_REG   *((volatile int32u *)0x400010F4u)

Definition at line 1281 of file regs.h.

#define SCR_WRITE_RESET   (0x00000000u)

Definition at line 1283 of file regs.h.

#define SCR_WRITE_SCR_WRITE   (0x0000FFFFu)

Definition at line 1285 of file regs.h.

#define SCR_WRITE_SCR_WRITE_BIT   (0)

Definition at line 1287 of file regs.h.

#define SCR_WRITE_SCR_WRITE_BITS   (16)

Definition at line 1288 of file regs.h.

#define SCR_WRITE_SCR_WRITE_MASK   (0x0000FFFFu)

Definition at line 1286 of file regs.h.

#define SCS_AFR0   *((volatile int32u *)0xE000ED4Cu)

Definition at line 10405 of file regs.h.

#define SCS_AFR0_ADDR   (0xE000ED4Cu)

Definition at line 10407 of file regs.h.

#define SCS_AFR0_FEATURE   (0xFFFFFFFFu)

Definition at line 10410 of file regs.h.

#define SCS_AFR0_FEATURE_BIT   (0)

Definition at line 10412 of file regs.h.

#define SCS_AFR0_FEATURE_BITS   (32)

Definition at line 10413 of file regs.h.

#define SCS_AFR0_FEATURE_MASK   (0xFFFFFFFFu)

Definition at line 10411 of file regs.h.

#define SCS_AFR0_REG   *((volatile int32u *)0xE000ED4Cu)

Definition at line 10406 of file regs.h.

#define SCS_AFR0_RESET   (0x00000000u)

Definition at line 10408 of file regs.h.

#define SCS_AFSR   *((volatile int32u *)0xE000ED3Cu)

Definition at line 10350 of file regs.h.

#define SCS_AFSR_ADDR   (0xE000ED3Cu)

Definition at line 10352 of file regs.h.

#define SCS_AFSR_MISSED   (0x00000001u)

Definition at line 10370 of file regs.h.

#define SCS_AFSR_MISSED_BIT   (0)

Definition at line 10372 of file regs.h.

#define SCS_AFSR_MISSED_BITS   (1)

Definition at line 10373 of file regs.h.

#define SCS_AFSR_MISSED_MASK   (0x00000001u)

Definition at line 10371 of file regs.h.

#define SCS_AFSR_PROTECTED   (0x00000004u)

Definition at line 10360 of file regs.h.

#define SCS_AFSR_PROTECTED_BIT   (2)

Definition at line 10362 of file regs.h.

#define SCS_AFSR_PROTECTED_BITS   (1)

Definition at line 10363 of file regs.h.

#define SCS_AFSR_PROTECTED_MASK   (0x00000004u)

Definition at line 10361 of file regs.h.

#define SCS_AFSR_REG   *((volatile int32u *)0xE000ED3Cu)

Definition at line 10351 of file regs.h.

#define SCS_AFSR_RESERVED   (0x00000002u)

Definition at line 10365 of file regs.h.

#define SCS_AFSR_RESERVED_BIT   (1)

Definition at line 10367 of file regs.h.

#define SCS_AFSR_RESERVED_BITS   (1)

Definition at line 10368 of file regs.h.

#define SCS_AFSR_RESERVED_MASK   (0x00000002u)

Definition at line 10366 of file regs.h.

#define SCS_AFSR_RESET   (0x00000000u)

Definition at line 10353 of file regs.h.

#define SCS_AFSR_WRONGSIZE   (0x00000008u)

Definition at line 10355 of file regs.h.

#define SCS_AFSR_WRONGSIZE_BIT   (3)

Definition at line 10357 of file regs.h.

#define SCS_AFSR_WRONGSIZE_BITS   (1)

Definition at line 10358 of file regs.h.

#define SCS_AFSR_WRONGSIZE_MASK   (0x00000008u)

Definition at line 10356 of file regs.h.

#define SCS_AIRCR   *((volatile int32u *)0xE000ED0Cu)

Definition at line 9945 of file regs.h.

#define SCS_AIRCR_ADDR   (0xE000ED0Cu)

Definition at line 9947 of file regs.h.

#define SCS_AIRCR_ENDIANESS   (0x00008000u)

Definition at line 9960 of file regs.h.

#define SCS_AIRCR_ENDIANESS_BIT   (15)

Definition at line 9962 of file regs.h.

#define SCS_AIRCR_ENDIANESS_BITS   (1)

Definition at line 9963 of file regs.h.

#define SCS_AIRCR_ENDIANESS_MASK   (0x00008000u)

Definition at line 9961 of file regs.h.

#define SCS_AIRCR_PRIGROUP   (0x00000700u)

Definition at line 9965 of file regs.h.

#define SCS_AIRCR_PRIGROUP_BIT   (8)

Definition at line 9967 of file regs.h.

#define SCS_AIRCR_PRIGROUP_BITS   (3)

Definition at line 9968 of file regs.h.

#define SCS_AIRCR_PRIGROUP_MASK   (0x00000700u)

Definition at line 9966 of file regs.h.

#define SCS_AIRCR_REG   *((volatile int32u *)0xE000ED0Cu)

Definition at line 9946 of file regs.h.

#define SCS_AIRCR_RESET   (0x00000000u)

Definition at line 9948 of file regs.h.

#define SCS_AIRCR_SYSRESETREQ   (0x00000004u)

Definition at line 9970 of file regs.h.

#define SCS_AIRCR_SYSRESETREQ_BIT   (2)

Definition at line 9972 of file regs.h.

#define SCS_AIRCR_SYSRESETREQ_BITS   (1)

Definition at line 9973 of file regs.h.

#define SCS_AIRCR_SYSRESETREQ_MASK   (0x00000004u)

Definition at line 9971 of file regs.h.

#define SCS_AIRCR_VECTCLRACTIVE   (0x00000002u)

Definition at line 9975 of file regs.h.

#define SCS_AIRCR_VECTCLRACTIVE_BIT   (1)

Definition at line 9977 of file regs.h.

#define SCS_AIRCR_VECTCLRACTIVE_BITS   (1)

Definition at line 9978 of file regs.h.

#define SCS_AIRCR_VECTCLRACTIVE_MASK   (0x00000002u)

Definition at line 9976 of file regs.h.

#define SCS_AIRCR_VECTKEY   (0xFFFF0000u)

Definition at line 9955 of file regs.h.

#define SCS_AIRCR_VECTKEY_BIT   (16)

Definition at line 9957 of file regs.h.

#define SCS_AIRCR_VECTKEY_BITS   (16)

Definition at line 9958 of file regs.h.

#define SCS_AIRCR_VECTKEY_MASK   (0xFFFF0000u)

Definition at line 9956 of file regs.h.

#define SCS_AIRCR_VECTKEYSTAT   (0xFFFF0000u)

Definition at line 9950 of file regs.h.

#define SCS_AIRCR_VECTKEYSTAT_BIT   (16)

Definition at line 9952 of file regs.h.

#define SCS_AIRCR_VECTKEYSTAT_BITS   (16)

Definition at line 9953 of file regs.h.

#define SCS_AIRCR_VECTKEYSTAT_MASK   (0xFFFF0000u)

Definition at line 9951 of file regs.h.

#define SCS_AIRCR_VECTRESET   (0x00000001u)

Definition at line 9980 of file regs.h.

#define SCS_AIRCR_VECTRESET_BIT   (0)

Definition at line 9982 of file regs.h.

#define SCS_AIRCR_VECTRESET_BITS   (1)

Definition at line 9983 of file regs.h.

#define SCS_AIRCR_VECTRESET_MASK   (0x00000001u)

Definition at line 9981 of file regs.h.

#define SCS_BFAR   *((volatile int32u *)0xE000ED38u)

Definition at line 10340 of file regs.h.

#define SCS_BFAR_ADDR   (0xE000ED38u)

Definition at line 10342 of file regs.h.

#define SCS_BFAR_ADDRESS   (0xFFFFFFFFu)

Definition at line 10345 of file regs.h.

#define SCS_BFAR_ADDRESS_BIT   (0)

Definition at line 10347 of file regs.h.

#define SCS_BFAR_ADDRESS_BITS   (32)

Definition at line 10348 of file regs.h.

#define SCS_BFAR_ADDRESS_MASK   (0xFFFFFFFFu)

Definition at line 10346 of file regs.h.

#define SCS_BFAR_REG   *((volatile int32u *)0xE000ED38u)

Definition at line 10341 of file regs.h.

#define SCS_BFAR_RESET   (0x00000000u)

Definition at line 10343 of file regs.h.

#define SCS_CCR   *((volatile int32u *)0xE000ED14u)

Definition at line 10005 of file regs.h.

#define SCS_CCR_ADDR   (0xE000ED14u)

Definition at line 10007 of file regs.h.

#define SCS_CCR_BFHFNMIGN   (0x00000100u)

Definition at line 10015 of file regs.h.

#define SCS_CCR_BFHFNMIGN_BIT   (8)

Definition at line 10017 of file regs.h.

#define SCS_CCR_BFHFNMIGN_BITS   (1)

Definition at line 10018 of file regs.h.

#define SCS_CCR_BFHFNMIGN_MASK   (0x00000100u)

Definition at line 10016 of file regs.h.

#define SCS_CCR_DIV_0_TRP   (0x00000010u)

Definition at line 10020 of file regs.h.

#define SCS_CCR_DIV_0_TRP_BIT   (4)

Definition at line 10022 of file regs.h.

#define SCS_CCR_DIV_0_TRP_BITS   (1)

Definition at line 10023 of file regs.h.

#define SCS_CCR_DIV_0_TRP_MASK   (0x00000010u)

Definition at line 10021 of file regs.h.

#define SCS_CCR_NONBASETHRDENA   (0x00000001u)

Definition at line 10035 of file regs.h.

#define SCS_CCR_NONBASETHRDENA_BIT   (0)

Definition at line 10037 of file regs.h.

#define SCS_CCR_NONBASETHRDENA_BITS   (1)

Definition at line 10038 of file regs.h.

#define SCS_CCR_NONBASETHRDENA_MASK   (0x00000001u)

Definition at line 10036 of file regs.h.

#define SCS_CCR_REG   *((volatile int32u *)0xE000ED14u)

Definition at line 10006 of file regs.h.

#define SCS_CCR_RESET   (0x00000000u)

Definition at line 10008 of file regs.h.

#define SCS_CCR_STKALIGN   (0x00000200u)

Definition at line 10010 of file regs.h.

#define SCS_CCR_STKALIGN_BIT   (9)

Definition at line 10012 of file regs.h.

#define SCS_CCR_STKALIGN_BITS   (1)

Definition at line 10013 of file regs.h.

#define SCS_CCR_STKALIGN_MASK   (0x00000200u)

Definition at line 10011 of file regs.h.

#define SCS_CCR_UNALIGN_TRP   (0x00000008u)

Definition at line 10025 of file regs.h.

#define SCS_CCR_UNALIGN_TRP_BIT   (3)

Definition at line 10027 of file regs.h.

#define SCS_CCR_UNALIGN_TRP_BITS   (1)

Definition at line 10028 of file regs.h.

#define SCS_CCR_UNALIGN_TRP_MASK   (0x00000008u)

Definition at line 10026 of file regs.h.

#define SCS_CCR_USERSETMPEND   (0x00000002u)

Definition at line 10030 of file regs.h.

#define SCS_CCR_USERSETMPEND_BIT   (1)

Definition at line 10032 of file regs.h.

#define SCS_CCR_USERSETMPEND_BITS   (1)

Definition at line 10033 of file regs.h.

#define SCS_CCR_USERSETMPEND_MASK   (0x00000002u)

Definition at line 10031 of file regs.h.

#define SCS_CFSR   *((volatile int32u *)0xE000ED28u)

Definition at line 10190 of file regs.h.

#define SCS_CFSR_ADDR   (0xE000ED28u)

Definition at line 10192 of file regs.h.

#define SCS_CFSR_BFARVALID   (0x00008000u)

Definition at line 10225 of file regs.h.

#define SCS_CFSR_BFARVALID_BIT   (15)

Definition at line 10227 of file regs.h.

#define SCS_CFSR_BFARVALID_BITS   (1)

Definition at line 10228 of file regs.h.

#define SCS_CFSR_BFARVALID_MASK   (0x00008000u)

Definition at line 10226 of file regs.h.

#define SCS_CFSR_DACCVIOL   (0x00000002u)

Definition at line 10270 of file regs.h.

#define SCS_CFSR_DACCVIOL_BIT   (1)

Definition at line 10272 of file regs.h.

#define SCS_CFSR_DACCVIOL_BITS   (1)

Definition at line 10273 of file regs.h.

#define SCS_CFSR_DACCVIOL_MASK   (0x00000002u)

Definition at line 10271 of file regs.h.

#define SCS_CFSR_DIVBYZERO   (0x02000000u)

Definition at line 10195 of file regs.h.

#define SCS_CFSR_DIVBYZERO_BIT   (25)

Definition at line 10197 of file regs.h.

#define SCS_CFSR_DIVBYZERO_BITS   (1)

Definition at line 10198 of file regs.h.

#define SCS_CFSR_DIVBYZERO_MASK   (0x02000000u)

Definition at line 10196 of file regs.h.

#define SCS_CFSR_IACCVIOL   (0x00000001u)

Definition at line 10275 of file regs.h.

#define SCS_CFSR_IACCVIOL_BIT   (0)

Definition at line 10277 of file regs.h.

#define SCS_CFSR_IACCVIOL_BITS   (1)

Definition at line 10278 of file regs.h.

#define SCS_CFSR_IACCVIOL_MASK   (0x00000001u)

Definition at line 10276 of file regs.h.

#define SCS_CFSR_IBUSERR   (0x00000100u)

Definition at line 10250 of file regs.h.

#define SCS_CFSR_IBUSERR_BIT   (8)

Definition at line 10252 of file regs.h.

#define SCS_CFSR_IBUSERR_BITS   (1)

Definition at line 10253 of file regs.h.

#define SCS_CFSR_IBUSERR_MASK   (0x00000100u)

Definition at line 10251 of file regs.h.

#define SCS_CFSR_IMPRECISERR   (0x00000400u)

Definition at line 10240 of file regs.h.

#define SCS_CFSR_IMPRECISERR_BIT   (10)

Definition at line 10242 of file regs.h.

#define SCS_CFSR_IMPRECISERR_BITS   (1)

Definition at line 10243 of file regs.h.

#define SCS_CFSR_IMPRECISERR_MASK   (0x00000400u)

Definition at line 10241 of file regs.h.

#define SCS_CFSR_INVPC   (0x00040000u)

Definition at line 10210 of file regs.h.

#define SCS_CFSR_INVPC_BIT   (18)

Definition at line 10212 of file regs.h.

#define SCS_CFSR_INVPC_BITS   (1)

Definition at line 10213 of file regs.h.

#define SCS_CFSR_INVPC_MASK   (0x00040000u)

Definition at line 10211 of file regs.h.

#define SCS_CFSR_INVSTATE   (0x00020000u)

Definition at line 10215 of file regs.h.

#define SCS_CFSR_INVSTATE_BIT   (17)

Definition at line 10217 of file regs.h.

#define SCS_CFSR_INVSTATE_BITS   (1)

Definition at line 10218 of file regs.h.

#define SCS_CFSR_INVSTATE_MASK   (0x00020000u)

Definition at line 10216 of file regs.h.

#define SCS_CFSR_MMARVALID   (0x00000080u)

Definition at line 10255 of file regs.h.

#define SCS_CFSR_MMARVALID_BIT   (7)

Definition at line 10257 of file regs.h.

#define SCS_CFSR_MMARVALID_BITS   (1)

Definition at line 10258 of file regs.h.

#define SCS_CFSR_MMARVALID_MASK   (0x00000080u)

Definition at line 10256 of file regs.h.

#define SCS_CFSR_MSTKERR   (0x00000010u)

Definition at line 10260 of file regs.h.

#define SCS_CFSR_MSTKERR_BIT   (4)

Definition at line 10262 of file regs.h.

#define SCS_CFSR_MSTKERR_BITS   (1)

Definition at line 10263 of file regs.h.

#define SCS_CFSR_MSTKERR_MASK   (0x00000010u)

Definition at line 10261 of file regs.h.

#define SCS_CFSR_MUNSTKERR   (0x00000008u)

Definition at line 10265 of file regs.h.

#define SCS_CFSR_MUNSTKERR_BIT   (3)

Definition at line 10267 of file regs.h.

#define SCS_CFSR_MUNSTKERR_BITS   (1)

Definition at line 10268 of file regs.h.

#define SCS_CFSR_MUNSTKERR_MASK   (0x00000008u)

Definition at line 10266 of file regs.h.

#define SCS_CFSR_NOCP   (0x00080000u)

Definition at line 10205 of file regs.h.

#define SCS_CFSR_NOCP_BIT   (19)

Definition at line 10207 of file regs.h.

#define SCS_CFSR_NOCP_BITS   (1)

Definition at line 10208 of file regs.h.

#define SCS_CFSR_NOCP_MASK   (0x00080000u)

Definition at line 10206 of file regs.h.

#define SCS_CFSR_PRECISERR   (0x00000200u)

Definition at line 10245 of file regs.h.

#define SCS_CFSR_PRECISERR_BIT   (9)

Definition at line 10247 of file regs.h.

#define SCS_CFSR_PRECISERR_BITS   (1)

Definition at line 10248 of file regs.h.

#define SCS_CFSR_PRECISERR_MASK   (0x00000200u)

Definition at line 10246 of file regs.h.

#define SCS_CFSR_REG   *((volatile int32u *)0xE000ED28u)

Definition at line 10191 of file regs.h.

#define SCS_CFSR_RESET   (0x00000000u)

Definition at line 10193 of file regs.h.

#define SCS_CFSR_STKERR   (0x00001000u)

Definition at line 10230 of file regs.h.

#define SCS_CFSR_STKERR_BIT   (12)

Definition at line 10232 of file regs.h.

#define SCS_CFSR_STKERR_BITS   (1)

Definition at line 10233 of file regs.h.

#define SCS_CFSR_STKERR_MASK   (0x00001000u)

Definition at line 10231 of file regs.h.

#define SCS_CFSR_UNALIGNED   (0x01000000u)

Definition at line 10200 of file regs.h.

#define SCS_CFSR_UNALIGNED_BIT   (24)

Definition at line 10202 of file regs.h.

#define SCS_CFSR_UNALIGNED_BITS   (1)

Definition at line 10203 of file regs.h.

#define SCS_CFSR_UNALIGNED_MASK   (0x01000000u)

Definition at line 10201 of file regs.h.

#define SCS_CFSR_UNDEFINSTR   (0x00010000u)

Definition at line 10220 of file regs.h.

#define SCS_CFSR_UNDEFINSTR_BIT   (16)

Definition at line 10222 of file regs.h.

#define SCS_CFSR_UNDEFINSTR_BITS   (1)

Definition at line 10223 of file regs.h.

#define SCS_CFSR_UNDEFINSTR_MASK   (0x00010000u)

Definition at line 10221 of file regs.h.

#define SCS_CFSR_UNSTKERR   (0x00000800u)

Definition at line 10235 of file regs.h.

#define SCS_CFSR_UNSTKERR_BIT   (11)

Definition at line 10237 of file regs.h.

#define SCS_CFSR_UNSTKERR_BITS   (1)

Definition at line 10238 of file regs.h.

#define SCS_CFSR_UNSTKERR_MASK   (0x00000800u)

Definition at line 10236 of file regs.h.

#define SCS_CPUID   *((volatile int32u *)0xE000ED00u)

Definition at line 9845 of file regs.h.

#define SCS_CPUID_ADDR   (0xE000ED00u)

Definition at line 9847 of file regs.h.

#define SCS_CPUID_CONSTANT   (0x000F0000u)

Definition at line 9860 of file regs.h.

#define SCS_CPUID_CONSTANT_BIT   (16)

Definition at line 9862 of file regs.h.

#define SCS_CPUID_CONSTANT_BITS   (4)

Definition at line 9863 of file regs.h.

#define SCS_CPUID_CONSTANT_MASK   (0x000F0000u)

Definition at line 9861 of file regs.h.

#define SCS_CPUID_IMPLEMENTER   (0xFF000000u)

Definition at line 9850 of file regs.h.

#define SCS_CPUID_IMPLEMENTER_BIT   (24)

Definition at line 9852 of file regs.h.

#define SCS_CPUID_IMPLEMENTER_BITS   (8)

Definition at line 9853 of file regs.h.

#define SCS_CPUID_IMPLEMENTER_MASK   (0xFF000000u)

Definition at line 9851 of file regs.h.

#define SCS_CPUID_PARTNO   (0x0000FFF0u)

Definition at line 9865 of file regs.h.

#define SCS_CPUID_PARTNO_BIT   (4)

Definition at line 9867 of file regs.h.

#define SCS_CPUID_PARTNO_BITS   (12)

Definition at line 9868 of file regs.h.

#define SCS_CPUID_PARTNO_MASK   (0x0000FFF0u)

Definition at line 9866 of file regs.h.

#define SCS_CPUID_REG   *((volatile int32u *)0xE000ED00u)

Definition at line 9846 of file regs.h.

#define SCS_CPUID_RESET   (0x411FC231u)

Definition at line 9848 of file regs.h.

#define SCS_CPUID_REVISION   (0x0000000Fu)

Definition at line 9870 of file regs.h.

#define SCS_CPUID_REVISION_BIT   (0)

Definition at line 9872 of file regs.h.

#define SCS_CPUID_REVISION_BITS   (4)

Definition at line 9873 of file regs.h.

#define SCS_CPUID_REVISION_MASK   (0x0000000Fu)

Definition at line 9871 of file regs.h.

#define SCS_CPUID_VARIANT   (0x00F00000u)

Definition at line 9855 of file regs.h.

#define SCS_CPUID_VARIANT_BIT   (20)

Definition at line 9857 of file regs.h.

#define SCS_CPUID_VARIANT_BITS   (4)

Definition at line 9858 of file regs.h.

#define SCS_CPUID_VARIANT_MASK   (0x00F00000u)

Definition at line 9856 of file regs.h.

#define SCS_DFR0   *((volatile int32u *)0xE000ED48u)

Definition at line 10395 of file regs.h.

#define SCS_DFR0_ADDR   (0xE000ED48u)

Definition at line 10397 of file regs.h.

#define SCS_DFR0_FEATURE   (0xFFFFFFFFu)

Definition at line 10400 of file regs.h.

#define SCS_DFR0_FEATURE_BIT   (0)

Definition at line 10402 of file regs.h.

#define SCS_DFR0_FEATURE_BITS   (32)

Definition at line 10403 of file regs.h.

#define SCS_DFR0_FEATURE_MASK   (0xFFFFFFFFu)

Definition at line 10401 of file regs.h.

#define SCS_DFR0_REG   *((volatile int32u *)0xE000ED48u)

Definition at line 10396 of file regs.h.

#define SCS_DFR0_RESET   (0x00100000u)

Definition at line 10398 of file regs.h.

#define SCS_DFSR   *((volatile int32u *)0xE000ED30u)

Definition at line 10300 of file regs.h.

#define SCS_DFSR_ADDR   (0xE000ED30u)

Definition at line 10302 of file regs.h.

#define SCS_DFSR_BKPT   (0x00000002u)

Definition at line 10320 of file regs.h.

#define SCS_DFSR_BKPT_BIT   (1)

Definition at line 10322 of file regs.h.

#define SCS_DFSR_BKPT_BITS   (1)

Definition at line 10323 of file regs.h.

#define SCS_DFSR_BKPT_MASK   (0x00000002u)

Definition at line 10321 of file regs.h.

#define SCS_DFSR_DWTTRAP   (0x00000004u)

Definition at line 10315 of file regs.h.

#define SCS_DFSR_DWTTRAP_BIT   (2)

Definition at line 10317 of file regs.h.

#define SCS_DFSR_DWTTRAP_BITS   (1)

Definition at line 10318 of file regs.h.

#define SCS_DFSR_DWTTRAP_MASK   (0x00000004u)

Definition at line 10316 of file regs.h.

#define SCS_DFSR_EXTERNAL   (0x00000010u)

Definition at line 10305 of file regs.h.

#define SCS_DFSR_EXTERNAL_BIT   (4)

Definition at line 10307 of file regs.h.

#define SCS_DFSR_EXTERNAL_BITS   (1)

Definition at line 10308 of file regs.h.

#define SCS_DFSR_EXTERNAL_MASK   (0x00000010u)

Definition at line 10306 of file regs.h.

#define SCS_DFSR_HALTED   (0x00000001u)

Definition at line 10325 of file regs.h.

#define SCS_DFSR_HALTED_BIT   (0)

Definition at line 10327 of file regs.h.

#define SCS_DFSR_HALTED_BITS   (1)

Definition at line 10328 of file regs.h.

#define SCS_DFSR_HALTED_MASK   (0x00000001u)

Definition at line 10326 of file regs.h.

#define SCS_DFSR_REG   *((volatile int32u *)0xE000ED30u)

Definition at line 10301 of file regs.h.

#define SCS_DFSR_RESET   (0x00000000u)

Definition at line 10303 of file regs.h.

#define SCS_DFSR_VCATCH   (0x00000008u)

Definition at line 10310 of file regs.h.

#define SCS_DFSR_VCATCH_BIT   (3)

Definition at line 10312 of file regs.h.

#define SCS_DFSR_VCATCH_BITS   (1)

Definition at line 10313 of file regs.h.

#define SCS_DFSR_VCATCH_MASK   (0x00000008u)

Definition at line 10311 of file regs.h.

#define SCS_HFSR   *((volatile int32u *)0xE000ED2Cu)

Definition at line 10280 of file regs.h.

#define SCS_HFSR_ADDR   (0xE000ED2Cu)

Definition at line 10282 of file regs.h.

#define SCS_HFSR_DEBUGEVT   (0x80000000u)

Definition at line 10285 of file regs.h.

#define SCS_HFSR_DEBUGEVT_BIT   (31)

Definition at line 10287 of file regs.h.

#define SCS_HFSR_DEBUGEVT_BITS   (1)

Definition at line 10288 of file regs.h.

#define SCS_HFSR_DEBUGEVT_MASK   (0x80000000u)

Definition at line 10286 of file regs.h.

#define SCS_HFSR_FORCED   (0x40000000u)

Definition at line 10290 of file regs.h.

#define SCS_HFSR_FORCED_BIT   (30)

Definition at line 10292 of file regs.h.

#define SCS_HFSR_FORCED_BITS   (1)

Definition at line 10293 of file regs.h.

#define SCS_HFSR_FORCED_MASK   (0x40000000u)

Definition at line 10291 of file regs.h.

#define SCS_HFSR_REG   *((volatile int32u *)0xE000ED2Cu)

Definition at line 10281 of file regs.h.

#define SCS_HFSR_RESET   (0x00000000u)

Definition at line 10283 of file regs.h.

#define SCS_HFSR_VECTTBL   (0x00000002u)

Definition at line 10295 of file regs.h.

#define SCS_HFSR_VECTTBL_BIT   (1)

Definition at line 10297 of file regs.h.

#define SCS_HFSR_VECTTBL_BITS   (1)

Definition at line 10298 of file regs.h.

#define SCS_HFSR_VECTTBL_MASK   (0x00000002u)

Definition at line 10296 of file regs.h.

#define SCS_ICSR   *((volatile int32u *)0xE000ED04u)

Definition at line 9875 of file regs.h.

#define SCS_ICSR_ADDR   (0xE000ED04u)

Definition at line 9877 of file regs.h.

#define SCS_ICSR_ISRPENDING   (0x00400000u)

Definition at line 9910 of file regs.h.

#define SCS_ICSR_ISRPENDING_BIT   (22)

Definition at line 9912 of file regs.h.

#define SCS_ICSR_ISRPENDING_BITS   (1)

Definition at line 9913 of file regs.h.

#define SCS_ICSR_ISRPENDING_MASK   (0x00400000u)

Definition at line 9911 of file regs.h.

#define SCS_ICSR_ISRPREEMPT   (0x00800000u)

Definition at line 9905 of file regs.h.

#define SCS_ICSR_ISRPREEMPT_BIT   (23)

Definition at line 9907 of file regs.h.

#define SCS_ICSR_ISRPREEMPT_BITS   (1)

Definition at line 9908 of file regs.h.

#define SCS_ICSR_ISRPREEMPT_MASK   (0x00800000u)

Definition at line 9906 of file regs.h.

#define SCS_ICSR_NMIPENDSET   (0x80000000u)

Definition at line 9880 of file regs.h.

#define SCS_ICSR_NMIPENDSET_BIT   (31)

Definition at line 9882 of file regs.h.

#define SCS_ICSR_NMIPENDSET_BITS   (1)

Definition at line 9883 of file regs.h.

#define SCS_ICSR_NMIPENDSET_MASK   (0x80000000u)

Definition at line 9881 of file regs.h.

#define SCS_ICSR_PENDSTCLR   (0x02000000u)

Definition at line 9900 of file regs.h.

#define SCS_ICSR_PENDSTCLR_BIT   (25)

Definition at line 9902 of file regs.h.

#define SCS_ICSR_PENDSTCLR_BITS   (1)

Definition at line 9903 of file regs.h.

#define SCS_ICSR_PENDSTCLR_MASK   (0x02000000u)

Definition at line 9901 of file regs.h.

#define SCS_ICSR_PENDSTSET   (0x04000000u)

Definition at line 9895 of file regs.h.

#define SCS_ICSR_PENDSTSET_BIT   (26)

Definition at line 9897 of file regs.h.

#define SCS_ICSR_PENDSTSET_BITS   (1)

Definition at line 9898 of file regs.h.

#define SCS_ICSR_PENDSTSET_MASK   (0x04000000u)

Definition at line 9896 of file regs.h.

#define SCS_ICSR_PENDSVCLR   (0x08000000u)

Definition at line 9890 of file regs.h.

#define SCS_ICSR_PENDSVCLR_BIT   (27)

Definition at line 9892 of file regs.h.

#define SCS_ICSR_PENDSVCLR_BITS   (1)

Definition at line 9893 of file regs.h.

#define SCS_ICSR_PENDSVCLR_MASK   (0x08000000u)

Definition at line 9891 of file regs.h.

#define SCS_ICSR_PENDSVSET   (0x10000000u)

Definition at line 9885 of file regs.h.

#define SCS_ICSR_PENDSVSET_BIT   (28)

Definition at line 9887 of file regs.h.

#define SCS_ICSR_PENDSVSET_BITS   (1)

Definition at line 9888 of file regs.h.

#define SCS_ICSR_PENDSVSET_MASK   (0x10000000u)

Definition at line 9886 of file regs.h.

#define SCS_ICSR_REG   *((volatile int32u *)0xE000ED04u)

Definition at line 9876 of file regs.h.

#define SCS_ICSR_RESET   (0x00000000u)

Definition at line 9878 of file regs.h.

#define SCS_ICSR_RETTOBASE   (0x00000800u)

Definition at line 9920 of file regs.h.

#define SCS_ICSR_RETTOBASE_BIT   (11)

Definition at line 9922 of file regs.h.

#define SCS_ICSR_RETTOBASE_BITS   (1)

Definition at line 9923 of file regs.h.

#define SCS_ICSR_RETTOBASE_MASK   (0x00000800u)

Definition at line 9921 of file regs.h.

#define SCS_ICSR_VECACTIVE   (0x000001FFu)

Definition at line 9925 of file regs.h.

#define SCS_ICSR_VECACTIVE_BIT   (0)

Definition at line 9927 of file regs.h.

#define SCS_ICSR_VECACTIVE_BITS   (9)

Definition at line 9928 of file regs.h.

#define SCS_ICSR_VECACTIVE_MASK   (0x000001FFu)

Definition at line 9926 of file regs.h.

#define SCS_ICSR_VECTPENDING   (0x001FF000u)

Definition at line 9915 of file regs.h.

#define SCS_ICSR_VECTPENDING_BIT   (12)

Definition at line 9917 of file regs.h.

#define SCS_ICSR_VECTPENDING_BITS   (9)

Definition at line 9918 of file regs.h.

#define SCS_ICSR_VECTPENDING_MASK   (0x001FF000u)

Definition at line 9916 of file regs.h.

#define SCS_ISAFR0   *((volatile int32u *)0xE000ED60u)

Definition at line 10455 of file regs.h.

#define SCS_ISAFR0_ADDR   (0xE000ED60u)

Definition at line 10457 of file regs.h.

#define SCS_ISAFR0_FEATURE   (0xFFFFFFFFu)

Definition at line 10460 of file regs.h.

#define SCS_ISAFR0_FEATURE_BIT   (0)

Definition at line 10462 of file regs.h.

#define SCS_ISAFR0_FEATURE_BITS   (32)

Definition at line 10463 of file regs.h.

#define SCS_ISAFR0_FEATURE_MASK   (0xFFFFFFFFu)

Definition at line 10461 of file regs.h.

#define SCS_ISAFR0_REG   *((volatile int32u *)0xE000ED60u)

Definition at line 10456 of file regs.h.

#define SCS_ISAFR0_RESET   (0x01141110u)

Definition at line 10458 of file regs.h.

#define SCS_ISAFR1   *((volatile int32u *)0xE000ED64u)

Definition at line 10465 of file regs.h.

#define SCS_ISAFR1_ADDR   (0xE000ED64u)

Definition at line 10467 of file regs.h.

#define SCS_ISAFR1_FEATURE   (0xFFFFFFFFu)

Definition at line 10470 of file regs.h.

#define SCS_ISAFR1_FEATURE_BIT   (0)

Definition at line 10472 of file regs.h.

#define SCS_ISAFR1_FEATURE_BITS   (32)

Definition at line 10473 of file regs.h.

#define SCS_ISAFR1_FEATURE_MASK   (0xFFFFFFFFu)

Definition at line 10471 of file regs.h.

#define SCS_ISAFR1_REG   *((volatile int32u *)0xE000ED64u)

Definition at line 10466 of file regs.h.

#define SCS_ISAFR1_RESET   (0x02111000u)

Definition at line 10468 of file regs.h.

#define SCS_ISAFR2   *((volatile int32u *)0xE000ED68u)

Definition at line 10475 of file regs.h.

#define SCS_ISAFR2_ADDR   (0xE000ED68u)

Definition at line 10477 of file regs.h.

#define SCS_ISAFR2_FEATURE   (0xFFFFFFFFu)

Definition at line 10480 of file regs.h.

#define SCS_ISAFR2_FEATURE_BIT   (0)

Definition at line 10482 of file regs.h.

#define SCS_ISAFR2_FEATURE_BITS   (32)

Definition at line 10483 of file regs.h.

#define SCS_ISAFR2_FEATURE_MASK   (0xFFFFFFFFu)

Definition at line 10481 of file regs.h.

#define SCS_ISAFR2_REG   *((volatile int32u *)0xE000ED68u)

Definition at line 10476 of file regs.h.

#define SCS_ISAFR2_RESET   (0x21112231u)

Definition at line 10478 of file regs.h.

#define SCS_ISAFR3   *((volatile int32u *)0xE000ED6Cu)

Definition at line 10485 of file regs.h.

#define SCS_ISAFR3_ADDR   (0xE000ED6Cu)

Definition at line 10487 of file regs.h.

#define SCS_ISAFR3_FEATURE   (0xFFFFFFFFu)

Definition at line 10490 of file regs.h.

#define SCS_ISAFR3_FEATURE_BIT   (0)

Definition at line 10492 of file regs.h.

#define SCS_ISAFR3_FEATURE_BITS   (32)

Definition at line 10493 of file regs.h.

#define SCS_ISAFR3_FEATURE_MASK   (0xFFFFFFFFu)

Definition at line 10491 of file regs.h.

#define SCS_ISAFR3_REG   *((volatile int32u *)0xE000ED6Cu)

Definition at line 10486 of file regs.h.

#define SCS_ISAFR3_RESET   (0x11111110u)

Definition at line 10488 of file regs.h.

#define SCS_ISAFR4   *((volatile int32u *)0xE000ED70u)

Definition at line 10495 of file regs.h.

#define SCS_ISAFR4_ADDR   (0xE000ED70u)

Definition at line 10497 of file regs.h.

#define SCS_ISAFR4_FEATURE   (0xFFFFFFFFu)

Definition at line 10500 of file regs.h.

#define SCS_ISAFR4_FEATURE_BIT   (0)

Definition at line 10502 of file regs.h.

#define SCS_ISAFR4_FEATURE_BITS   (32)

Definition at line 10503 of file regs.h.

#define SCS_ISAFR4_FEATURE_MASK   (0xFFFFFFFFu)

Definition at line 10501 of file regs.h.

#define SCS_ISAFR4_REG   *((volatile int32u *)0xE000ED70u)

Definition at line 10496 of file regs.h.

#define SCS_ISAFR4_RESET   (0x01310102u)

Definition at line 10498 of file regs.h.

#define SCS_MMAR   *((volatile int32u *)0xE000ED34u)

Definition at line 10330 of file regs.h.

#define SCS_MMAR_ADDR   (0xE000ED34u)

Definition at line 10332 of file regs.h.

#define SCS_MMAR_ADDRESS   (0xFFFFFFFFu)

Definition at line 10335 of file regs.h.

#define SCS_MMAR_ADDRESS_BIT   (0)

Definition at line 10337 of file regs.h.

#define SCS_MMAR_ADDRESS_BITS   (32)

Definition at line 10338 of file regs.h.

#define SCS_MMAR_ADDRESS_MASK   (0xFFFFFFFFu)

Definition at line 10336 of file regs.h.

#define SCS_MMAR_REG   *((volatile int32u *)0xE000ED34u)

Definition at line 10331 of file regs.h.

#define SCS_MMAR_RESET   (0x00000000u)

Definition at line 10333 of file regs.h.

#define SCS_MMFR0   *((volatile int32u *)0xE000ED50u)

Definition at line 10415 of file regs.h.

#define SCS_MMFR0_ADDR   (0xE000ED50u)

Definition at line 10417 of file regs.h.

#define SCS_MMFR0_FEATURE   (0xFFFFFFFFu)

Definition at line 10420 of file regs.h.

#define SCS_MMFR0_FEATURE_BIT   (0)

Definition at line 10422 of file regs.h.

#define SCS_MMFR0_FEATURE_BITS   (32)

Definition at line 10423 of file regs.h.

#define SCS_MMFR0_FEATURE_MASK   (0xFFFFFFFFu)

Definition at line 10421 of file regs.h.

#define SCS_MMFR0_REG   *((volatile int32u *)0xE000ED50u)

Definition at line 10416 of file regs.h.

#define SCS_MMFR0_RESET   (0x00000030u)

Definition at line 10418 of file regs.h.

#define SCS_MMFR1   *((volatile int32u *)0xE000ED54u)

Definition at line 10425 of file regs.h.

#define SCS_MMFR1_ADDR   (0xE000ED54u)

Definition at line 10427 of file regs.h.

#define SCS_MMFR1_FEATURE   (0xFFFFFFFFu)

Definition at line 10430 of file regs.h.

#define SCS_MMFR1_FEATURE_BIT   (0)

Definition at line 10432 of file regs.h.

#define SCS_MMFR1_FEATURE_BITS   (32)

Definition at line 10433 of file regs.h.

#define SCS_MMFR1_FEATURE_MASK   (0xFFFFFFFFu)

Definition at line 10431 of file regs.h.

#define SCS_MMFR1_REG   *((volatile int32u *)0xE000ED54u)

Definition at line 10426 of file regs.h.

#define SCS_MMFR1_RESET   (0x00000000u)

Definition at line 10428 of file regs.h.

#define SCS_MMFR2   *((volatile int32u *)0xE000ED58u)

Definition at line 10435 of file regs.h.

#define SCS_MMFR2_ADDR   (0xE000ED58u)

Definition at line 10437 of file regs.h.

#define SCS_MMFR2_FEATURE   (0xFFFFFFFFu)

Definition at line 10440 of file regs.h.

#define SCS_MMFR2_FEATURE_BIT   (0)

Definition at line 10442 of file regs.h.

#define SCS_MMFR2_FEATURE_BITS   (32)

Definition at line 10443 of file regs.h.

#define SCS_MMFR2_FEATURE_MASK   (0xFFFFFFFFu)

Definition at line 10441 of file regs.h.

#define SCS_MMFR2_REG   *((volatile int32u *)0xE000ED58u)

Definition at line 10436 of file regs.h.

#define SCS_MMFR2_RESET   (0x00000000u)

Definition at line 10438 of file regs.h.

#define SCS_MMFR3   *((volatile int32u *)0xE000ED5Cu)

Definition at line 10445 of file regs.h.

#define SCS_MMFR3_ADDR   (0xE000ED5Cu)

Definition at line 10447 of file regs.h.

#define SCS_MMFR3_FEATURE   (0xFFFFFFFFu)

Definition at line 10450 of file regs.h.

#define SCS_MMFR3_FEATURE_BIT   (0)

Definition at line 10452 of file regs.h.

#define SCS_MMFR3_FEATURE_BITS   (32)

Definition at line 10453 of file regs.h.

#define SCS_MMFR3_FEATURE_MASK   (0xFFFFFFFFu)

Definition at line 10451 of file regs.h.

#define SCS_MMFR3_REG   *((volatile int32u *)0xE000ED5Cu)

Definition at line 10446 of file regs.h.

#define SCS_MMFR3_RESET   (0x00000000u)

Definition at line 10448 of file regs.h.

#define SCS_PFR0   *((volatile int32u *)0xE000ED40u)

Definition at line 10375 of file regs.h.

#define SCS_PFR0_ADDR   (0xE000ED40u)

Definition at line 10377 of file regs.h.

#define SCS_PFR0_FEATURE   (0xFFFFFFFFu)

Definition at line 10380 of file regs.h.

#define SCS_PFR0_FEATURE_BIT   (0)

Definition at line 10382 of file regs.h.

#define SCS_PFR0_FEATURE_BITS   (32)

Definition at line 10383 of file regs.h.

#define SCS_PFR0_FEATURE_MASK   (0xFFFFFFFFu)

Definition at line 10381 of file regs.h.

#define SCS_PFR0_REG   *((volatile int32u *)0xE000ED40u)

Definition at line 10376 of file regs.h.

#define SCS_PFR0_RESET   (0x00000030u)

Definition at line 10378 of file regs.h.

#define SCS_PFR1   *((volatile int32u *)0xE000ED44u)

Definition at line 10385 of file regs.h.

#define SCS_PFR1_ADDR   (0xE000ED44u)

Definition at line 10387 of file regs.h.

#define SCS_PFR1_FEATURE   (0xFFFFFFFFu)

Definition at line 10390 of file regs.h.

#define SCS_PFR1_FEATURE_BIT   (0)

Definition at line 10392 of file regs.h.

#define SCS_PFR1_FEATURE_BITS   (32)

Definition at line 10393 of file regs.h.

#define SCS_PFR1_FEATURE_MASK   (0xFFFFFFFFu)

Definition at line 10391 of file regs.h.

#define SCS_PFR1_REG   *((volatile int32u *)0xE000ED44u)

Definition at line 10386 of file regs.h.

#define SCS_PFR1_RESET   (0x00000200u)

Definition at line 10388 of file regs.h.

#define SCS_SCR   *((volatile int32u *)0xE000ED10u)

Definition at line 9985 of file regs.h.

#define SCS_SCR_ADDR   (0xE000ED10u)

Definition at line 9987 of file regs.h.

#define SCS_SCR_REG   *((volatile int32u *)0xE000ED10u)

Definition at line 9986 of file regs.h.

#define SCS_SCR_RESET   (0x00000000u)

Definition at line 9988 of file regs.h.

#define SCS_SCR_SEVONPEND   (0x00000010u)

Definition at line 9990 of file regs.h.

#define SCS_SCR_SEVONPEND_BIT   (4)

Definition at line 9992 of file regs.h.

#define SCS_SCR_SEVONPEND_BITS   (1)

Definition at line 9993 of file regs.h.

#define SCS_SCR_SEVONPEND_MASK   (0x00000010u)

Definition at line 9991 of file regs.h.

#define SCS_SCR_SLEEPDEEP   (0x00000004u)

Definition at line 9995 of file regs.h.

#define SCS_SCR_SLEEPDEEP_BIT   (2)

Definition at line 9997 of file regs.h.

#define SCS_SCR_SLEEPDEEP_BITS   (1)

Definition at line 9998 of file regs.h.

#define SCS_SCR_SLEEPDEEP_MASK   (0x00000004u)

Definition at line 9996 of file regs.h.

#define SCS_SCR_SLEEPONEXIT   (0x00000002u)

Definition at line 10000 of file regs.h.

#define SCS_SCR_SLEEPONEXIT_BIT   (1)

Definition at line 10002 of file regs.h.

#define SCS_SCR_SLEEPONEXIT_BITS   (1)

Definition at line 10003 of file regs.h.

#define SCS_SCR_SLEEPONEXIT_MASK   (0x00000002u)

Definition at line 10001 of file regs.h.

#define SCS_SHCSR   *((volatile int32u *)0xE000ED24u)

Definition at line 10115 of file regs.h.

#define SCS_SHCSR_ADDR   (0xE000ED24u)

Definition at line 10117 of file regs.h.

#define SCS_SHCSR_BUSFAULTACT   (0x00000002u)

Definition at line 10180 of file regs.h.

#define SCS_SHCSR_BUSFAULTACT_BIT   (1)

Definition at line 10182 of file regs.h.

#define SCS_SHCSR_BUSFAULTACT_BITS   (1)

Definition at line 10183 of file regs.h.

#define SCS_SHCSR_BUSFAULTACT_MASK   (0x00000002u)

Definition at line 10181 of file regs.h.

#define SCS_SHCSR_BUSFAULTENA   (0x00020000u)

Definition at line 10125 of file regs.h.

#define SCS_SHCSR_BUSFAULTENA_BIT   (17)

Definition at line 10127 of file regs.h.

#define SCS_SHCSR_BUSFAULTENA_BITS   (1)

Definition at line 10128 of file regs.h.

#define SCS_SHCSR_BUSFAULTENA_MASK   (0x00020000u)

Definition at line 10126 of file regs.h.

#define SCS_SHCSR_BUSFAULTPENDED   (0x00004000u)

Definition at line 10140 of file regs.h.

#define SCS_SHCSR_BUSFAULTPENDED_BIT   (14)

Definition at line 10142 of file regs.h.

#define SCS_SHCSR_BUSFAULTPENDED_BITS   (1)

Definition at line 10143 of file regs.h.

#define SCS_SHCSR_BUSFAULTPENDED_MASK   (0x00004000u)

Definition at line 10141 of file regs.h.

#define SCS_SHCSR_MEMFAULTACT   (0x00000001u)

Definition at line 10185 of file regs.h.

#define SCS_SHCSR_MEMFAULTACT_BIT   (0)

Definition at line 10187 of file regs.h.

#define SCS_SHCSR_MEMFAULTACT_BITS   (1)

Definition at line 10188 of file regs.h.

#define SCS_SHCSR_MEMFAULTACT_MASK   (0x00000001u)

Definition at line 10186 of file regs.h.

#define SCS_SHCSR_MEMFAULTENA   (0x00010000u)

Definition at line 10130 of file regs.h.

#define SCS_SHCSR_MEMFAULTENA_BIT   (16)

Definition at line 10132 of file regs.h.

#define SCS_SHCSR_MEMFAULTENA_BITS   (1)

Definition at line 10133 of file regs.h.

#define SCS_SHCSR_MEMFAULTENA_MASK   (0x00010000u)

Definition at line 10131 of file regs.h.

#define SCS_SHCSR_MEMFAULTPENDED   (0x00002000u)

Definition at line 10145 of file regs.h.

#define SCS_SHCSR_MEMFAULTPENDED_BIT   (13)

Definition at line 10147 of file regs.h.

#define SCS_SHCSR_MEMFAULTPENDED_BITS   (1)

Definition at line 10148 of file regs.h.

#define SCS_SHCSR_MEMFAULTPENDED_MASK   (0x00002000u)

Definition at line 10146 of file regs.h.

#define SCS_SHCSR_MONITORACT   (0x00000100u)

Definition at line 10165 of file regs.h.

#define SCS_SHCSR_MONITORACT_BIT   (8)

Definition at line 10167 of file regs.h.

#define SCS_SHCSR_MONITORACT_BITS   (1)

Definition at line 10168 of file regs.h.

#define SCS_SHCSR_MONITORACT_MASK   (0x00000100u)

Definition at line 10166 of file regs.h.

#define SCS_SHCSR_PENDSVACT   (0x00000400u)

Definition at line 10160 of file regs.h.

#define SCS_SHCSR_PENDSVACT_BIT   (10)

Definition at line 10162 of file regs.h.

#define SCS_SHCSR_PENDSVACT_BITS   (1)

Definition at line 10163 of file regs.h.

#define SCS_SHCSR_PENDSVACT_MASK   (0x00000400u)

Definition at line 10161 of file regs.h.

#define SCS_SHCSR_REG   *((volatile int32u *)0xE000ED24u)

Definition at line 10116 of file regs.h.

#define SCS_SHCSR_RESET   (0x00000000u)

Definition at line 10118 of file regs.h.

#define SCS_SHCSR_SVCALLACT   (0x00000080u)

Definition at line 10170 of file regs.h.

#define SCS_SHCSR_SVCALLACT_BIT   (7)

Definition at line 10172 of file regs.h.

#define SCS_SHCSR_SVCALLACT_BITS   (1)

Definition at line 10173 of file regs.h.

#define SCS_SHCSR_SVCALLACT_MASK   (0x00000080u)

Definition at line 10171 of file regs.h.

#define SCS_SHCSR_SVCALLPENDED   (0x00008000u)

Definition at line 10135 of file regs.h.

#define SCS_SHCSR_SVCALLPENDED_BIT   (15)

Definition at line 10137 of file regs.h.

#define SCS_SHCSR_SVCALLPENDED_BITS   (1)

Definition at line 10138 of file regs.h.

#define SCS_SHCSR_SVCALLPENDED_MASK   (0x00008000u)

Definition at line 10136 of file regs.h.

#define SCS_SHCSR_SYSTICKACT   (0x00000800u)

Definition at line 10155 of file regs.h.

#define SCS_SHCSR_SYSTICKACT_BIT   (11)

Definition at line 10157 of file regs.h.

#define SCS_SHCSR_SYSTICKACT_BITS   (1)

Definition at line 10158 of file regs.h.

#define SCS_SHCSR_SYSTICKACT_MASK   (0x00000800u)

Definition at line 10156 of file regs.h.

#define SCS_SHCSR_USGFAULTACT   (0x00000008u)

Definition at line 10175 of file regs.h.

#define SCS_SHCSR_USGFAULTACT_BIT   (3)

Definition at line 10177 of file regs.h.

#define SCS_SHCSR_USGFAULTACT_BITS   (1)

Definition at line 10178 of file regs.h.

#define SCS_SHCSR_USGFAULTACT_MASK   (0x00000008u)

Definition at line 10176 of file regs.h.

#define SCS_SHCSR_USGFAULTENA   (0x00040000u)

Definition at line 10120 of file regs.h.

#define SCS_SHCSR_USGFAULTENA_BIT   (18)

Definition at line 10122 of file regs.h.

#define SCS_SHCSR_USGFAULTENA_BITS   (1)

Definition at line 10123 of file regs.h.

#define SCS_SHCSR_USGFAULTENA_MASK   (0x00040000u)

Definition at line 10121 of file regs.h.

#define SCS_SHCSR_USGFAULTPENDED   (0x00001000u)

Definition at line 10150 of file regs.h.

#define SCS_SHCSR_USGFAULTPENDED_BIT   (12)

Definition at line 10152 of file regs.h.

#define SCS_SHCSR_USGFAULTPENDED_BITS   (1)

Definition at line 10153 of file regs.h.

#define SCS_SHCSR_USGFAULTPENDED_MASK   (0x00001000u)

Definition at line 10151 of file regs.h.

#define SCS_SHPR_11to8   *((volatile int32u *)0xE000ED1Cu)

Definition at line 10065 of file regs.h.

#define SCS_SHPR_11to8_ADDR   (0xE000ED1Cu)

Definition at line 10067 of file regs.h.

#define SCS_SHPR_11to8_PRI_10   (0x00FF0000u)

Definition at line 10075 of file regs.h.

#define SCS_SHPR_11to8_PRI_10_BIT   (16)

Definition at line 10077 of file regs.h.

#define SCS_SHPR_11to8_PRI_10_BITS   (8)

Definition at line 10078 of file regs.h.

#define SCS_SHPR_11to8_PRI_10_MASK   (0x00FF0000u)

Definition at line 10076 of file regs.h.

#define SCS_SHPR_11to8_PRI_11   (0xFF000000u)

Definition at line 10070 of file regs.h.

#define SCS_SHPR_11to8_PRI_11_BIT   (24)

Definition at line 10072 of file regs.h.

#define SCS_SHPR_11to8_PRI_11_BITS   (8)

Definition at line 10073 of file regs.h.

#define SCS_SHPR_11to8_PRI_11_MASK   (0xFF000000u)

Definition at line 10071 of file regs.h.

#define SCS_SHPR_11to8_PRI_8   (0x000000FFu)

Definition at line 10085 of file regs.h.

#define SCS_SHPR_11to8_PRI_8_BIT   (0)

Definition at line 10087 of file regs.h.

#define SCS_SHPR_11to8_PRI_8_BITS   (8)

Definition at line 10088 of file regs.h.

#define SCS_SHPR_11to8_PRI_8_MASK   (0x000000FFu)

Definition at line 10086 of file regs.h.

#define SCS_SHPR_11to8_PRI_9   (0x0000FF00u)

Definition at line 10080 of file regs.h.

#define SCS_SHPR_11to8_PRI_9_BIT   (8)

Definition at line 10082 of file regs.h.

#define SCS_SHPR_11to8_PRI_9_BITS   (8)

Definition at line 10083 of file regs.h.

#define SCS_SHPR_11to8_PRI_9_MASK   (0x0000FF00u)

Definition at line 10081 of file regs.h.

#define SCS_SHPR_11to8_REG   *((volatile int32u *)0xE000ED1Cu)

Definition at line 10066 of file regs.h.

#define SCS_SHPR_11to8_RESET   (0x00000000u)

Definition at line 10068 of file regs.h.

#define SCS_SHPR_15to12   *((volatile int32u *)0xE000ED20u)

Definition at line 10090 of file regs.h.

#define SCS_SHPR_15to12_ADDR   (0xE000ED20u)

Definition at line 10092 of file regs.h.

#define SCS_SHPR_15to12_PRI_12   (0x000000FFu)

Definition at line 10110 of file regs.h.

#define SCS_SHPR_15to12_PRI_12_BIT   (0)

Definition at line 10112 of file regs.h.

#define SCS_SHPR_15to12_PRI_12_BITS   (8)

Definition at line 10113 of file regs.h.

#define SCS_SHPR_15to12_PRI_12_MASK   (0x000000FFu)

Definition at line 10111 of file regs.h.

#define SCS_SHPR_15to12_PRI_13   (0x0000FF00u)

Definition at line 10105 of file regs.h.

#define SCS_SHPR_15to12_PRI_13_BIT   (8)

Definition at line 10107 of file regs.h.

#define SCS_SHPR_15to12_PRI_13_BITS   (8)

Definition at line 10108 of file regs.h.

#define SCS_SHPR_15to12_PRI_13_MASK   (0x0000FF00u)

Definition at line 10106 of file regs.h.

#define SCS_SHPR_15to12_PRI_14   (0x00FF0000u)

Definition at line 10100 of file regs.h.

#define SCS_SHPR_15to12_PRI_14_BIT   (16)

Definition at line 10102 of file regs.h.

#define SCS_SHPR_15to12_PRI_14_BITS   (8)

Definition at line 10103 of file regs.h.

#define SCS_SHPR_15to12_PRI_14_MASK   (0x00FF0000u)

Definition at line 10101 of file regs.h.

#define SCS_SHPR_15to12_PRI_15   (0xFF000000u)

Definition at line 10095 of file regs.h.

#define SCS_SHPR_15to12_PRI_15_BIT   (24)

Definition at line 10097 of file regs.h.

#define SCS_SHPR_15to12_PRI_15_BITS   (8)

Definition at line 10098 of file regs.h.

#define SCS_SHPR_15to12_PRI_15_MASK   (0xFF000000u)

Definition at line 10096 of file regs.h.

#define SCS_SHPR_15to12_REG   *((volatile int32u *)0xE000ED20u)

Definition at line 10091 of file regs.h.

#define SCS_SHPR_15to12_RESET   (0x00000000u)

Definition at line 10093 of file regs.h.

#define SCS_SHPR_7to4   *((volatile int32u *)0xE000ED18u)

Definition at line 10040 of file regs.h.

#define SCS_SHPR_7to4_ADDR   (0xE000ED18u)

Definition at line 10042 of file regs.h.

#define SCS_SHPR_7to4_PRI_4   (0x000000FFu)

Definition at line 10060 of file regs.h.

#define SCS_SHPR_7to4_PRI_4_BIT   (0)

Definition at line 10062 of file regs.h.

#define SCS_SHPR_7to4_PRI_4_BITS   (8)

Definition at line 10063 of file regs.h.

#define SCS_SHPR_7to4_PRI_4_MASK   (0x000000FFu)

Definition at line 10061 of file regs.h.

#define SCS_SHPR_7to4_PRI_5   (0x0000FF00u)

Definition at line 10055 of file regs.h.

#define SCS_SHPR_7to4_PRI_5_BIT   (8)

Definition at line 10057 of file regs.h.

#define SCS_SHPR_7to4_PRI_5_BITS   (8)

Definition at line 10058 of file regs.h.

#define SCS_SHPR_7to4_PRI_5_MASK   (0x0000FF00u)

Definition at line 10056 of file regs.h.

#define SCS_SHPR_7to4_PRI_6   (0x00FF0000u)

Definition at line 10050 of file regs.h.

#define SCS_SHPR_7to4_PRI_6_BIT   (16)

Definition at line 10052 of file regs.h.

#define SCS_SHPR_7to4_PRI_6_BITS   (8)

Definition at line 10053 of file regs.h.

#define SCS_SHPR_7to4_PRI_6_MASK   (0x00FF0000u)

Definition at line 10051 of file regs.h.

#define SCS_SHPR_7to4_PRI_7   (0xFF000000u)

Definition at line 10045 of file regs.h.

#define SCS_SHPR_7to4_PRI_7_BIT   (24)

Definition at line 10047 of file regs.h.

#define SCS_SHPR_7to4_PRI_7_BITS   (8)

Definition at line 10048 of file regs.h.

#define SCS_SHPR_7to4_PRI_7_MASK   (0xFF000000u)

Definition at line 10046 of file regs.h.

#define SCS_SHPR_7to4_REG   *((volatile int32u *)0xE000ED18u)

Definition at line 10041 of file regs.h.

#define SCS_SHPR_7to4_RESET   (0x00000000u)

Definition at line 10043 of file regs.h.

#define SCS_VTOR   *((volatile int32u *)0xE000ED08u)

Definition at line 9930 of file regs.h.

#define SCS_VTOR_ADDR   (0xE000ED08u)

Definition at line 9932 of file regs.h.

#define SCS_VTOR_REG   *((volatile int32u *)0xE000ED08u)

Definition at line 9931 of file regs.h.

#define SCS_VTOR_RESET   (0x00000000u)

Definition at line 9933 of file regs.h.

#define SCS_VTOR_TBLBASE   (0x20000000u)

Definition at line 9935 of file regs.h.

#define SCS_VTOR_TBLBASE_BIT   (29)

Definition at line 9937 of file regs.h.

#define SCS_VTOR_TBLBASE_BITS   (1)

Definition at line 9938 of file regs.h.

#define SCS_VTOR_TBLBASE_MASK   (0x20000000u)

Definition at line 9936 of file regs.h.

#define SCS_VTOR_TBLOFF   (0x1FFFFF00u)

Definition at line 9940 of file regs.h.

#define SCS_VTOR_TBLOFF_BIT   (8)

Definition at line 9942 of file regs.h.

#define SCS_VTOR_TBLOFF_BITS   (21)

Definition at line 9943 of file regs.h.

#define SCS_VTOR_TBLOFF_MASK   (0x1FFFFF00u)

Definition at line 9941 of file regs.h.

#define SEC_INT_MASK   *((volatile int32u *)0x4000A050u)

Definition at line 3715 of file regs.h.

#define SEC_INT_MASK_ADDR   (0x4000A050u)

Definition at line 3717 of file regs.h.

#define SEC_INT_MASK_CT_WORD_VALID_MSK   (0x00000004u)

Definition at line 3720 of file regs.h.

#define SEC_INT_MASK_CT_WORD_VALID_MSK_BIT   (2)

Definition at line 3722 of file regs.h.

#define SEC_INT_MASK_CT_WORD_VALID_MSK_BITS   (1)

Definition at line 3723 of file regs.h.

#define SEC_INT_MASK_CT_WORD_VALID_MSK_MASK   (0x00000004u)

Definition at line 3721 of file regs.h.

#define SEC_INT_MASK_ENC_COMPLETE_MSK   (0x00000001u)

Definition at line 3730 of file regs.h.

#define SEC_INT_MASK_ENC_COMPLETE_MSK_BIT   (0)

Definition at line 3732 of file regs.h.

#define SEC_INT_MASK_ENC_COMPLETE_MSK_BITS   (1)

Definition at line 3733 of file regs.h.

#define SEC_INT_MASK_ENC_COMPLETE_MSK_MASK   (0x00000001u)

Definition at line 3731 of file regs.h.

#define SEC_INT_MASK_PT_WORD_REQ_MSK   (0x00000002u)

Definition at line 3725 of file regs.h.

#define SEC_INT_MASK_PT_WORD_REQ_MSK_BIT   (1)

Definition at line 3727 of file regs.h.

#define SEC_INT_MASK_PT_WORD_REQ_MSK_BITS   (1)

Definition at line 3728 of file regs.h.

#define SEC_INT_MASK_PT_WORD_REQ_MSK_MASK   (0x00000002u)

Definition at line 3726 of file regs.h.

#define SEC_INT_MASK_REG   *((volatile int32u *)0x4000A050u)

Definition at line 3716 of file regs.h.

#define SEC_INT_MASK_RESET   (0x00000000u)

Definition at line 3718 of file regs.h.

#define SEC_INT_SRC   *((volatile int32u *)0x4000A010u)

Definition at line 3415 of file regs.h.

#define SEC_INT_SRC_ADDR   (0x4000A010u)

Definition at line 3417 of file regs.h.

#define SEC_INT_SRC_CT_WORD_VALID_SRC   (0x00000004u)

Definition at line 3420 of file regs.h.

#define SEC_INT_SRC_CT_WORD_VALID_SRC_BIT   (2)

Definition at line 3422 of file regs.h.

#define SEC_INT_SRC_CT_WORD_VALID_SRC_BITS   (1)

Definition at line 3423 of file regs.h.

#define SEC_INT_SRC_CT_WORD_VALID_SRC_MASK   (0x00000004u)

Definition at line 3421 of file regs.h.

#define SEC_INT_SRC_ENC_COMPLETE_SRC   (0x00000001u)

Definition at line 3430 of file regs.h.

#define SEC_INT_SRC_ENC_COMPLETE_SRC_BIT   (0)

Definition at line 3432 of file regs.h.

#define SEC_INT_SRC_ENC_COMPLETE_SRC_BITS   (1)

Definition at line 3433 of file regs.h.

#define SEC_INT_SRC_ENC_COMPLETE_SRC_MASK   (0x00000001u)

Definition at line 3431 of file regs.h.

#define SEC_INT_SRC_PT_WORD_REQ_SRC   (0x00000002u)

Definition at line 3425 of file regs.h.

#define SEC_INT_SRC_PT_WORD_REQ_SRC_BIT   (1)

Definition at line 3427 of file regs.h.

#define SEC_INT_SRC_PT_WORD_REQ_SRC_BITS   (1)

Definition at line 3428 of file regs.h.

#define SEC_INT_SRC_PT_WORD_REQ_SRC_MASK   (0x00000002u)

Definition at line 3426 of file regs.h.

#define SEC_INT_SRC_REG   *((volatile int32u *)0x4000A010u)

Definition at line 3416 of file regs.h.

#define SEC_INT_SRC_RESET   (0x00000000u)

Definition at line 3418 of file regs.h.

#define SECURITY_CONFIG   *((volatile int32u *)0x40003000u)

Definition at line 2280 of file regs.h.

#define SECURITY_CONFIG_ADDR   (0x40003000u)

Definition at line 2282 of file regs.h.

#define SECURITY_CONFIG_CBC_XOR_PT   (0x00000010u)

Definition at line 2300 of file regs.h.

#define SECURITY_CONFIG_CBC_XOR_PT_BIT   (4)

Definition at line 2302 of file regs.h.

#define SECURITY_CONFIG_CBC_XOR_PT_BITS   (1)

Definition at line 2303 of file regs.h.

#define SECURITY_CONFIG_CBC_XOR_PT_MASK   (0x00000010u)

Definition at line 2301 of file regs.h.

#define SECURITY_CONFIG_CT_TO_CBC_ST   (0x00000008u)

Definition at line 2305 of file regs.h.

#define SECURITY_CONFIG_CT_TO_CBC_ST_BIT   (3)

Definition at line 2307 of file regs.h.

#define SECURITY_CONFIG_CT_TO_CBC_ST_BITS   (1)

Definition at line 2308 of file regs.h.

#define SECURITY_CONFIG_CT_TO_CBC_ST_MASK   (0x00000008u)

Definition at line 2306 of file regs.h.

#define SECURITY_CONFIG_CTR_IN   (0x00000040u)

Definition at line 2290 of file regs.h.

#define SECURITY_CONFIG_CTR_IN_BIT   (6)

Definition at line 2292 of file regs.h.

#define SECURITY_CONFIG_CTR_IN_BITS   (1)

Definition at line 2293 of file regs.h.

#define SECURITY_CONFIG_CTR_IN_MASK   (0x00000040u)

Definition at line 2291 of file regs.h.

#define SECURITY_CONFIG_MIC_XOR_CT   (0x00000020u)

Definition at line 2295 of file regs.h.

#define SECURITY_CONFIG_MIC_XOR_CT_BIT   (5)

Definition at line 2297 of file regs.h.

#define SECURITY_CONFIG_MIC_XOR_CT_BITS   (1)

Definition at line 2298 of file regs.h.

#define SECURITY_CONFIG_MIC_XOR_CT_MASK   (0x00000020u)

Definition at line 2296 of file regs.h.

#define SECURITY_CONFIG_REG   *((volatile int32u *)0x40003000u)

Definition at line 2281 of file regs.h.

#define SECURITY_CONFIG_RESET   (0x00000000u)

Definition at line 2283 of file regs.h.

#define SECURITY_CONFIG_SEC_RST   (0x00000080u)

Definition at line 2285 of file regs.h.

#define SECURITY_CONFIG_SEC_RST_BIT   (7)

Definition at line 2287 of file regs.h.

#define SECURITY_CONFIG_SEC_RST_BITS   (1)

Definition at line 2288 of file regs.h.

#define SECURITY_CONFIG_SEC_RST_MASK   (0x00000080u)

Definition at line 2286 of file regs.h.

#define SECURITY_CONFIG_START_AES   (0x00000001u)

Definition at line 2320 of file regs.h.

#define SECURITY_CONFIG_START_AES_BIT   (0)

Definition at line 2322 of file regs.h.

#define SECURITY_CONFIG_START_AES_BITS   (1)

Definition at line 2323 of file regs.h.

#define SECURITY_CONFIG_START_AES_MASK   (0x00000001u)

Definition at line 2321 of file regs.h.

#define SECURITY_CONFIG_WAIT_CT_READ   (0x00000004u)

Definition at line 2310 of file regs.h.

#define SECURITY_CONFIG_WAIT_CT_READ_BIT   (2)

Definition at line 2312 of file regs.h.

#define SECURITY_CONFIG_WAIT_CT_READ_BITS   (1)

Definition at line 2313 of file regs.h.

#define SECURITY_CONFIG_WAIT_CT_READ_MASK   (0x00000004u)

Definition at line 2311 of file regs.h.

#define SECURITY_CONFIG_WAIT_PT_WRITE   (0x00000002u)

Definition at line 2315 of file regs.h.

#define SECURITY_CONFIG_WAIT_PT_WRITE_BIT   (1)

Definition at line 2317 of file regs.h.

#define SECURITY_CONFIG_WAIT_PT_WRITE_BITS   (1)

Definition at line 2318 of file regs.h.

#define SECURITY_CONFIG_WAIT_PT_WRITE_MASK   (0x00000002u)

Definition at line 2316 of file regs.h.

#define SECURITY_STATUS   *((volatile int32u *)0x40003004u)

Definition at line 2325 of file regs.h.

#define SECURITY_STATUS_ADDR   (0x40003004u)

Definition at line 2327 of file regs.h.

#define SECURITY_STATUS_REG   *((volatile int32u *)0x40003004u)

Definition at line 2326 of file regs.h.

#define SECURITY_STATUS_RESET   (0x00000000u)

Definition at line 2328 of file regs.h.

#define SECURITY_STATUS_SEC_BUSY   (0x00000001u)

Definition at line 2330 of file regs.h.

#define SECURITY_STATUS_SEC_BUSY_BIT   (0)

Definition at line 2332 of file regs.h.

#define SECURITY_STATUS_SEC_BUSY_BITS   (1)

Definition at line 2333 of file regs.h.

#define SECURITY_STATUS_SEC_BUSY_MASK   (0x00000001u)

Definition at line 2331 of file regs.h.

#define SEL_GPIO   (0x0000001Fu)

Definition at line 5466 of file regs.h.

#define SEL_GPIO   (0x0000001Fu)

Definition at line 5466 of file regs.h.

#define SEL_GPIO_BIT   (0)

Definition at line 5468 of file regs.h.

#define SEL_GPIO_BIT   (0)

Definition at line 5468 of file regs.h.

#define SEL_GPIO_BITS   (5)

Definition at line 5469 of file regs.h.

#define SEL_GPIO_BITS   (5)

Definition at line 5469 of file regs.h.

#define SEL_GPIO_MASK   (0x0000001Fu)

Definition at line 5467 of file regs.h.

#define SEL_GPIO_MASK   (0x0000001Fu)

Definition at line 5467 of file regs.h.

#define SHORT_ADDR   *((volatile int32u *)0x40002094u)

Definition at line 2095 of file regs.h.

#define SHORT_ADDR_ADDR   (0x40002094u)

Definition at line 2097 of file regs.h.

#define SHORT_ADDR_REG   *((volatile int32u *)0x40002094u)

Definition at line 2096 of file regs.h.

#define SHORT_ADDR_RESET   (0x00000000u)

Definition at line 2098 of file regs.h.

#define SHORT_ADDR_SHORT_ADDR   (0x0000FFFFu)

Definition at line 2100 of file regs.h.

#define SHORT_ADDR_SHORT_ADDR_BIT   (0)

Definition at line 2102 of file regs.h.

#define SHORT_ADDR_SHORT_ADDR_BITS   (16)

Definition at line 2103 of file regs.h.

#define SHORT_ADDR_SHORT_ADDR_MASK   (0x0000FFFFu)

Definition at line 2101 of file regs.h.

#define SILICON_ID   *((volatile int32u *)0x40004000u)

Definition at line 2440 of file regs.h.

#define SILICON_ID_ADDR   (0x40004000u)

Definition at line 2442 of file regs.h.

#define SILICON_ID_CHIP_TYPE   (0x00FF8000u)

Definition at line 2455 of file regs.h.

#define SILICON_ID_CHIP_TYPE_BIT   (15)

Definition at line 2457 of file regs.h.

#define SILICON_ID_CHIP_TYPE_BITS   (9)

Definition at line 2458 of file regs.h.

#define SILICON_ID_CHIP_TYPE_MASK   (0x00FF8000u)

Definition at line 2456 of file regs.h.

#define SILICON_ID_HW_VERSION   (0xF0000000u)

Definition at line 2445 of file regs.h.

#define SILICON_ID_HW_VERSION_BIT   (28)

Definition at line 2447 of file regs.h.

#define SILICON_ID_HW_VERSION_BITS   (4)

Definition at line 2448 of file regs.h.

#define SILICON_ID_HW_VERSION_MASK   (0xF0000000u)

Definition at line 2446 of file regs.h.

#define SILICON_ID_JEDEC_MAN_ID   (0x00000FFEu)

Definition at line 2465 of file regs.h.

#define SILICON_ID_JEDEC_MAN_ID_BIT   (1)

Definition at line 2467 of file regs.h.

#define SILICON_ID_JEDEC_MAN_ID_BITS   (11)

Definition at line 2468 of file regs.h.

#define SILICON_ID_JEDEC_MAN_ID_MASK   (0x00000FFEu)

Definition at line 2466 of file regs.h.

#define SILICON_ID_ONE   (0x00000001u)

Definition at line 2470 of file regs.h.

#define SILICON_ID_ONE_BIT   (0)

Definition at line 2472 of file regs.h.

#define SILICON_ID_ONE_BITS   (1)

Definition at line 2473 of file regs.h.

#define SILICON_ID_ONE_MASK   (0x00000001u)

Definition at line 2471 of file regs.h.

#define SILICON_ID_REG   *((volatile int32u *)0x40004000u)

Definition at line 2441 of file regs.h.

#define SILICON_ID_RESET   (0x069A862Bu)

Definition at line 2443 of file regs.h.

#define SILICON_ID_ST_DIVISION   (0x0F000000u)

Definition at line 2450 of file regs.h.

#define SILICON_ID_ST_DIVISION_BIT   (24)

Definition at line 2452 of file regs.h.

#define SILICON_ID_ST_DIVISION_BITS   (4)

Definition at line 2453 of file regs.h.

#define SILICON_ID_ST_DIVISION_MASK   (0x0F000000u)

Definition at line 2451 of file regs.h.

#define SILICON_ID_SUB_TYPE   (0x00007000u)

Definition at line 2460 of file regs.h.

#define SILICON_ID_SUB_TYPE_BIT   (12)

Definition at line 2462 of file regs.h.

#define SILICON_ID_SUB_TYPE_BITS   (3)

Definition at line 2463 of file regs.h.

#define SILICON_ID_SUB_TYPE_MASK   (0x00007000u)

Definition at line 2461 of file regs.h.

#define SLEEPTMR_CFG   *((volatile int32u *)0x4000600Cu)

Definition at line 2800 of file regs.h.

#define SLEEPTMR_CFG_ADDR   (0x4000600Cu)

Definition at line 2802 of file regs.h.

#define SLEEPTMR_CFG_REG   *((volatile int32u *)0x4000600Cu)

Definition at line 2801 of file regs.h.

#define SLEEPTMR_CFG_RESET   (0x00000400u)

Definition at line 2803 of file regs.h.

#define SLEEPTMR_CLK10KEN   (0x00000002u)

Definition at line 65 of file regs.h.

#define SLEEPTMR_CLK10KEN_BIT   (1)

Definition at line 67 of file regs.h.

#define SLEEPTMR_CLK10KEN_BITS   (1)

Definition at line 68 of file regs.h.

#define SLEEPTMR_CLK10KEN_MASK   (0x00000002u)

Definition at line 66 of file regs.h.

#define SLEEPTMR_CLK32KEN   (0x00000001u)

Definition at line 70 of file regs.h.

#define SLEEPTMR_CLK32KEN_BIT   (0)

Definition at line 72 of file regs.h.

#define SLEEPTMR_CLK32KEN_BITS   (1)

Definition at line 73 of file regs.h.

#define SLEEPTMR_CLK32KEN_MASK   (0x00000001u)

Definition at line 71 of file regs.h.

#define SLEEPTMR_CLKDIV   (0x000000F0u)

Definition at line 2820 of file regs.h.

#define SLEEPTMR_CLKDIV_BIT   (4)

Definition at line 2822 of file regs.h.

#define SLEEPTMR_CLKDIV_BITS   (4)

Definition at line 2823 of file regs.h.

#define SLEEPTMR_CLKDIV_MASK   (0x000000F0u)

Definition at line 2821 of file regs.h.

#define SLEEPTMR_CLKEN   *((volatile int32u *)0x40000008u)

Definition at line 60 of file regs.h.

#define SLEEPTMR_CLKEN_ADDR   (0x40000008u)

Definition at line 62 of file regs.h.

#define SLEEPTMR_CLKEN_REG   *((volatile int32u *)0x40000008u)

Definition at line 61 of file regs.h.

#define SLEEPTMR_CLKEN_RESET   (0x00000002u)

Definition at line 63 of file regs.h.

#define SLEEPTMR_CLKSEL   (0x00000001u)

Definition at line 2825 of file regs.h.

#define SLEEPTMR_CLKSEL_BIT   (0)

Definition at line 2827 of file regs.h.

#define SLEEPTMR_CLKSEL_BITS   (1)

Definition at line 2828 of file regs.h.

#define SLEEPTMR_CLKSEL_MASK   (0x00000001u)

Definition at line 2826 of file regs.h.

#define SLEEPTMR_CMPAH   *((volatile int32u *)0x40006018u)

Definition at line 2850 of file regs.h.

#define SLEEPTMR_CMPAH_ADDR   (0x40006018u)

Definition at line 2852 of file regs.h.

#define SLEEPTMR_CMPAH_FIELD   (0x0000FFFFu)

Definition at line 2855 of file regs.h.

#define SLEEPTMR_CMPAH_FIELD_BIT   (0)

Definition at line 2857 of file regs.h.

#define SLEEPTMR_CMPAH_FIELD_BITS   (16)

Definition at line 2858 of file regs.h.

#define SLEEPTMR_CMPAH_FIELD_MASK   (0x0000FFFFu)

Definition at line 2856 of file regs.h.

#define SLEEPTMR_CMPAH_REG   *((volatile int32u *)0x40006018u)

Definition at line 2851 of file regs.h.

#define SLEEPTMR_CMPAH_RESET   (0x0000FFFFu)

Definition at line 2853 of file regs.h.

#define SLEEPTMR_CMPAL   *((volatile int32u *)0x4000601Cu)

Definition at line 2860 of file regs.h.

#define SLEEPTMR_CMPAL_ADDR   (0x4000601Cu)

Definition at line 2862 of file regs.h.

#define SLEEPTMR_CMPAL_FIELD   (0x0000FFFFu)

Definition at line 2865 of file regs.h.

#define SLEEPTMR_CMPAL_FIELD_BIT   (0)

Definition at line 2867 of file regs.h.

#define SLEEPTMR_CMPAL_FIELD_BITS   (16)

Definition at line 2868 of file regs.h.

#define SLEEPTMR_CMPAL_FIELD_MASK   (0x0000FFFFu)

Definition at line 2866 of file regs.h.

#define SLEEPTMR_CMPAL_REG   *((volatile int32u *)0x4000601Cu)

Definition at line 2861 of file regs.h.

#define SLEEPTMR_CMPAL_RESET   (0x0000FFFFu)

Definition at line 2863 of file regs.h.

#define SLEEPTMR_CMPBH   *((volatile int32u *)0x40006020u)

Definition at line 2870 of file regs.h.

#define SLEEPTMR_CMPBH_ADDR   (0x40006020u)

Definition at line 2872 of file regs.h.

#define SLEEPTMR_CMPBH_FIELD   (0x0000FFFFu)

Definition at line 2875 of file regs.h.

#define SLEEPTMR_CMPBH_FIELD_BIT   (0)

Definition at line 2877 of file regs.h.

#define SLEEPTMR_CMPBH_FIELD_BITS   (16)

Definition at line 2878 of file regs.h.

#define SLEEPTMR_CMPBH_FIELD_MASK   (0x0000FFFFu)

Definition at line 2876 of file regs.h.

#define SLEEPTMR_CMPBH_REG   *((volatile int32u *)0x40006020u)

Definition at line 2871 of file regs.h.

#define SLEEPTMR_CMPBH_RESET   (0x0000FFFFu)

Definition at line 2873 of file regs.h.

#define SLEEPTMR_CMPBL   *((volatile int32u *)0x40006024u)

Definition at line 2880 of file regs.h.

#define SLEEPTMR_CMPBL_ADDR   (0x40006024u)

Definition at line 2882 of file regs.h.

#define SLEEPTMR_CMPBL_FIELD   (0x0000FFFFu)

Definition at line 2885 of file regs.h.

#define SLEEPTMR_CMPBL_FIELD_BIT   (0)

Definition at line 2887 of file regs.h.

#define SLEEPTMR_CMPBL_FIELD_BITS   (16)

Definition at line 2888 of file regs.h.

#define SLEEPTMR_CMPBL_FIELD_MASK   (0x0000FFFFu)

Definition at line 2886 of file regs.h.

#define SLEEPTMR_CMPBL_REG   *((volatile int32u *)0x40006024u)

Definition at line 2881 of file regs.h.

#define SLEEPTMR_CMPBL_RESET   (0x0000FFFFu)

Definition at line 2883 of file regs.h.

#define SLEEPTMR_CNTH   *((volatile int32u *)0x40006010u)

Definition at line 2830 of file regs.h.

#define SLEEPTMR_CNTH_ADDR   (0x40006010u)

Definition at line 2832 of file regs.h.

#define SLEEPTMR_CNTH_FIELD   (0x0000FFFFu)

Definition at line 2835 of file regs.h.

#define SLEEPTMR_CNTH_FIELD_BIT   (0)

Definition at line 2837 of file regs.h.

#define SLEEPTMR_CNTH_FIELD_BITS   (16)

Definition at line 2838 of file regs.h.

#define SLEEPTMR_CNTH_FIELD_MASK   (0x0000FFFFu)

Definition at line 2836 of file regs.h.

#define SLEEPTMR_CNTH_REG   *((volatile int32u *)0x40006010u)

Definition at line 2831 of file regs.h.

#define SLEEPTMR_CNTH_RESET   (0x00000000u)

Definition at line 2833 of file regs.h.

#define SLEEPTMR_CNTL   *((volatile int32u *)0x40006014u)

Definition at line 2840 of file regs.h.

#define SLEEPTMR_CNTL_ADDR   (0x40006014u)

Definition at line 2842 of file regs.h.

#define SLEEPTMR_CNTL_FIELD   (0x0000FFFFu)

Definition at line 2845 of file regs.h.

#define SLEEPTMR_CNTL_FIELD_BIT   (0)

Definition at line 2847 of file regs.h.

#define SLEEPTMR_CNTL_FIELD_BITS   (16)

Definition at line 2848 of file regs.h.

#define SLEEPTMR_CNTL_FIELD_MASK   (0x0000FFFFu)

Definition at line 2846 of file regs.h.

#define SLEEPTMR_CNTL_REG   *((volatile int32u *)0x40006014u)

Definition at line 2841 of file regs.h.

#define SLEEPTMR_CNTL_RESET   (0x00000000u)

Definition at line 2843 of file regs.h.

#define SLEEPTMR_DBGPAUSE   (0x00000400u)

Definition at line 2815 of file regs.h.

#define SLEEPTMR_DBGPAUSE_BIT   (10)

Definition at line 2817 of file regs.h.

#define SLEEPTMR_DBGPAUSE_BITS   (1)

Definition at line 2818 of file regs.h.

#define SLEEPTMR_DBGPAUSE_MASK   (0x00000400u)

Definition at line 2816 of file regs.h.

#define SLEEPTMR_ENABLE   (0x00000800u)

Definition at line 2810 of file regs.h.

#define SLEEPTMR_ENABLE_BIT   (11)

Definition at line 2812 of file regs.h.

#define SLEEPTMR_ENABLE_BITS   (1)

Definition at line 2813 of file regs.h.

#define SLEEPTMR_ENABLE_MASK   (0x00000800u)

Definition at line 2811 of file regs.h.

#define SLEEPTMR_REVERSE   (0x00001000u)

Definition at line 2805 of file regs.h.

#define SLEEPTMR_REVERSE_BIT   (12)

Definition at line 2807 of file regs.h.

#define SLEEPTMR_REVERSE_BITS   (1)

Definition at line 2808 of file regs.h.

#define SLEEPTMR_REVERSE_MASK   (0x00001000u)

Definition at line 2806 of file regs.h.

#define ST_CALVR   *((volatile int32u *)0xE000E01Cu)

Definition at line 9250 of file regs.h.

#define ST_CALVR_ADDR   (0xE000E01Cu)

Definition at line 9252 of file regs.h.

#define ST_CALVR_NOREF   (0x80000000u)

Definition at line 9255 of file regs.h.

#define ST_CALVR_NOREF_BIT   (31)

Definition at line 9257 of file regs.h.

#define ST_CALVR_NOREF_BITS   (1)

Definition at line 9258 of file regs.h.

#define ST_CALVR_NOREF_MASK   (0x80000000u)

Definition at line 9256 of file regs.h.

#define ST_CALVR_REG   *((volatile int32u *)0xE000E01Cu)

Definition at line 9251 of file regs.h.

#define ST_CALVR_RESET   (0x00000000u)

Definition at line 9253 of file regs.h.

#define ST_CALVR_SKEW   (0x40000000u)

Definition at line 9260 of file regs.h.

#define ST_CALVR_SKEW_BIT   (30)

Definition at line 9262 of file regs.h.

#define ST_CALVR_SKEW_BITS   (1)

Definition at line 9263 of file regs.h.

#define ST_CALVR_SKEW_MASK   (0x40000000u)

Definition at line 9261 of file regs.h.

#define ST_CALVR_TENMS   (0x00FFFFFFu)

Definition at line 9265 of file regs.h.

#define ST_CALVR_TENMS_BIT   (0)

Definition at line 9267 of file regs.h.

#define ST_CALVR_TENMS_BITS   (24)

Definition at line 9268 of file regs.h.

#define ST_CALVR_TENMS_MASK   (0x00FFFFFFu)

Definition at line 9266 of file regs.h.

#define ST_CSR   *((volatile int32u *)0xE000E010u)

Definition at line 9205 of file regs.h.

#define ST_CSR_ADDR   (0xE000E010u)

Definition at line 9207 of file regs.h.

#define ST_CSR_CLKSOURCE   (0x00000004u)

Definition at line 9215 of file regs.h.

#define ST_CSR_CLKSOURCE_BIT   (2)

Definition at line 9217 of file regs.h.

#define ST_CSR_CLKSOURCE_BITS   (1)

Definition at line 9218 of file regs.h.

#define ST_CSR_CLKSOURCE_MASK   (0x00000004u)

Definition at line 9216 of file regs.h.

#define ST_CSR_COUNTFLAG   (0x00010000u)

Definition at line 9210 of file regs.h.

#define ST_CSR_COUNTFLAG_BIT   (16)

Definition at line 9212 of file regs.h.

#define ST_CSR_COUNTFLAG_BITS   (1)

Definition at line 9213 of file regs.h.

#define ST_CSR_COUNTFLAG_MASK   (0x00010000u)

Definition at line 9211 of file regs.h.

#define ST_CSR_ENABLE   (0x00000001u)

Definition at line 9225 of file regs.h.

#define ST_CSR_ENABLE_BIT   (0)

Definition at line 9227 of file regs.h.

#define ST_CSR_ENABLE_BITS   (1)

Definition at line 9228 of file regs.h.

#define ST_CSR_ENABLE_MASK   (0x00000001u)

Definition at line 9226 of file regs.h.

#define ST_CSR_REG   *((volatile int32u *)0xE000E010u)

Definition at line 9206 of file regs.h.

#define ST_CSR_RESET   (0x00000000u)

Definition at line 9208 of file regs.h.

#define ST_CSR_TICKINT   (0x00000002u)

Definition at line 9220 of file regs.h.

#define ST_CSR_TICKINT_BIT   (1)

Definition at line 9222 of file regs.h.

#define ST_CSR_TICKINT_BITS   (1)

Definition at line 9223 of file regs.h.

#define ST_CSR_TICKINT_MASK   (0x00000002u)

Definition at line 9221 of file regs.h.

#define ST_CVR   *((volatile int32u *)0xE000E018u)

Definition at line 9240 of file regs.h.

#define ST_CVR_ADDR   (0xE000E018u)

Definition at line 9242 of file regs.h.

#define ST_CVR_CURRENT   (0xFFFFFFFFu)

Definition at line 9245 of file regs.h.

#define ST_CVR_CURRENT_BIT   (0)

Definition at line 9247 of file regs.h.

#define ST_CVR_CURRENT_BITS   (32)

Definition at line 9248 of file regs.h.

#define ST_CVR_CURRENT_MASK   (0xFFFFFFFFu)

Definition at line 9246 of file regs.h.

#define ST_CVR_REG   *((volatile int32u *)0xE000E018u)

Definition at line 9241 of file regs.h.

#define ST_CVR_RESET   (0x00000000u)

Definition at line 9243 of file regs.h.

#define ST_RVR   *((volatile int32u *)0xE000E014u)

Definition at line 9230 of file regs.h.

#define ST_RVR_ADDR   (0xE000E014u)

Definition at line 9232 of file regs.h.

#define ST_RVR_REG   *((volatile int32u *)0xE000E014u)

Definition at line 9231 of file regs.h.

#define ST_RVR_RELOAD   (0x00FFFFFFu)

Definition at line 9235 of file regs.h.

#define ST_RVR_RELOAD_BIT   (0)

Definition at line 9237 of file regs.h.

#define ST_RVR_RELOAD_BITS   (24)

Definition at line 9238 of file regs.h.

#define ST_RVR_RELOAD_MASK   (0x00FFFFFFu)

Definition at line 9236 of file regs.h.

#define ST_RVR_RESET   (0x00000000u)

Definition at line 9233 of file regs.h.

#define SYNTH_FREQ_H   *((volatile int32u *)0x400010C4u)

Definition at line 1080 of file regs.h.

#define SYNTH_FREQ_H_ADDR   (0x400010C4u)

Definition at line 1082 of file regs.h.

#define SYNTH_FREQ_H_REG   *((volatile int32u *)0x400010C4u)

Definition at line 1081 of file regs.h.

#define SYNTH_FREQ_H_RESET   (0x00000003u)

Definition at line 1083 of file regs.h.

#define SYNTH_FREQ_H_SYNTH_FREQ_H   (0x00000003u)

Definition at line 1085 of file regs.h.

#define SYNTH_FREQ_H_SYNTH_FREQ_H_BIT   (0)

Definition at line 1087 of file regs.h.

#define SYNTH_FREQ_H_SYNTH_FREQ_H_BITS   (2)

Definition at line 1088 of file regs.h.

#define SYNTH_FREQ_H_SYNTH_FREQ_H_MASK   (0x00000003u)

Definition at line 1086 of file regs.h.

#define SYNTH_FREQ_L   *((volatile int32u *)0x400010C8u)

Definition at line 1090 of file regs.h.

#define SYNTH_FREQ_L_ADDR   (0x400010C8u)

Definition at line 1092 of file regs.h.

#define SYNTH_FREQ_L_REG   *((volatile int32u *)0x400010C8u)

Definition at line 1091 of file regs.h.

#define SYNTH_FREQ_L_RESET   (0x00003800u)

Definition at line 1093 of file regs.h.

#define SYNTH_FREQ_L_SYNTH_FREQ_L   (0x0000FFFFu)

Definition at line 1095 of file regs.h.

#define SYNTH_FREQ_L_SYNTH_FREQ_L_BIT   (0)

Definition at line 1097 of file regs.h.

#define SYNTH_FREQ_L_SYNTH_FREQ_L_BITS   (16)

Definition at line 1098 of file regs.h.

#define SYNTH_FREQ_L_SYNTH_FREQ_L_MASK   (0x0000FFFFu)

Definition at line 1096 of file regs.h.

#define SYNTH_LOCK   *((volatile int32u *)0x400010FCu)

Definition at line 1300 of file regs.h.

#define SYNTH_LOCK_ADDR   (0x400010FCu)

Definition at line 1302 of file regs.h.

#define SYNTH_LOCK_IN_LOCK   (0x00000001u)

Definition at line 1305 of file regs.h.

#define SYNTH_LOCK_IN_LOCK_BIT   (0)

Definition at line 1307 of file regs.h.

#define SYNTH_LOCK_IN_LOCK_BITS   (1)

Definition at line 1308 of file regs.h.

#define SYNTH_LOCK_IN_LOCK_MASK   (0x00000001u)

Definition at line 1306 of file regs.h.

#define SYNTH_LOCK_REG   *((volatile int32u *)0x400010FCu)

Definition at line 1301 of file regs.h.

#define SYNTH_LOCK_RESET   (0x00000000u)

Definition at line 1303 of file regs.h.

#define SYNTH_START   *((volatile int32u *)0x40001058u)

Definition at line 675 of file regs.h.

#define SYNTH_START_ADDR   (0x40001058u)

Definition at line 677 of file regs.h.

#define SYNTH_START_REG   *((volatile int32u *)0x40001058u)

Definition at line 676 of file regs.h.

#define SYNTH_START_RESET   (0x00006464u)

Definition at line 678 of file regs.h.

#define SYNTH_START_SYNTH_COLD_START   (0x000000FFu)

Definition at line 685 of file regs.h.

#define SYNTH_START_SYNTH_COLD_START_BIT   (0)

Definition at line 687 of file regs.h.

#define SYNTH_START_SYNTH_COLD_START_BITS   (8)

Definition at line 688 of file regs.h.

#define SYNTH_START_SYNTH_COLD_START_MASK   (0x000000FFu)

Definition at line 686 of file regs.h.

#define SYNTH_START_SYNTH_WARM_START   (0x0000FF00u)

Definition at line 680 of file regs.h.

#define SYNTH_START_SYNTH_WARM_START_BIT   (8)

Definition at line 682 of file regs.h.

#define SYNTH_START_SYNTH_WARM_START_BITS   (8)

Definition at line 683 of file regs.h.

#define SYNTH_START_SYNTH_WARM_START_MASK   (0x0000FF00u)

Definition at line 681 of file regs.h.

#define TEST_FORCE_ALL_INT   *((volatile int32u *)0x4000A024u)

Definition at line 3520 of file regs.h.

#define TEST_FORCE_ALL_INT_ADDR   (0x4000A024u)

Definition at line 3522 of file regs.h.

#define TEST_FORCE_ALL_INT_FORCE_ALL_INT   (0x00000001u)

Definition at line 3525 of file regs.h.

#define TEST_FORCE_ALL_INT_FORCE_ALL_INT_BIT   (0)

Definition at line 3527 of file regs.h.

#define TEST_FORCE_ALL_INT_FORCE_ALL_INT_BITS   (1)

Definition at line 3528 of file regs.h.

#define TEST_FORCE_ALL_INT_FORCE_ALL_INT_MASK   (0x00000001u)

Definition at line 3526 of file regs.h.

#define TEST_FORCE_ALL_INT_REG   *((volatile int32u *)0x4000A024u)

Definition at line 3521 of file regs.h.

#define TEST_FORCE_ALL_INT_RESET   (0x00000000u)

Definition at line 3523 of file regs.h.

#define TIM1_ARR   *((volatile int32u *)0x4000E02Cu)

Definition at line 7065 of file regs.h.

#define TIM1_ARR_ADDR   (0x4000E02Cu)

Definition at line 7067 of file regs.h.

#define TIM1_ARR_REG   *((volatile int32u *)0x4000E02Cu)

Definition at line 7066 of file regs.h.

#define TIM1_ARR_RESET   (0x0000FFFFu)

Definition at line 7068 of file regs.h.

#define TIM1_CCER   *((volatile int32u *)0x4000E020u)

Definition at line 7000 of file regs.h.

#define TIM1_CCER_ADDR   (0x4000E020u)

Definition at line 7002 of file regs.h.

#define TIM1_CCER_REG   *((volatile int32u *)0x4000E020u)

Definition at line 7001 of file regs.h.

#define TIM1_CCER_RESET   (0x00000000u)

Definition at line 7003 of file regs.h.

#define TIM1_CCMR1   *((volatile int32u *)0x4000E018u)

Definition at line 6850 of file regs.h.

#define TIM1_CCMR1_ADDR   (0x4000E018u)

Definition at line 6852 of file regs.h.

#define TIM1_CCMR1_REG   *((volatile int32u *)0x4000E018u)

Definition at line 6851 of file regs.h.

#define TIM1_CCMR1_RESET   (0x00000000u)

Definition at line 6853 of file regs.h.

#define TIM1_CCMR2   *((volatile int32u *)0x4000E01Cu)

Definition at line 6925 of file regs.h.

#define TIM1_CCMR2_ADDR   (0x4000E01Cu)

Definition at line 6927 of file regs.h.

#define TIM1_CCMR2_REG   *((volatile int32u *)0x4000E01Cu)

Definition at line 6926 of file regs.h.

#define TIM1_CCMR2_RESET   (0x00000000u)

Definition at line 6928 of file regs.h.

#define TIM1_CCR1   *((volatile int32u *)0x4000E034u)

Definition at line 7075 of file regs.h.

#define TIM1_CCR1_ADDR   (0x4000E034u)

Definition at line 7077 of file regs.h.

#define TIM1_CCR1_REG   *((volatile int32u *)0x4000E034u)

Definition at line 7076 of file regs.h.

#define TIM1_CCR1_RESET   (0x00000000u)

Definition at line 7078 of file regs.h.

#define TIM1_CCR2   *((volatile int32u *)0x4000E038u)

Definition at line 7085 of file regs.h.

#define TIM1_CCR2_ADDR   (0x4000E038u)

Definition at line 7087 of file regs.h.

#define TIM1_CCR2_REG   *((volatile int32u *)0x4000E038u)

Definition at line 7086 of file regs.h.

#define TIM1_CCR2_RESET   (0x00000000u)

Definition at line 7088 of file regs.h.

#define TIM1_CCR3   *((volatile int32u *)0x4000E03Cu)

Definition at line 7095 of file regs.h.

#define TIM1_CCR3_ADDR   (0x4000E03Cu)

Definition at line 7097 of file regs.h.

#define TIM1_CCR3_REG   *((volatile int32u *)0x4000E03Cu)

Definition at line 7096 of file regs.h.

#define TIM1_CCR3_RESET   (0x00000000u)

Definition at line 7098 of file regs.h.

#define TIM1_CCR4   *((volatile int32u *)0x4000E040u)

Definition at line 7105 of file regs.h.

#define TIM1_CCR4_ADDR   (0x4000E040u)

Definition at line 7107 of file regs.h.

#define TIM1_CCR4_REG   *((volatile int32u *)0x4000E040u)

Definition at line 7106 of file regs.h.

#define TIM1_CCR4_RESET   (0x00000000u)

Definition at line 7108 of file regs.h.

#define TIM1_CNT   *((volatile int32u *)0x4000E024u)

Definition at line 7045 of file regs.h.

#define TIM1_CNT_ADDR   (0x4000E024u)

Definition at line 7047 of file regs.h.

#define TIM1_CNT_REG   *((volatile int32u *)0x4000E024u)

Definition at line 7046 of file regs.h.

#define TIM1_CNT_RESET   (0x00000000u)

Definition at line 7048 of file regs.h.

#define TIM1_CR1   *((volatile int32u *)0x4000E000u)

Definition at line 6630 of file regs.h.

#define TIM1_CR1_ADDR   (0x4000E000u)

Definition at line 6632 of file regs.h.

#define TIM1_CR1_REG   *((volatile int32u *)0x4000E000u)

Definition at line 6631 of file regs.h.

#define TIM1_CR1_RESET   (0x00000000u)

Definition at line 6633 of file regs.h.

#define TIM1_CR2   *((volatile int32u *)0x4000E004u)

Definition at line 6670 of file regs.h.

#define TIM1_CR2_ADDR   (0x4000E004u)

Definition at line 6672 of file regs.h.

#define TIM1_CR2_REG   *((volatile int32u *)0x4000E004u)

Definition at line 6671 of file regs.h.

#define TIM1_CR2_RESET   (0x00000000u)

Definition at line 6673 of file regs.h.

#define TIM1_EGR   *((volatile int32u *)0x4000E014u)

Definition at line 6815 of file regs.h.

#define TIM1_EGR_ADDR   (0x4000E014u)

Definition at line 6817 of file regs.h.

#define TIM1_EGR_REG   *((volatile int32u *)0x4000E014u)

Definition at line 6816 of file regs.h.

#define TIM1_EGR_RESET   (0x00000000u)

Definition at line 6818 of file regs.h.

#define TIM1_EXTRIGSEL   (0x00000003u)

Definition at line 7660 of file regs.h.

#define TIM1_EXTRIGSEL   (0x00000003u)

Definition at line 7660 of file regs.h.

#define TIM1_EXTRIGSEL_BIT   (0)

Definition at line 7662 of file regs.h.

#define TIM1_EXTRIGSEL_BIT   (0)

Definition at line 7662 of file regs.h.

#define TIM1_EXTRIGSEL_BITS   (2)

Definition at line 7663 of file regs.h.

#define TIM1_EXTRIGSEL_BITS   (2)

Definition at line 7663 of file regs.h.

#define TIM1_EXTRIGSEL_MASK   (0x00000003u)

Definition at line 7661 of file regs.h.

#define TIM1_EXTRIGSEL_MASK   (0x00000003u)

Definition at line 7661 of file regs.h.

#define TIM1_OR   *((volatile int32u *)0x4000E050u)

Definition at line 7115 of file regs.h.

#define TIM1_OR_ADDR   (0x4000E050u)

Definition at line 7117 of file regs.h.

#define TIM1_OR_REG   *((volatile int32u *)0x4000E050u)

Definition at line 7116 of file regs.h.

#define TIM1_OR_RESET   (0x00000000u)

Definition at line 7118 of file regs.h.

#define TIM1_PSC   *((volatile int32u *)0x4000E028u)

Definition at line 7055 of file regs.h.

#define TIM1_PSC_ADDR   (0x4000E028u)

Definition at line 7057 of file regs.h.

#define TIM1_PSC_REG   *((volatile int32u *)0x4000E028u)

Definition at line 7056 of file regs.h.

#define TIM1_PSC_RESET   (0x00000000u)

Definition at line 7058 of file regs.h.

#define TIM1_SMCR   *((volatile int32u *)0x4000E008u)

Definition at line 6685 of file regs.h.

#define TIM1_SMCR_ADDR   (0x4000E008u)

Definition at line 6687 of file regs.h.

#define TIM1_SMCR_REG   *((volatile int32u *)0x4000E008u)

Definition at line 6686 of file regs.h.

#define TIM1_SMCR_RESET   (0x00000000u)

Definition at line 6688 of file regs.h.

#define TIM2_ARR   *((volatile int32u *)0x4000F02Cu)

Definition at line 7575 of file regs.h.

#define TIM2_ARR_ADDR   (0x4000F02Cu)

Definition at line 7577 of file regs.h.

#define TIM2_ARR_REG   *((volatile int32u *)0x4000F02Cu)

Definition at line 7576 of file regs.h.

#define TIM2_ARR_RESET   (0x0000FFFFu)

Definition at line 7578 of file regs.h.

#define TIM2_CCER   *((volatile int32u *)0x4000F020u)

Definition at line 7510 of file regs.h.

#define TIM2_CCER_ADDR   (0x4000F020u)

Definition at line 7512 of file regs.h.

#define TIM2_CCER_REG   *((volatile int32u *)0x4000F020u)

Definition at line 7511 of file regs.h.

#define TIM2_CCER_RESET   (0x00000000u)

Definition at line 7513 of file regs.h.

#define TIM2_CCMR1   *((volatile int32u *)0x4000F018u)

Definition at line 7360 of file regs.h.

#define TIM2_CCMR1_ADDR   (0x4000F018u)

Definition at line 7362 of file regs.h.

#define TIM2_CCMR1_REG   *((volatile int32u *)0x4000F018u)

Definition at line 7361 of file regs.h.

#define TIM2_CCMR1_RESET   (0x00000000u)

Definition at line 7363 of file regs.h.

#define TIM2_CCMR2   *((volatile int32u *)0x4000F01Cu)

Definition at line 7435 of file regs.h.

#define TIM2_CCMR2_ADDR   (0x4000F01Cu)

Definition at line 7437 of file regs.h.

#define TIM2_CCMR2_REG   *((volatile int32u *)0x4000F01Cu)

Definition at line 7436 of file regs.h.

#define TIM2_CCMR2_RESET   (0x00000000u)

Definition at line 7438 of file regs.h.

#define TIM2_CCR1   *((volatile int32u *)0x4000F034u)

Definition at line 7585 of file regs.h.

#define TIM2_CCR1_ADDR   (0x4000F034u)

Definition at line 7587 of file regs.h.

#define TIM2_CCR1_REG   *((volatile int32u *)0x4000F034u)

Definition at line 7586 of file regs.h.

#define TIM2_CCR1_RESET   (0x00000000u)

Definition at line 7588 of file regs.h.

#define TIM2_CCR2   *((volatile int32u *)0x4000F038u)

Definition at line 7595 of file regs.h.

#define TIM2_CCR2_ADDR   (0x4000F038u)

Definition at line 7597 of file regs.h.

#define TIM2_CCR2_REG   *((volatile int32u *)0x4000F038u)

Definition at line 7596 of file regs.h.

#define TIM2_CCR2_RESET   (0x00000000u)

Definition at line 7598 of file regs.h.

#define TIM2_CCR3   *((volatile int32u *)0x4000F03Cu)

Definition at line 7605 of file regs.h.

#define TIM2_CCR3_ADDR   (0x4000F03Cu)

Definition at line 7607 of file regs.h.

#define TIM2_CCR3_REG   *((volatile int32u *)0x4000F03Cu)

Definition at line 7606 of file regs.h.

#define TIM2_CCR3_RESET   (0x00000000u)

Definition at line 7608 of file regs.h.

#define TIM2_CCR4   *((volatile int32u *)0x4000F040u)

Definition at line 7615 of file regs.h.

#define TIM2_CCR4_ADDR   (0x4000F040u)

Definition at line 7617 of file regs.h.

#define TIM2_CCR4_REG   *((volatile int32u *)0x4000F040u)

Definition at line 7616 of file regs.h.

#define TIM2_CCR4_RESET   (0x00000000u)

Definition at line 7618 of file regs.h.

#define TIM2_CNT   *((volatile int32u *)0x4000F024u)

Definition at line 7555 of file regs.h.

#define TIM2_CNT_ADDR   (0x4000F024u)

Definition at line 7557 of file regs.h.

#define TIM2_CNT_REG   *((volatile int32u *)0x4000F024u)

Definition at line 7556 of file regs.h.

#define TIM2_CNT_RESET   (0x00000000u)

Definition at line 7558 of file regs.h.

#define TIM2_CR1   *((volatile int32u *)0x4000F000u)

Definition at line 7140 of file regs.h.

#define TIM2_CR1_ADDR   (0x4000F000u)

Definition at line 7142 of file regs.h.

#define TIM2_CR1_REG   *((volatile int32u *)0x4000F000u)

Definition at line 7141 of file regs.h.

#define TIM2_CR1_RESET   (0x00000000u)

Definition at line 7143 of file regs.h.

#define TIM2_CR2   *((volatile int32u *)0x4000F004u)

Definition at line 7180 of file regs.h.

#define TIM2_CR2_ADDR   (0x4000F004u)

Definition at line 7182 of file regs.h.

#define TIM2_CR2_REG   *((volatile int32u *)0x4000F004u)

Definition at line 7181 of file regs.h.

#define TIM2_CR2_RESET   (0x00000000u)

Definition at line 7183 of file regs.h.

#define TIM2_EGR   *((volatile int32u *)0x4000F014u)

Definition at line 7325 of file regs.h.

#define TIM2_EGR_ADDR   (0x4000F014u)

Definition at line 7327 of file regs.h.

#define TIM2_EGR_REG   *((volatile int32u *)0x4000F014u)

Definition at line 7326 of file regs.h.

#define TIM2_EGR_RESET   (0x00000000u)

Definition at line 7328 of file regs.h.

#define TIM2_OR   *((volatile int32u *)0x4000F050u)

Definition at line 7625 of file regs.h.

#define TIM2_OR_ADDR   (0x4000F050u)

Definition at line 7627 of file regs.h.

#define TIM2_OR_REG   *((volatile int32u *)0x4000F050u)

Definition at line 7626 of file regs.h.

#define TIM2_OR_RESET   (0x00000000u)

Definition at line 7628 of file regs.h.

#define TIM2_PSC   *((volatile int32u *)0x4000F028u)

Definition at line 7565 of file regs.h.

#define TIM2_PSC_ADDR   (0x4000F028u)

Definition at line 7567 of file regs.h.

#define TIM2_PSC_REG   *((volatile int32u *)0x4000F028u)

Definition at line 7566 of file regs.h.

#define TIM2_PSC_RESET   (0x00000000u)

Definition at line 7568 of file regs.h.

#define TIM2_SMCR   *((volatile int32u *)0x4000F008u)

Definition at line 7195 of file regs.h.

#define TIM2_SMCR_ADDR   (0x4000F008u)

Definition at line 7197 of file regs.h.

#define TIM2_SMCR_REG   *((volatile int32u *)0x4000F008u)

Definition at line 7196 of file regs.h.

#define TIM2_SMCR_RESET   (0x00000000u)

Definition at line 7198 of file regs.h.

#define TIM_ARBE   (0x00000080u)

Definition at line 7145 of file regs.h.

#define TIM_ARBE   (0x00000080u)

Definition at line 7145 of file regs.h.

#define TIM_ARBE_BIT   (7)

Definition at line 7147 of file regs.h.

#define TIM_ARBE_BIT   (7)

Definition at line 7147 of file regs.h.

#define TIM_ARBE_BITS   (1)

Definition at line 7148 of file regs.h.

#define TIM_ARBE_BITS   (1)

Definition at line 7148 of file regs.h.

#define TIM_ARBE_MASK   (0x00000080u)

Definition at line 7146 of file regs.h.

#define TIM_ARBE_MASK   (0x00000080u)

Definition at line 7146 of file regs.h.

#define TIM_ARR   (0x0000FFFFu)

Definition at line 7580 of file regs.h.

#define TIM_ARR   (0x0000FFFFu)

Definition at line 7580 of file regs.h.

#define TIM_ARR_BIT   (0)

Definition at line 7582 of file regs.h.

#define TIM_ARR_BIT   (0)

Definition at line 7582 of file regs.h.

#define TIM_ARR_BITS   (16)

Definition at line 7583 of file regs.h.

#define TIM_ARR_BITS   (16)

Definition at line 7583 of file regs.h.

#define TIM_ARR_MASK   (0x0000FFFFu)

Definition at line 7581 of file regs.h.

#define TIM_ARR_MASK   (0x0000FFFFu)

Definition at line 7581 of file regs.h.

#define TIM_CC1E   (0x00000001u)

Definition at line 7550 of file regs.h.

#define TIM_CC1E   (0x00000001u)

Definition at line 7550 of file regs.h.

#define TIM_CC1E_BIT   (0)

Definition at line 7552 of file regs.h.

#define TIM_CC1E_BIT   (0)

Definition at line 7552 of file regs.h.

#define TIM_CC1E_BITS   (1)

Definition at line 7553 of file regs.h.

#define TIM_CC1E_BITS   (1)

Definition at line 7553 of file regs.h.

#define TIM_CC1E_MASK   (0x00000001u)

Definition at line 7551 of file regs.h.

#define TIM_CC1E_MASK   (0x00000001u)

Definition at line 7551 of file regs.h.

#define TIM_CC1G   (0x00000002u)

Definition at line 7350 of file regs.h.

#define TIM_CC1G   (0x00000002u)

Definition at line 7350 of file regs.h.

#define TIM_CC1G_BIT   (1)

Definition at line 7352 of file regs.h.

#define TIM_CC1G_BIT   (1)

Definition at line 7352 of file regs.h.

#define TIM_CC1G_BITS   (1)

Definition at line 7353 of file regs.h.

#define TIM_CC1G_BITS   (1)

Definition at line 7353 of file regs.h.

#define TIM_CC1G_MASK   (0x00000002u)

Definition at line 7351 of file regs.h.

#define TIM_CC1G_MASK   (0x00000002u)

Definition at line 7351 of file regs.h.

#define TIM_CC1P   (0x00000002u)

Definition at line 7545 of file regs.h.

#define TIM_CC1P   (0x00000002u)

Definition at line 7545 of file regs.h.

#define TIM_CC1P_BIT   (1)

Definition at line 7547 of file regs.h.

#define TIM_CC1P_BIT   (1)

Definition at line 7547 of file regs.h.

#define TIM_CC1P_BITS   (1)

Definition at line 7548 of file regs.h.

#define TIM_CC1P_BITS   (1)

Definition at line 7548 of file regs.h.

#define TIM_CC1P_MASK   (0x00000002u)

Definition at line 7546 of file regs.h.

#define TIM_CC1P_MASK   (0x00000002u)

Definition at line 7546 of file regs.h.

#define TIM_CC1S   (0x00000003u)

Definition at line 7430 of file regs.h.

#define TIM_CC1S   (0x00000003u)

Definition at line 7430 of file regs.h.

#define TIM_CC1S_BIT   (0)

Definition at line 7432 of file regs.h.

#define TIM_CC1S_BIT   (0)

Definition at line 7432 of file regs.h.

#define TIM_CC1S_BITS   (2)

Definition at line 7433 of file regs.h.

#define TIM_CC1S_BITS   (2)

Definition at line 7433 of file regs.h.

#define TIM_CC1S_MASK   (0x00000003u)

Definition at line 7431 of file regs.h.

#define TIM_CC1S_MASK   (0x00000003u)

Definition at line 7431 of file regs.h.

#define TIM_CC2E   (0x00000010u)

Definition at line 7540 of file regs.h.

#define TIM_CC2E   (0x00000010u)

Definition at line 7540 of file regs.h.

#define TIM_CC2E_BIT   (4)

Definition at line 7542 of file regs.h.

#define TIM_CC2E_BIT   (4)

Definition at line 7542 of file regs.h.

#define TIM_CC2E_BITS   (1)

Definition at line 7543 of file regs.h.

#define TIM_CC2E_BITS   (1)

Definition at line 7543 of file regs.h.

#define TIM_CC2E_MASK   (0x00000010u)

Definition at line 7541 of file regs.h.

#define TIM_CC2E_MASK   (0x00000010u)

Definition at line 7541 of file regs.h.

#define TIM_CC2G   (0x00000004u)

Definition at line 7345 of file regs.h.

#define TIM_CC2G   (0x00000004u)

Definition at line 7345 of file regs.h.

#define TIM_CC2G_BIT   (2)

Definition at line 7347 of file regs.h.

#define TIM_CC2G_BIT   (2)

Definition at line 7347 of file regs.h.

#define TIM_CC2G_BITS   (1)

Definition at line 7348 of file regs.h.

#define TIM_CC2G_BITS   (1)

Definition at line 7348 of file regs.h.

#define TIM_CC2G_MASK   (0x00000004u)

Definition at line 7346 of file regs.h.

#define TIM_CC2G_MASK   (0x00000004u)

Definition at line 7346 of file regs.h.

#define TIM_CC2P   (0x00000020u)

Definition at line 7535 of file regs.h.

#define TIM_CC2P   (0x00000020u)

Definition at line 7535 of file regs.h.

#define TIM_CC2P_BIT   (5)

Definition at line 7537 of file regs.h.

#define TIM_CC2P_BIT   (5)

Definition at line 7537 of file regs.h.

#define TIM_CC2P_BITS   (1)

Definition at line 7538 of file regs.h.

#define TIM_CC2P_BITS   (1)

Definition at line 7538 of file regs.h.

#define TIM_CC2P_MASK   (0x00000020u)

Definition at line 7536 of file regs.h.

#define TIM_CC2P_MASK   (0x00000020u)

Definition at line 7536 of file regs.h.

#define TIM_CC2S   (0x00000300u)

Definition at line 7405 of file regs.h.

#define TIM_CC2S   (0x00000300u)

Definition at line 7405 of file regs.h.

#define TIM_CC2S_BIT   (8)

Definition at line 7407 of file regs.h.

#define TIM_CC2S_BIT   (8)

Definition at line 7407 of file regs.h.

#define TIM_CC2S_BITS   (2)

Definition at line 7408 of file regs.h.

#define TIM_CC2S_BITS   (2)

Definition at line 7408 of file regs.h.

#define TIM_CC2S_MASK   (0x00000300u)

Definition at line 7406 of file regs.h.

#define TIM_CC2S_MASK   (0x00000300u)

Definition at line 7406 of file regs.h.

#define TIM_CC3E   (0x00000100u)

Definition at line 7530 of file regs.h.

#define TIM_CC3E   (0x00000100u)

Definition at line 7530 of file regs.h.

#define TIM_CC3E_BIT   (8)

Definition at line 7532 of file regs.h.

#define TIM_CC3E_BIT   (8)

Definition at line 7532 of file regs.h.

#define TIM_CC3E_BITS   (1)

Definition at line 7533 of file regs.h.

#define TIM_CC3E_BITS   (1)

Definition at line 7533 of file regs.h.

#define TIM_CC3E_MASK   (0x00000100u)

Definition at line 7531 of file regs.h.

#define TIM_CC3E_MASK   (0x00000100u)

Definition at line 7531 of file regs.h.

#define TIM_CC3G   (0x00000008u)

Definition at line 7340 of file regs.h.

#define TIM_CC3G   (0x00000008u)

Definition at line 7340 of file regs.h.

#define TIM_CC3G_BIT   (3)

Definition at line 7342 of file regs.h.

#define TIM_CC3G_BIT   (3)

Definition at line 7342 of file regs.h.

#define TIM_CC3G_BITS   (1)

Definition at line 7343 of file regs.h.

#define TIM_CC3G_BITS   (1)

Definition at line 7343 of file regs.h.

#define TIM_CC3G_MASK   (0x00000008u)

Definition at line 7341 of file regs.h.

#define TIM_CC3G_MASK   (0x00000008u)

Definition at line 7341 of file regs.h.

#define TIM_CC3P   (0x00000200u)

Definition at line 7525 of file regs.h.

#define TIM_CC3P   (0x00000200u)

Definition at line 7525 of file regs.h.

#define TIM_CC3P_BIT   (9)

Definition at line 7527 of file regs.h.

#define TIM_CC3P_BIT   (9)

Definition at line 7527 of file regs.h.

#define TIM_CC3P_BITS   (1)

Definition at line 7528 of file regs.h.

#define TIM_CC3P_BITS   (1)

Definition at line 7528 of file regs.h.

#define TIM_CC3P_MASK   (0x00000200u)

Definition at line 7526 of file regs.h.

#define TIM_CC3P_MASK   (0x00000200u)

Definition at line 7526 of file regs.h.

#define TIM_CC3S   (0x00000003u)

Definition at line 7505 of file regs.h.

#define TIM_CC3S   (0x00000003u)

Definition at line 7505 of file regs.h.

#define TIM_CC3S_BIT   (0)

Definition at line 7507 of file regs.h.

#define TIM_CC3S_BIT   (0)

Definition at line 7507 of file regs.h.

#define TIM_CC3S_BITS   (2)

Definition at line 7508 of file regs.h.

#define TIM_CC3S_BITS   (2)

Definition at line 7508 of file regs.h.

#define TIM_CC3S_MASK   (0x00000003u)

Definition at line 7506 of file regs.h.

#define TIM_CC3S_MASK   (0x00000003u)

Definition at line 7506 of file regs.h.

#define TIM_CC4E   (0x00001000u)

Definition at line 7520 of file regs.h.

#define TIM_CC4E   (0x00001000u)

Definition at line 7520 of file regs.h.

#define TIM_CC4E_BIT   (12)

Definition at line 7522 of file regs.h.

#define TIM_CC4E_BIT   (12)

Definition at line 7522 of file regs.h.

#define TIM_CC4E_BITS   (1)

Definition at line 7523 of file regs.h.

#define TIM_CC4E_BITS   (1)

Definition at line 7523 of file regs.h.

#define TIM_CC4E_MASK   (0x00001000u)

Definition at line 7521 of file regs.h.

#define TIM_CC4E_MASK   (0x00001000u)

Definition at line 7521 of file regs.h.

#define TIM_CC4G   (0x00000010u)

Definition at line 7335 of file regs.h.

#define TIM_CC4G   (0x00000010u)

Definition at line 7335 of file regs.h.

#define TIM_CC4G_BIT   (4)

Definition at line 7337 of file regs.h.

#define TIM_CC4G_BIT   (4)

Definition at line 7337 of file regs.h.

#define TIM_CC4G_BITS   (1)

Definition at line 7338 of file regs.h.

#define TIM_CC4G_BITS   (1)

Definition at line 7338 of file regs.h.

#define TIM_CC4G_MASK   (0x00000010u)

Definition at line 7336 of file regs.h.

#define TIM_CC4G_MASK   (0x00000010u)

Definition at line 7336 of file regs.h.

#define TIM_CC4P   (0x00002000u)

Definition at line 7515 of file regs.h.

#define TIM_CC4P   (0x00002000u)

Definition at line 7515 of file regs.h.

#define TIM_CC4P_BIT   (13)

Definition at line 7517 of file regs.h.

#define TIM_CC4P_BIT   (13)

Definition at line 7517 of file regs.h.

#define TIM_CC4P_BITS   (1)

Definition at line 7518 of file regs.h.

#define TIM_CC4P_BITS   (1)

Definition at line 7518 of file regs.h.

#define TIM_CC4P_MASK   (0x00002000u)

Definition at line 7516 of file regs.h.

#define TIM_CC4P_MASK   (0x00002000u)

Definition at line 7516 of file regs.h.

#define TIM_CC4S   (0x00000300u)

Definition at line 7480 of file regs.h.

#define TIM_CC4S   (0x00000300u)

Definition at line 7480 of file regs.h.

#define TIM_CC4S_BIT   (8)

Definition at line 7482 of file regs.h.

#define TIM_CC4S_BIT   (8)

Definition at line 7482 of file regs.h.

#define TIM_CC4S_BITS   (2)

Definition at line 7483 of file regs.h.

#define TIM_CC4S_BITS   (2)

Definition at line 7483 of file regs.h.

#define TIM_CC4S_MASK   (0x00000300u)

Definition at line 7481 of file regs.h.

#define TIM_CC4S_MASK   (0x00000300u)

Definition at line 7481 of file regs.h.

#define TIM_CCR   (0x0000FFFFu)

Definition at line 7620 of file regs.h.

#define TIM_CCR   (0x0000FFFFu)

Definition at line 7620 of file regs.h.

#define TIM_CCR   (0x0000FFFFu)

Definition at line 7620 of file regs.h.

#define TIM_CCR   (0x0000FFFFu)

Definition at line 7620 of file regs.h.

#define TIM_CCR   (0x0000FFFFu)

Definition at line 7620 of file regs.h.

#define TIM_CCR   (0x0000FFFFu)

Definition at line 7620 of file regs.h.

#define TIM_CCR   (0x0000FFFFu)

Definition at line 7620 of file regs.h.

#define TIM_CCR   (0x0000FFFFu)

Definition at line 7620 of file regs.h.

#define TIM_CCR_BIT   (0)

Definition at line 7622 of file regs.h.

#define TIM_CCR_BIT   (0)

Definition at line 7622 of file regs.h.

#define TIM_CCR_BIT   (0)

Definition at line 7622 of file regs.h.

#define TIM_CCR_BIT   (0)

Definition at line 7622 of file regs.h.

#define TIM_CCR_BIT   (0)

Definition at line 7622 of file regs.h.

#define TIM_CCR_BIT   (0)

Definition at line 7622 of file regs.h.

#define TIM_CCR_BIT   (0)

Definition at line 7622 of file regs.h.

#define TIM_CCR_BIT   (0)

Definition at line 7622 of file regs.h.

#define TIM_CCR_BITS   (16)

Definition at line 7623 of file regs.h.

#define TIM_CCR_BITS   (16)

Definition at line 7623 of file regs.h.

#define TIM_CCR_BITS   (16)

Definition at line 7623 of file regs.h.

#define TIM_CCR_BITS   (16)

Definition at line 7623 of file regs.h.

#define TIM_CCR_BITS   (16)

Definition at line 7623 of file regs.h.

#define TIM_CCR_BITS   (16)

Definition at line 7623 of file regs.h.

#define TIM_CCR_BITS   (16)

Definition at line 7623 of file regs.h.

#define TIM_CCR_BITS   (16)

Definition at line 7623 of file regs.h.

#define TIM_CCR_MASK   (0x0000FFFFu)

Definition at line 7621 of file regs.h.

#define TIM_CCR_MASK   (0x0000FFFFu)

Definition at line 7621 of file regs.h.

#define TIM_CCR_MASK   (0x0000FFFFu)

Definition at line 7621 of file regs.h.

#define TIM_CCR_MASK   (0x0000FFFFu)

Definition at line 7621 of file regs.h.

#define TIM_CCR_MASK   (0x0000FFFFu)

Definition at line 7621 of file regs.h.

#define TIM_CCR_MASK   (0x0000FFFFu)

Definition at line 7621 of file regs.h.

#define TIM_CCR_MASK   (0x0000FFFFu)

Definition at line 7621 of file regs.h.

#define TIM_CCR_MASK   (0x0000FFFFu)

Definition at line 7621 of file regs.h.

#define TIM_CEN   (0x00000001u)

Definition at line 7175 of file regs.h.

#define TIM_CEN   (0x00000001u)

Definition at line 7175 of file regs.h.

#define TIM_CEN_BIT   (0)

Definition at line 7177 of file regs.h.

#define TIM_CEN_BIT   (0)

Definition at line 7177 of file regs.h.

#define TIM_CEN_BITS   (1)

Definition at line 7178 of file regs.h.

#define TIM_CEN_BITS   (1)

Definition at line 7178 of file regs.h.

#define TIM_CEN_MASK   (0x00000001u)

Definition at line 7176 of file regs.h.

#define TIM_CEN_MASK   (0x00000001u)

Definition at line 7176 of file regs.h.

#define TIM_CLKMSKEN   (0x00000004u)

Definition at line 7655 of file regs.h.

#define TIM_CLKMSKEN   (0x00000004u)

Definition at line 7655 of file regs.h.

#define TIM_CLKMSKEN_BIT   (2)

Definition at line 7657 of file regs.h.

#define TIM_CLKMSKEN_BIT   (2)

Definition at line 7657 of file regs.h.

#define TIM_CLKMSKEN_BITS   (1)

Definition at line 7658 of file regs.h.

#define TIM_CLKMSKEN_BITS   (1)

Definition at line 7658 of file regs.h.

#define TIM_CLKMSKEN_MASK   (0x00000004u)

Definition at line 7656 of file regs.h.

#define TIM_CLKMSKEN_MASK   (0x00000004u)

Definition at line 7656 of file regs.h.

#define TIM_CMS   (0x00000060u)

Definition at line 7150 of file regs.h.

#define TIM_CMS   (0x00000060u)

Definition at line 7150 of file regs.h.

#define TIM_CMS_BIT   (5)

Definition at line 7152 of file regs.h.

#define TIM_CMS_BIT   (5)

Definition at line 7152 of file regs.h.

#define TIM_CMS_BITS   (2)

Definition at line 7153 of file regs.h.

#define TIM_CMS_BITS   (2)

Definition at line 7153 of file regs.h.

#define TIM_CMS_MASK   (0x00000060u)

Definition at line 7151 of file regs.h.

#define TIM_CMS_MASK   (0x00000060u)

Definition at line 7151 of file regs.h.

#define TIM_CNT   (0x0000FFFFu)

Definition at line 7560 of file regs.h.

#define TIM_CNT   (0x0000FFFFu)

Definition at line 7560 of file regs.h.

#define TIM_CNT_BIT   (0)

Definition at line 7562 of file regs.h.

#define TIM_CNT_BIT   (0)

Definition at line 7562 of file regs.h.

#define TIM_CNT_BITS   (16)

Definition at line 7563 of file regs.h.

#define TIM_CNT_BITS   (16)

Definition at line 7563 of file regs.h.

#define TIM_CNT_MASK   (0x0000FFFFu)

Definition at line 7561 of file regs.h.

#define TIM_CNT_MASK   (0x0000FFFFu)

Definition at line 7561 of file regs.h.

#define TIM_DIR   (0x00000010u)

Definition at line 7155 of file regs.h.

#define TIM_DIR   (0x00000010u)

Definition at line 7155 of file regs.h.

#define TIM_DIR_BIT   (4)

Definition at line 7157 of file regs.h.

#define TIM_DIR_BIT   (4)

Definition at line 7157 of file regs.h.

#define TIM_DIR_BITS   (1)

Definition at line 7158 of file regs.h.

#define TIM_DIR_BITS   (1)

Definition at line 7158 of file regs.h.

#define TIM_DIR_MASK   (0x00000010u)

Definition at line 7156 of file regs.h.

#define TIM_DIR_MASK   (0x00000010u)

Definition at line 7156 of file regs.h.

#define TIM_ECE   (0x00004000u)

Definition at line 7205 of file regs.h.

#define TIM_ECE   (0x00004000u)

Definition at line 7205 of file regs.h.

#define TIM_ECE_BIT   (14)

Definition at line 7207 of file regs.h.

#define TIM_ECE_BIT   (14)

Definition at line 7207 of file regs.h.

#define TIM_ECE_BITS   (1)

Definition at line 7208 of file regs.h.

#define TIM_ECE_BITS   (1)

Definition at line 7208 of file regs.h.

#define TIM_ECE_MASK   (0x00004000u)

Definition at line 7206 of file regs.h.

#define TIM_ECE_MASK   (0x00004000u)

Definition at line 7206 of file regs.h.

#define TIM_ETF   (0x00000F00u)

Definition at line 7215 of file regs.h.

#define TIM_ETF   (0x00000F00u)

Definition at line 7215 of file regs.h.

#define TIM_ETF_BIT   (8)

Definition at line 7217 of file regs.h.

#define TIM_ETF_BIT   (8)

Definition at line 7217 of file regs.h.

#define TIM_ETF_BITS   (4)

Definition at line 7218 of file regs.h.

#define TIM_ETF_BITS   (4)

Definition at line 7218 of file regs.h.

#define TIM_ETF_MASK   (0x00000F00u)

Definition at line 7216 of file regs.h.

#define TIM_ETF_MASK   (0x00000F00u)

Definition at line 7216 of file regs.h.

#define TIM_ETP   (0x00008000u)

Definition at line 7200 of file regs.h.

#define TIM_ETP   (0x00008000u)

Definition at line 7200 of file regs.h.

#define TIM_ETP_BIT   (15)

Definition at line 7202 of file regs.h.

#define TIM_ETP_BIT   (15)

Definition at line 7202 of file regs.h.

#define TIM_ETP_BITS   (1)

Definition at line 7203 of file regs.h.

#define TIM_ETP_BITS   (1)

Definition at line 7203 of file regs.h.

#define TIM_ETP_MASK   (0x00008000u)

Definition at line 7201 of file regs.h.

#define TIM_ETP_MASK   (0x00008000u)

Definition at line 7201 of file regs.h.

#define TIM_ETPS   (0x00003000u)

Definition at line 7210 of file regs.h.

#define TIM_ETPS   (0x00003000u)

Definition at line 7210 of file regs.h.

#define TIM_ETPS_BIT   (12)

Definition at line 7212 of file regs.h.

#define TIM_ETPS_BIT   (12)

Definition at line 7212 of file regs.h.

#define TIM_ETPS_BITS   (2)

Definition at line 7213 of file regs.h.

#define TIM_ETPS_BITS   (2)

Definition at line 7213 of file regs.h.

#define TIM_ETPS_MASK   (0x00003000u)

Definition at line 7211 of file regs.h.

#define TIM_ETPS_MASK   (0x00003000u)

Definition at line 7211 of file regs.h.

#define TIM_IC1F   (0x000000F0u)

Definition at line 7375 of file regs.h.

#define TIM_IC1F   (0x000000F0u)

Definition at line 7375 of file regs.h.

#define TIM_IC1F_BIT   (4)

Definition at line 7377 of file regs.h.

#define TIM_IC1F_BIT   (4)

Definition at line 7377 of file regs.h.

#define TIM_IC1F_BITS   (4)

Definition at line 7378 of file regs.h.

#define TIM_IC1F_BITS   (4)

Definition at line 7378 of file regs.h.

#define TIM_IC1F_MASK   (0x000000F0u)

Definition at line 7376 of file regs.h.

#define TIM_IC1F_MASK   (0x000000F0u)

Definition at line 7376 of file regs.h.

#define TIM_IC1PSC   (0x0000000Cu)

Definition at line 7380 of file regs.h.

#define TIM_IC1PSC   (0x0000000Cu)

Definition at line 7380 of file regs.h.

#define TIM_IC1PSC_BIT   (2)

Definition at line 7382 of file regs.h.

#define TIM_IC1PSC_BIT   (2)

Definition at line 7382 of file regs.h.

#define TIM_IC1PSC_BITS   (2)

Definition at line 7383 of file regs.h.

#define TIM_IC1PSC_BITS   (2)

Definition at line 7383 of file regs.h.

#define TIM_IC1PSC_MASK   (0x0000000Cu)

Definition at line 7381 of file regs.h.

#define TIM_IC1PSC_MASK   (0x0000000Cu)

Definition at line 7381 of file regs.h.

#define TIM_IC2F   (0x0000F000u)

Definition at line 7365 of file regs.h.

#define TIM_IC2F   (0x0000F000u)

Definition at line 7365 of file regs.h.

#define TIM_IC2F_BIT   (12)

Definition at line 7367 of file regs.h.

#define TIM_IC2F_BIT   (12)

Definition at line 7367 of file regs.h.

#define TIM_IC2F_BITS   (4)

Definition at line 7368 of file regs.h.

#define TIM_IC2F_BITS   (4)

Definition at line 7368 of file regs.h.

#define TIM_IC2F_MASK   (0x0000F000u)

Definition at line 7366 of file regs.h.

#define TIM_IC2F_MASK   (0x0000F000u)

Definition at line 7366 of file regs.h.

#define TIM_IC2PSC   (0x00000C00u)

Definition at line 7370 of file regs.h.

#define TIM_IC2PSC   (0x00000C00u)

Definition at line 7370 of file regs.h.

#define TIM_IC2PSC_BIT   (10)

Definition at line 7372 of file regs.h.

#define TIM_IC2PSC_BIT   (10)

Definition at line 7372 of file regs.h.

#define TIM_IC2PSC_BITS   (2)

Definition at line 7373 of file regs.h.

#define TIM_IC2PSC_BITS   (2)

Definition at line 7373 of file regs.h.

#define TIM_IC2PSC_MASK   (0x00000C00u)

Definition at line 7371 of file regs.h.

#define TIM_IC2PSC_MASK   (0x00000C00u)

Definition at line 7371 of file regs.h.

#define TIM_IC3F   (0x000000F0u)

Definition at line 7450 of file regs.h.

#define TIM_IC3F   (0x000000F0u)

Definition at line 7450 of file regs.h.

#define TIM_IC3F_BIT   (4)

Definition at line 7452 of file regs.h.

#define TIM_IC3F_BIT   (4)

Definition at line 7452 of file regs.h.

#define TIM_IC3F_BITS   (4)

Definition at line 7453 of file regs.h.

#define TIM_IC3F_BITS   (4)

Definition at line 7453 of file regs.h.

#define TIM_IC3F_MASK   (0x000000F0u)

Definition at line 7451 of file regs.h.

#define TIM_IC3F_MASK   (0x000000F0u)

Definition at line 7451 of file regs.h.

#define TIM_IC3PSC   (0x0000000Cu)

Definition at line 7455 of file regs.h.

#define TIM_IC3PSC   (0x0000000Cu)

Definition at line 7455 of file regs.h.

#define TIM_IC3PSC_BIT   (2)

Definition at line 7457 of file regs.h.

#define TIM_IC3PSC_BIT   (2)

Definition at line 7457 of file regs.h.

#define TIM_IC3PSC_BITS   (2)

Definition at line 7458 of file regs.h.

#define TIM_IC3PSC_BITS   (2)

Definition at line 7458 of file regs.h.

#define TIM_IC3PSC_MASK   (0x0000000Cu)

Definition at line 7456 of file regs.h.

#define TIM_IC3PSC_MASK   (0x0000000Cu)

Definition at line 7456 of file regs.h.

#define TIM_IC4F   (0x0000F000u)

Definition at line 7440 of file regs.h.

#define TIM_IC4F   (0x0000F000u)

Definition at line 7440 of file regs.h.

#define TIM_IC4F_BIT   (12)

Definition at line 7442 of file regs.h.

#define TIM_IC4F_BIT   (12)

Definition at line 7442 of file regs.h.

#define TIM_IC4F_BITS   (4)

Definition at line 7443 of file regs.h.

#define TIM_IC4F_BITS   (4)

Definition at line 7443 of file regs.h.

#define TIM_IC4F_MASK   (0x0000F000u)

Definition at line 7441 of file regs.h.

#define TIM_IC4F_MASK   (0x0000F000u)

Definition at line 7441 of file regs.h.

#define TIM_IC4PSC   (0x00000C00u)

Definition at line 7445 of file regs.h.

#define TIM_IC4PSC   (0x00000C00u)

Definition at line 7445 of file regs.h.

#define TIM_IC4PSC_BIT   (10)

Definition at line 7447 of file regs.h.

#define TIM_IC4PSC_BIT   (10)

Definition at line 7447 of file regs.h.

#define TIM_IC4PSC_BITS   (2)

Definition at line 7448 of file regs.h.

#define TIM_IC4PSC_BITS   (2)

Definition at line 7448 of file regs.h.

#define TIM_IC4PSC_MASK   (0x00000C00u)

Definition at line 7446 of file regs.h.

#define TIM_IC4PSC_MASK   (0x00000C00u)

Definition at line 7446 of file regs.h.

#define TIM_MMS   (0x00000070u)

Definition at line 7190 of file regs.h.

#define TIM_MMS   (0x00000070u)

Definition at line 7190 of file regs.h.

#define TIM_MMS_BIT   (4)

Definition at line 7192 of file regs.h.

#define TIM_MMS_BIT   (4)

Definition at line 7192 of file regs.h.

#define TIM_MMS_BITS   (3)

Definition at line 7193 of file regs.h.

#define TIM_MMS_BITS   (3)

Definition at line 7193 of file regs.h.

#define TIM_MMS_MASK   (0x00000070u)

Definition at line 7191 of file regs.h.

#define TIM_MMS_MASK   (0x00000070u)

Definition at line 7191 of file regs.h.

#define TIM_MSM   (0x00000080u)

Definition at line 7220 of file regs.h.

#define TIM_MSM   (0x00000080u)

Definition at line 7220 of file regs.h.

#define TIM_MSM_BIT   (7)

Definition at line 7222 of file regs.h.

#define TIM_MSM_BIT   (7)

Definition at line 7222 of file regs.h.

#define TIM_MSM_BITS   (1)

Definition at line 7223 of file regs.h.

#define TIM_MSM_BITS   (1)

Definition at line 7223 of file regs.h.

#define TIM_MSM_MASK   (0x00000080u)

Definition at line 7221 of file regs.h.

#define TIM_MSM_MASK   (0x00000080u)

Definition at line 7221 of file regs.h.

#define TIM_OC1CE   (0x00000080u)

Definition at line 7410 of file regs.h.

#define TIM_OC1CE   (0x00000080u)

Definition at line 7410 of file regs.h.

#define TIM_OC1CE_BIT   (7)

Definition at line 7412 of file regs.h.

#define TIM_OC1CE_BIT   (7)

Definition at line 7412 of file regs.h.

#define TIM_OC1CE_BITS   (1)

Definition at line 7413 of file regs.h.

#define TIM_OC1CE_BITS   (1)

Definition at line 7413 of file regs.h.

#define TIM_OC1CE_MASK   (0x00000080u)

Definition at line 7411 of file regs.h.

#define TIM_OC1CE_MASK   (0x00000080u)

Definition at line 7411 of file regs.h.

#define TIM_OC1FE   (0x00000004u)

Definition at line 7425 of file regs.h.

#define TIM_OC1FE   (0x00000004u)

Definition at line 7425 of file regs.h.

#define TIM_OC1FE_BIT   (2)

Definition at line 7427 of file regs.h.

#define TIM_OC1FE_BIT   (2)

Definition at line 7427 of file regs.h.

#define TIM_OC1FE_BITS   (1)

Definition at line 7428 of file regs.h.

#define TIM_OC1FE_BITS   (1)

Definition at line 7428 of file regs.h.

#define TIM_OC1FE_MASK   (0x00000004u)

Definition at line 7426 of file regs.h.

#define TIM_OC1FE_MASK   (0x00000004u)

Definition at line 7426 of file regs.h.

#define TIM_OC1M   (0x00000070u)

Definition at line 7415 of file regs.h.

#define TIM_OC1M   (0x00000070u)

Definition at line 7415 of file regs.h.

#define TIM_OC1M_BIT   (4)

Definition at line 7417 of file regs.h.

#define TIM_OC1M_BIT   (4)

Definition at line 7417 of file regs.h.

#define TIM_OC1M_BITS   (3)

Definition at line 7418 of file regs.h.

#define TIM_OC1M_BITS   (3)

Definition at line 7418 of file regs.h.

#define TIM_OC1M_MASK   (0x00000070u)

Definition at line 7416 of file regs.h.

#define TIM_OC1M_MASK   (0x00000070u)

Definition at line 7416 of file regs.h.

#define TIM_OC1PE   (0x00000008u)

Definition at line 7420 of file regs.h.

#define TIM_OC1PE   (0x00000008u)

Definition at line 7420 of file regs.h.

#define TIM_OC1PE_BIT   (3)

Definition at line 7422 of file regs.h.

#define TIM_OC1PE_BIT   (3)

Definition at line 7422 of file regs.h.

#define TIM_OC1PE_BITS   (1)

Definition at line 7423 of file regs.h.

#define TIM_OC1PE_BITS   (1)

Definition at line 7423 of file regs.h.

#define TIM_OC1PE_MASK   (0x00000008u)

Definition at line 7421 of file regs.h.

#define TIM_OC1PE_MASK   (0x00000008u)

Definition at line 7421 of file regs.h.

#define TIM_OC2BE   (0x00000800u)

Definition at line 7395 of file regs.h.

#define TIM_OC2BE   (0x00000800u)

Definition at line 7395 of file regs.h.

#define TIM_OC2BE_BIT   (11)

Definition at line 7397 of file regs.h.

#define TIM_OC2BE_BIT   (11)

Definition at line 7397 of file regs.h.

#define TIM_OC2BE_BITS   (1)

Definition at line 7398 of file regs.h.

#define TIM_OC2BE_BITS   (1)

Definition at line 7398 of file regs.h.

#define TIM_OC2BE_MASK   (0x00000800u)

Definition at line 7396 of file regs.h.

#define TIM_OC2BE_MASK   (0x00000800u)

Definition at line 7396 of file regs.h.

#define TIM_OC2CE   (0x00008000u)

Definition at line 7385 of file regs.h.

#define TIM_OC2CE   (0x00008000u)

Definition at line 7385 of file regs.h.

#define TIM_OC2CE_BIT   (15)

Definition at line 7387 of file regs.h.

#define TIM_OC2CE_BIT   (15)

Definition at line 7387 of file regs.h.

#define TIM_OC2CE_BITS   (1)

Definition at line 7388 of file regs.h.

#define TIM_OC2CE_BITS   (1)

Definition at line 7388 of file regs.h.

#define TIM_OC2CE_MASK   (0x00008000u)

Definition at line 7386 of file regs.h.

#define TIM_OC2CE_MASK   (0x00008000u)

Definition at line 7386 of file regs.h.

#define TIM_OC2FE   (0x00000400u)

Definition at line 7400 of file regs.h.

#define TIM_OC2FE   (0x00000400u)

Definition at line 7400 of file regs.h.

#define TIM_OC2FE_BIT   (10)

Definition at line 7402 of file regs.h.

#define TIM_OC2FE_BIT   (10)

Definition at line 7402 of file regs.h.

#define TIM_OC2FE_BITS   (1)

Definition at line 7403 of file regs.h.

#define TIM_OC2FE_BITS   (1)

Definition at line 7403 of file regs.h.

#define TIM_OC2FE_MASK   (0x00000400u)

Definition at line 7401 of file regs.h.

#define TIM_OC2FE_MASK   (0x00000400u)

Definition at line 7401 of file regs.h.

#define TIM_OC2M   (0x00007000u)

Definition at line 7390 of file regs.h.

#define TIM_OC2M   (0x00007000u)

Definition at line 7390 of file regs.h.

#define TIM_OC2M_BIT   (12)

Definition at line 7392 of file regs.h.

#define TIM_OC2M_BIT   (12)

Definition at line 7392 of file regs.h.

#define TIM_OC2M_BITS   (3)

Definition at line 7393 of file regs.h.

#define TIM_OC2M_BITS   (3)

Definition at line 7393 of file regs.h.

#define TIM_OC2M_MASK   (0x00007000u)

Definition at line 7391 of file regs.h.

#define TIM_OC2M_MASK   (0x00007000u)

Definition at line 7391 of file regs.h.

#define TIM_OC3BE   (0x00000008u)

Definition at line 7495 of file regs.h.

#define TIM_OC3BE   (0x00000008u)

Definition at line 7495 of file regs.h.

#define TIM_OC3BE_BIT   (3)

Definition at line 7497 of file regs.h.

#define TIM_OC3BE_BIT   (3)

Definition at line 7497 of file regs.h.

#define TIM_OC3BE_BITS   (1)

Definition at line 7498 of file regs.h.

#define TIM_OC3BE_BITS   (1)

Definition at line 7498 of file regs.h.

#define TIM_OC3BE_MASK   (0x00000008u)

Definition at line 7496 of file regs.h.

#define TIM_OC3BE_MASK   (0x00000008u)

Definition at line 7496 of file regs.h.

#define TIM_OC3CE   (0x00000080u)

Definition at line 7485 of file regs.h.

#define TIM_OC3CE   (0x00000080u)

Definition at line 7485 of file regs.h.

#define TIM_OC3CE_BIT   (7)

Definition at line 7487 of file regs.h.

#define TIM_OC3CE_BIT   (7)

Definition at line 7487 of file regs.h.

#define TIM_OC3CE_BITS   (1)

Definition at line 7488 of file regs.h.

#define TIM_OC3CE_BITS   (1)

Definition at line 7488 of file regs.h.

#define TIM_OC3CE_MASK   (0x00000080u)

Definition at line 7486 of file regs.h.

#define TIM_OC3CE_MASK   (0x00000080u)

Definition at line 7486 of file regs.h.

#define TIM_OC3FE   (0x00000004u)

Definition at line 7500 of file regs.h.

#define TIM_OC3FE   (0x00000004u)

Definition at line 7500 of file regs.h.

#define TIM_OC3FE_BIT   (2)

Definition at line 7502 of file regs.h.

#define TIM_OC3FE_BIT   (2)

Definition at line 7502 of file regs.h.

#define TIM_OC3FE_BITS   (1)

Definition at line 7503 of file regs.h.

#define TIM_OC3FE_BITS   (1)

Definition at line 7503 of file regs.h.

#define TIM_OC3FE_MASK   (0x00000004u)

Definition at line 7501 of file regs.h.

#define TIM_OC3FE_MASK   (0x00000004u)

Definition at line 7501 of file regs.h.

#define TIM_OC3M   (0x00000070u)

Definition at line 7490 of file regs.h.

#define TIM_OC3M   (0x00000070u)

Definition at line 7490 of file regs.h.

#define TIM_OC3M_BIT   (4)

Definition at line 7492 of file regs.h.

#define TIM_OC3M_BIT   (4)

Definition at line 7492 of file regs.h.

#define TIM_OC3M_BITS   (3)

Definition at line 7493 of file regs.h.

#define TIM_OC3M_BITS   (3)

Definition at line 7493 of file regs.h.

#define TIM_OC3M_MASK   (0x00000070u)

Definition at line 7491 of file regs.h.

#define TIM_OC3M_MASK   (0x00000070u)

Definition at line 7491 of file regs.h.

#define TIM_OC4BE   (0x00000800u)

Definition at line 7470 of file regs.h.

#define TIM_OC4BE   (0x00000800u)

Definition at line 7470 of file regs.h.

#define TIM_OC4BE_BIT   (11)

Definition at line 7472 of file regs.h.

#define TIM_OC4BE_BIT   (11)

Definition at line 7472 of file regs.h.

#define TIM_OC4BE_BITS   (1)

Definition at line 7473 of file regs.h.

#define TIM_OC4BE_BITS   (1)

Definition at line 7473 of file regs.h.

#define TIM_OC4BE_MASK   (0x00000800u)

Definition at line 7471 of file regs.h.

#define TIM_OC4BE_MASK   (0x00000800u)

Definition at line 7471 of file regs.h.

#define TIM_OC4CE   (0x00008000u)

Definition at line 7460 of file regs.h.

#define TIM_OC4CE   (0x00008000u)

Definition at line 7460 of file regs.h.

#define TIM_OC4CE_BIT   (15)

Definition at line 7462 of file regs.h.

#define TIM_OC4CE_BIT   (15)

Definition at line 7462 of file regs.h.

#define TIM_OC4CE_BITS   (1)

Definition at line 7463 of file regs.h.

#define TIM_OC4CE_BITS   (1)

Definition at line 7463 of file regs.h.

#define TIM_OC4CE_MASK   (0x00008000u)

Definition at line 7461 of file regs.h.

#define TIM_OC4CE_MASK   (0x00008000u)

Definition at line 7461 of file regs.h.

#define TIM_OC4FE   (0x00000400u)

Definition at line 7475 of file regs.h.

#define TIM_OC4FE   (0x00000400u)

Definition at line 7475 of file regs.h.

#define TIM_OC4FE_BIT   (10)

Definition at line 7477 of file regs.h.

#define TIM_OC4FE_BIT   (10)

Definition at line 7477 of file regs.h.

#define TIM_OC4FE_BITS   (1)

Definition at line 7478 of file regs.h.

#define TIM_OC4FE_BITS   (1)

Definition at line 7478 of file regs.h.

#define TIM_OC4FE_MASK   (0x00000400u)

Definition at line 7476 of file regs.h.

#define TIM_OC4FE_MASK   (0x00000400u)

Definition at line 7476 of file regs.h.

#define TIM_OC4M   (0x00007000u)

Definition at line 7465 of file regs.h.

#define TIM_OC4M   (0x00007000u)

Definition at line 7465 of file regs.h.

#define TIM_OC4M_BIT   (12)

Definition at line 7467 of file regs.h.

#define TIM_OC4M_BIT   (12)

Definition at line 7467 of file regs.h.

#define TIM_OC4M_BITS   (3)

Definition at line 7468 of file regs.h.

#define TIM_OC4M_BITS   (3)

Definition at line 7468 of file regs.h.

#define TIM_OC4M_MASK   (0x00007000u)

Definition at line 7466 of file regs.h.

#define TIM_OC4M_MASK   (0x00007000u)

Definition at line 7466 of file regs.h.

#define TIM_OPM   (0x00000008u)

Definition at line 7160 of file regs.h.

#define TIM_OPM   (0x00000008u)

Definition at line 7160 of file regs.h.

#define TIM_OPM_BIT   (3)

Definition at line 7162 of file regs.h.

#define TIM_OPM_BIT   (3)

Definition at line 7162 of file regs.h.

#define TIM_OPM_BITS   (1)

Definition at line 7163 of file regs.h.

#define TIM_OPM_BITS   (1)

Definition at line 7163 of file regs.h.

#define TIM_OPM_MASK   (0x00000008u)

Definition at line 7161 of file regs.h.

#define TIM_OPM_MASK   (0x00000008u)

Definition at line 7161 of file regs.h.

#define TIM_ORRSVD   (0x00000008u)

Definition at line 7650 of file regs.h.

#define TIM_ORRSVD   (0x00000008u)

Definition at line 7650 of file regs.h.

#define TIM_ORRSVD_BIT   (3)

Definition at line 7652 of file regs.h.

#define TIM_ORRSVD_BIT   (3)

Definition at line 7652 of file regs.h.

#define TIM_ORRSVD_BITS   (1)

Definition at line 7653 of file regs.h.

#define TIM_ORRSVD_BITS   (1)

Definition at line 7653 of file regs.h.

#define TIM_ORRSVD_MASK   (0x00000008u)

Definition at line 7651 of file regs.h.

#define TIM_ORRSVD_MASK   (0x00000008u)

Definition at line 7651 of file regs.h.

#define TIM_PSC   (0x0000000Fu)

Definition at line 7570 of file regs.h.

#define TIM_PSC   (0x0000000Fu)

Definition at line 7570 of file regs.h.

#define TIM_PSC_BIT   (0)

Definition at line 7572 of file regs.h.

#define TIM_PSC_BIT   (0)

Definition at line 7572 of file regs.h.

#define TIM_PSC_BITS   (4)

Definition at line 7573 of file regs.h.

#define TIM_PSC_BITS   (4)

Definition at line 7573 of file regs.h.

#define TIM_PSC_MASK   (0x0000000Fu)

Definition at line 7571 of file regs.h.

#define TIM_PSC_MASK   (0x0000000Fu)

Definition at line 7571 of file regs.h.

#define TIM_REMAPC1   (0x00000010u)

Definition at line 7645 of file regs.h.

#define TIM_REMAPC1_BIT   (4)

Definition at line 7647 of file regs.h.

#define TIM_REMAPC1_BITS   (1)

Definition at line 7648 of file regs.h.

#define TIM_REMAPC1_MASK   (0x00000010u)

Definition at line 7646 of file regs.h.

#define TIM_REMAPC2   (0x00000020u)

Definition at line 7640 of file regs.h.

#define TIM_REMAPC2_BIT   (5)

Definition at line 7642 of file regs.h.

#define TIM_REMAPC2_BITS   (1)

Definition at line 7643 of file regs.h.

#define TIM_REMAPC2_MASK   (0x00000020u)

Definition at line 7641 of file regs.h.

#define TIM_REMAPC3   (0x00000040u)

Definition at line 7635 of file regs.h.

#define TIM_REMAPC3_BIT   (6)

Definition at line 7637 of file regs.h.

#define TIM_REMAPC3_BITS   (1)

Definition at line 7638 of file regs.h.

#define TIM_REMAPC3_MASK   (0x00000040u)

Definition at line 7636 of file regs.h.

#define TIM_REMAPC4   (0x00000080u)

Definition at line 7630 of file regs.h.

#define TIM_REMAPC4_BIT   (7)

Definition at line 7632 of file regs.h.

#define TIM_REMAPC4_BITS   (1)

Definition at line 7633 of file regs.h.

#define TIM_REMAPC4_MASK   (0x00000080u)

Definition at line 7631 of file regs.h.

#define TIM_SMS   (0x00000007u)

Definition at line 7230 of file regs.h.

#define TIM_SMS   (0x00000007u)

Definition at line 7230 of file regs.h.

#define TIM_SMS_BIT   (0)

Definition at line 7232 of file regs.h.

#define TIM_SMS_BIT   (0)

Definition at line 7232 of file regs.h.

#define TIM_SMS_BITS   (3)

Definition at line 7233 of file regs.h.

#define TIM_SMS_BITS   (3)

Definition at line 7233 of file regs.h.

#define TIM_SMS_MASK   (0x00000007u)

Definition at line 7231 of file regs.h.

#define TIM_SMS_MASK   (0x00000007u)

Definition at line 7231 of file regs.h.

#define TIM_TG   (0x00000040u)

Definition at line 7330 of file regs.h.

#define TIM_TG   (0x00000040u)

Definition at line 7330 of file regs.h.

#define TIM_TG_BIT   (6)

Definition at line 7332 of file regs.h.

#define TIM_TG_BIT   (6)

Definition at line 7332 of file regs.h.

#define TIM_TG_BITS   (1)

Definition at line 7333 of file regs.h.

#define TIM_TG_BITS   (1)

Definition at line 7333 of file regs.h.

#define TIM_TG_MASK   (0x00000040u)

Definition at line 7331 of file regs.h.

#define TIM_TG_MASK   (0x00000040u)

Definition at line 7331 of file regs.h.

#define TIM_TI1S   (0x00000080u)

Definition at line 7185 of file regs.h.

#define TIM_TI1S   (0x00000080u)

Definition at line 7185 of file regs.h.

#define TIM_TI1S_BIT   (7)

Definition at line 7187 of file regs.h.

#define TIM_TI1S_BIT   (7)

Definition at line 7187 of file regs.h.

#define TIM_TI1S_BITS   (1)

Definition at line 7188 of file regs.h.

#define TIM_TI1S_BITS   (1)

Definition at line 7188 of file regs.h.

#define TIM_TI1S_MASK   (0x00000080u)

Definition at line 7186 of file regs.h.

#define TIM_TI1S_MASK   (0x00000080u)

Definition at line 7186 of file regs.h.

#define TIM_TS   (0x00000070u)

Definition at line 7225 of file regs.h.

#define TIM_TS   (0x00000070u)

Definition at line 7225 of file regs.h.

#define TIM_TS_BIT   (4)

Definition at line 7227 of file regs.h.

#define TIM_TS_BIT   (4)

Definition at line 7227 of file regs.h.

#define TIM_TS_BITS   (3)

Definition at line 7228 of file regs.h.

#define TIM_TS_BITS   (3)

Definition at line 7228 of file regs.h.

#define TIM_TS_MASK   (0x00000070u)

Definition at line 7226 of file regs.h.

#define TIM_TS_MASK   (0x00000070u)

Definition at line 7226 of file regs.h.

#define TIM_UDIS   (0x00000002u)

Definition at line 7170 of file regs.h.

#define TIM_UDIS   (0x00000002u)

Definition at line 7170 of file regs.h.

#define TIM_UDIS_BIT   (1)

Definition at line 7172 of file regs.h.

#define TIM_UDIS_BIT   (1)

Definition at line 7172 of file regs.h.

#define TIM_UDIS_BITS   (1)

Definition at line 7173 of file regs.h.

#define TIM_UDIS_BITS   (1)

Definition at line 7173 of file regs.h.

#define TIM_UDIS_MASK   (0x00000002u)

Definition at line 7171 of file regs.h.

#define TIM_UDIS_MASK   (0x00000002u)

Definition at line 7171 of file regs.h.

#define TIM_UG   (0x00000001u)

Definition at line 7355 of file regs.h.

#define TIM_UG   (0x00000001u)

Definition at line 7355 of file regs.h.

#define TIM_UG_BIT   (0)

Definition at line 7357 of file regs.h.

#define TIM_UG_BIT   (0)

Definition at line 7357 of file regs.h.

#define TIM_UG_BITS   (1)

Definition at line 7358 of file regs.h.

#define TIM_UG_BITS   (1)

Definition at line 7358 of file regs.h.

#define TIM_UG_MASK   (0x00000001u)

Definition at line 7356 of file regs.h.

#define TIM_UG_MASK   (0x00000001u)

Definition at line 7356 of file regs.h.

#define TIM_URS   (0x00000004u)

Definition at line 7165 of file regs.h.

#define TIM_URS   (0x00000004u)

Definition at line 7165 of file regs.h.

#define TIM_URS_BIT   (2)

Definition at line 7167 of file regs.h.

#define TIM_URS_BIT   (2)

Definition at line 7167 of file regs.h.

#define TIM_URS_BITS   (1)

Definition at line 7168 of file regs.h.

#define TIM_URS_BITS   (1)

Definition at line 7168 of file regs.h.

#define TIM_URS_MASK   (0x00000004u)

Definition at line 7166 of file regs.h.

#define TIM_URS_MASK   (0x00000004u)

Definition at line 7166 of file regs.h.

#define TMR1_DIER   *((volatile int32u *)0x4000E00Cu)

Definition at line 6725 of file regs.h.

#define TMR1_DIER_ADDR   (0x4000E00Cu)

Definition at line 6727 of file regs.h.

#define TMR1_DIER_CC1IE   (0x00000002u)

Definition at line 6750 of file regs.h.

#define TMR1_DIER_CC1IE_BIT   (1)

Definition at line 6752 of file regs.h.

#define TMR1_DIER_CC1IE_BITS   (1)

Definition at line 6753 of file regs.h.

#define TMR1_DIER_CC1IE_MASK   (0x00000002u)

Definition at line 6751 of file regs.h.

#define TMR1_DIER_CC2IE   (0x00000004u)

Definition at line 6745 of file regs.h.

#define TMR1_DIER_CC2IE_BIT   (2)

Definition at line 6747 of file regs.h.

#define TMR1_DIER_CC2IE_BITS   (1)

Definition at line 6748 of file regs.h.

#define TMR1_DIER_CC2IE_MASK   (0x00000004u)

Definition at line 6746 of file regs.h.

#define TMR1_DIER_CC3IE   (0x00000008u)

Definition at line 6740 of file regs.h.

#define TMR1_DIER_CC3IE_BIT   (3)

Definition at line 6742 of file regs.h.

#define TMR1_DIER_CC3IE_BITS   (1)

Definition at line 6743 of file regs.h.

#define TMR1_DIER_CC3IE_MASK   (0x00000008u)

Definition at line 6741 of file regs.h.

#define TMR1_DIER_CC4IE   (0x00000010u)

Definition at line 6735 of file regs.h.

#define TMR1_DIER_CC4IE_BIT   (4)

Definition at line 6737 of file regs.h.

#define TMR1_DIER_CC4IE_BITS   (1)

Definition at line 6738 of file regs.h.

#define TMR1_DIER_CC4IE_MASK   (0x00000010u)

Definition at line 6736 of file regs.h.

#define TMR1_DIER_REG   *((volatile int32u *)0x4000E00Cu)

Definition at line 6726 of file regs.h.

#define TMR1_DIER_RESET   (0x00000000u)

Definition at line 6728 of file regs.h.

#define TMR1_DIER_TIE   (0x00000040u)

Definition at line 6730 of file regs.h.

#define TMR1_DIER_TIE_BIT   (6)

Definition at line 6732 of file regs.h.

#define TMR1_DIER_TIE_BITS   (1)

Definition at line 6733 of file regs.h.

#define TMR1_DIER_TIE_MASK   (0x00000040u)

Definition at line 6731 of file regs.h.

#define TMR1_DIER_UIE   (0x00000001u)

Definition at line 6755 of file regs.h.

#define TMR1_DIER_UIE_BIT   (0)

Definition at line 6757 of file regs.h.

#define TMR1_DIER_UIE_BITS   (1)

Definition at line 6758 of file regs.h.

#define TMR1_DIER_UIE_MASK   (0x00000001u)

Definition at line 6756 of file regs.h.

#define TMR1_SR   *((volatile int32u *)0x4000E010u)

Definition at line 6760 of file regs.h.

#define TMR1_SR_ADDR   (0x4000E010u)

Definition at line 6762 of file regs.h.

#define TMR1_SR_CC1IF   (0x00000002u)

Definition at line 6805 of file regs.h.

#define TMR1_SR_CC1IF_BIT   (1)

Definition at line 6807 of file regs.h.

#define TMR1_SR_CC1IF_BITS   (1)

Definition at line 6808 of file regs.h.

#define TMR1_SR_CC1IF_MASK   (0x00000002u)

Definition at line 6806 of file regs.h.

#define TMR1_SR_CC1OF   (0x00000200u)

Definition at line 6780 of file regs.h.

#define TMR1_SR_CC1OF_BIT   (9)

Definition at line 6782 of file regs.h.

#define TMR1_SR_CC1OF_BITS   (1)

Definition at line 6783 of file regs.h.

#define TMR1_SR_CC1OF_MASK   (0x00000200u)

Definition at line 6781 of file regs.h.

#define TMR1_SR_CC2IF   (0x00000004u)

Definition at line 6800 of file regs.h.

#define TMR1_SR_CC2IF_BIT   (2)

Definition at line 6802 of file regs.h.

#define TMR1_SR_CC2IF_BITS   (1)

Definition at line 6803 of file regs.h.

#define TMR1_SR_CC2IF_MASK   (0x00000004u)

Definition at line 6801 of file regs.h.

#define TMR1_SR_CC2OF   (0x00000400u)

Definition at line 6775 of file regs.h.

#define TMR1_SR_CC2OF_BIT   (10)

Definition at line 6777 of file regs.h.

#define TMR1_SR_CC2OF_BITS   (1)

Definition at line 6778 of file regs.h.

#define TMR1_SR_CC2OF_MASK   (0x00000400u)

Definition at line 6776 of file regs.h.

#define TMR1_SR_CC3IF   (0x00000008u)

Definition at line 6795 of file regs.h.

#define TMR1_SR_CC3IF_BIT   (3)

Definition at line 6797 of file regs.h.

#define TMR1_SR_CC3IF_BITS   (1)

Definition at line 6798 of file regs.h.

#define TMR1_SR_CC3IF_MASK   (0x00000008u)

Definition at line 6796 of file regs.h.

#define TMR1_SR_CC3OF   (0x00000800u)

Definition at line 6770 of file regs.h.

#define TMR1_SR_CC3OF_BIT   (11)

Definition at line 6772 of file regs.h.

#define TMR1_SR_CC3OF_BITS   (1)

Definition at line 6773 of file regs.h.

#define TMR1_SR_CC3OF_MASK   (0x00000800u)

Definition at line 6771 of file regs.h.

#define TMR1_SR_CC4IF   (0x00000010u)

Definition at line 6790 of file regs.h.

#define TMR1_SR_CC4IF_BIT   (4)

Definition at line 6792 of file regs.h.

#define TMR1_SR_CC4IF_BITS   (1)

Definition at line 6793 of file regs.h.

#define TMR1_SR_CC4IF_MASK   (0x00000010u)

Definition at line 6791 of file regs.h.

#define TMR1_SR_CC4OF   (0x00001000u)

Definition at line 6765 of file regs.h.

#define TMR1_SR_CC4OF_BIT   (12)

Definition at line 6767 of file regs.h.

#define TMR1_SR_CC4OF_BITS   (1)

Definition at line 6768 of file regs.h.

#define TMR1_SR_CC4OF_MASK   (0x00001000u)

Definition at line 6766 of file regs.h.

#define TMR1_SR_REG   *((volatile int32u *)0x4000E010u)

Definition at line 6761 of file regs.h.

#define TMR1_SR_RESET   (0x00000000u)

Definition at line 6763 of file regs.h.

#define TMR1_SR_TIF   (0x00000040u)

Definition at line 6785 of file regs.h.

#define TMR1_SR_TIF_BIT   (6)

Definition at line 6787 of file regs.h.

#define TMR1_SR_TIF_BITS   (1)

Definition at line 6788 of file regs.h.

#define TMR1_SR_TIF_MASK   (0x00000040u)

Definition at line 6786 of file regs.h.

#define TMR1_SR_UIF   (0x00000001u)

Definition at line 6810 of file regs.h.

#define TMR1_SR_UIF_BIT   (0)

Definition at line 6812 of file regs.h.

#define TMR1_SR_UIF_BITS   (1)

Definition at line 6813 of file regs.h.

#define TMR1_SR_UIF_MASK   (0x00000001u)

Definition at line 6811 of file regs.h.

#define TMR2_DIER   *((volatile int32u *)0x4000F00Cu)

Definition at line 7235 of file regs.h.

#define TMR2_DIER_ADDR   (0x4000F00Cu)

Definition at line 7237 of file regs.h.

#define TMR2_DIER_CC1IE   (0x00000002u)

Definition at line 7260 of file regs.h.

#define TMR2_DIER_CC1IE_BIT   (1)

Definition at line 7262 of file regs.h.

#define TMR2_DIER_CC1IE_BITS   (1)

Definition at line 7263 of file regs.h.

#define TMR2_DIER_CC1IE_MASK   (0x00000002u)

Definition at line 7261 of file regs.h.

#define TMR2_DIER_CC2IE   (0x00000004u)

Definition at line 7255 of file regs.h.

#define TMR2_DIER_CC2IE_BIT   (2)

Definition at line 7257 of file regs.h.

#define TMR2_DIER_CC2IE_BITS   (1)

Definition at line 7258 of file regs.h.

#define TMR2_DIER_CC2IE_MASK   (0x00000004u)

Definition at line 7256 of file regs.h.

#define TMR2_DIER_CC3IE   (0x00000008u)

Definition at line 7250 of file regs.h.

#define TMR2_DIER_CC3IE_BIT   (3)

Definition at line 7252 of file regs.h.

#define TMR2_DIER_CC3IE_BITS   (1)

Definition at line 7253 of file regs.h.

#define TMR2_DIER_CC3IE_MASK   (0x00000008u)

Definition at line 7251 of file regs.h.

#define TMR2_DIER_CC4IE   (0x00000010u)

Definition at line 7245 of file regs.h.

#define TMR2_DIER_CC4IE_BIT   (4)

Definition at line 7247 of file regs.h.

#define TMR2_DIER_CC4IE_BITS   (1)

Definition at line 7248 of file regs.h.

#define TMR2_DIER_CC4IE_MASK   (0x00000010u)

Definition at line 7246 of file regs.h.

#define TMR2_DIER_REG   *((volatile int32u *)0x4000F00Cu)

Definition at line 7236 of file regs.h.

#define TMR2_DIER_RESET   (0x00000000u)

Definition at line 7238 of file regs.h.

#define TMR2_DIER_TIE   (0x00000040u)

Definition at line 7240 of file regs.h.

#define TMR2_DIER_TIE_BIT   (6)

Definition at line 7242 of file regs.h.

#define TMR2_DIER_TIE_BITS   (1)

Definition at line 7243 of file regs.h.

#define TMR2_DIER_TIE_MASK   (0x00000040u)

Definition at line 7241 of file regs.h.

#define TMR2_DIER_UIE   (0x00000001u)

Definition at line 7265 of file regs.h.

#define TMR2_DIER_UIE_BIT   (0)

Definition at line 7267 of file regs.h.

#define TMR2_DIER_UIE_BITS   (1)

Definition at line 7268 of file regs.h.

#define TMR2_DIER_UIE_MASK   (0x00000001u)

Definition at line 7266 of file regs.h.

#define TMR2_SR   *((volatile int32u *)0x4000F010u)

Definition at line 7270 of file regs.h.

#define TMR2_SR_ADDR   (0x4000F010u)

Definition at line 7272 of file regs.h.

#define TMR2_SR_CC1IF   (0x00000002u)

Definition at line 7315 of file regs.h.

#define TMR2_SR_CC1IF_BIT   (1)

Definition at line 7317 of file regs.h.

#define TMR2_SR_CC1IF_BITS   (1)

Definition at line 7318 of file regs.h.

#define TMR2_SR_CC1IF_MASK   (0x00000002u)

Definition at line 7316 of file regs.h.

#define TMR2_SR_CC1OF   (0x00000200u)

Definition at line 7290 of file regs.h.

#define TMR2_SR_CC1OF_BIT   (9)

Definition at line 7292 of file regs.h.

#define TMR2_SR_CC1OF_BITS   (1)

Definition at line 7293 of file regs.h.

#define TMR2_SR_CC1OF_MASK   (0x00000200u)

Definition at line 7291 of file regs.h.

#define TMR2_SR_CC2IF   (0x00000004u)

Definition at line 7310 of file regs.h.

#define TMR2_SR_CC2IF_BIT   (2)

Definition at line 7312 of file regs.h.

#define TMR2_SR_CC2IF_BITS   (1)

Definition at line 7313 of file regs.h.

#define TMR2_SR_CC2IF_MASK   (0x00000004u)

Definition at line 7311 of file regs.h.

#define TMR2_SR_CC2OF   (0x00000400u)

Definition at line 7285 of file regs.h.

#define TMR2_SR_CC2OF_BIT   (10)

Definition at line 7287 of file regs.h.

#define TMR2_SR_CC2OF_BITS   (1)

Definition at line 7288 of file regs.h.

#define TMR2_SR_CC2OF_MASK   (0x00000400u)

Definition at line 7286 of file regs.h.

#define TMR2_SR_CC3IF   (0x00000008u)

Definition at line 7305 of file regs.h.

#define TMR2_SR_CC3IF_BIT   (3)

Definition at line 7307 of file regs.h.

#define TMR2_SR_CC3IF_BITS   (1)

Definition at line 7308 of file regs.h.

#define TMR2_SR_CC3IF_MASK   (0x00000008u)

Definition at line 7306 of file regs.h.

#define TMR2_SR_CC3OF   (0x00000800u)

Definition at line 7280 of file regs.h.

#define TMR2_SR_CC3OF_BIT   (11)

Definition at line 7282 of file regs.h.

#define TMR2_SR_CC3OF_BITS   (1)

Definition at line 7283 of file regs.h.

#define TMR2_SR_CC3OF_MASK   (0x00000800u)

Definition at line 7281 of file regs.h.

#define TMR2_SR_CC4IF   (0x00000010u)

Definition at line 7300 of file regs.h.

#define TMR2_SR_CC4IF_BIT   (4)

Definition at line 7302 of file regs.h.

#define TMR2_SR_CC4IF_BITS   (1)

Definition at line 7303 of file regs.h.

#define TMR2_SR_CC4IF_MASK   (0x00000010u)

Definition at line 7301 of file regs.h.

#define TMR2_SR_CC4OF   (0x00001000u)

Definition at line 7275 of file regs.h.

#define TMR2_SR_CC4OF_BIT   (12)

Definition at line 7277 of file regs.h.

#define TMR2_SR_CC4OF_BITS   (1)

Definition at line 7278 of file regs.h.

#define TMR2_SR_CC4OF_MASK   (0x00001000u)

Definition at line 7276 of file regs.h.

#define TMR2_SR_REG   *((volatile int32u *)0x4000F010u)

Definition at line 7271 of file regs.h.

#define TMR2_SR_RESET   (0x00000000u)

Definition at line 7273 of file regs.h.

#define TMR2_SR_TIF   (0x00000040u)

Definition at line 7295 of file regs.h.

#define TMR2_SR_TIF_BIT   (6)

Definition at line 7297 of file regs.h.

#define TMR2_SR_TIF_BITS   (1)

Definition at line 7298 of file regs.h.

#define TMR2_SR_TIF_MASK   (0x00000040u)

Definition at line 7296 of file regs.h.

#define TMR2_SR_UIF   (0x00000001u)

Definition at line 7320 of file regs.h.

#define TMR2_SR_UIF_BIT   (0)

Definition at line 7322 of file regs.h.

#define TMR2_SR_UIF_BITS   (1)

Definition at line 7323 of file regs.h.

#define TMR2_SR_UIF_MASK   (0x00000001u)

Definition at line 7321 of file regs.h.

#define TPIU_COSD   *((volatile int32u *)0xE0040010u)

Definition at line 11175 of file regs.h.

#define TPIU_COSD_ADDR   (0xE0040010u)

Definition at line 11177 of file regs.h.

#define TPIU_COSD_PRESCALER   (0x00001FFFu)

Definition at line 11180 of file regs.h.

#define TPIU_COSD_PRESCALER_BIT   (0)

Definition at line 11182 of file regs.h.

#define TPIU_COSD_PRESCALER_BITS   (13)

Definition at line 11183 of file regs.h.

#define TPIU_COSD_PRESCALER_MASK   (0x00001FFFu)

Definition at line 11181 of file regs.h.

#define TPIU_COSD_REG   *((volatile int32u *)0xE0040010u)

Definition at line 11176 of file regs.h.

#define TPIU_COSD_RESET   (0x00000000u)

Definition at line 11178 of file regs.h.

#define TPIU_CPS   *((volatile int32u *)0xE0040004u)

Definition at line 11150 of file regs.h.

#define TPIU_CPS_ADDR   (0xE0040004u)

Definition at line 11152 of file regs.h.

#define TPIU_CPS_CPS_01   (0x00000001u)

Definition at line 11170 of file regs.h.

#define TPIU_CPS_CPS_01_BIT   (0)

Definition at line 11172 of file regs.h.

#define TPIU_CPS_CPS_01_BITS   (1)

Definition at line 11173 of file regs.h.

#define TPIU_CPS_CPS_01_MASK   (0x00000001u)

Definition at line 11171 of file regs.h.

#define TPIU_CPS_CPS_02   (0x00000002u)

Definition at line 11165 of file regs.h.

#define TPIU_CPS_CPS_02_BIT   (1)

Definition at line 11167 of file regs.h.

#define TPIU_CPS_CPS_02_BITS   (1)

Definition at line 11168 of file regs.h.

#define TPIU_CPS_CPS_02_MASK   (0x00000002u)

Definition at line 11166 of file regs.h.

#define TPIU_CPS_CPS_03   (0x00000004u)

Definition at line 11160 of file regs.h.

#define TPIU_CPS_CPS_03_BIT   (2)

Definition at line 11162 of file regs.h.

#define TPIU_CPS_CPS_03_BITS   (1)

Definition at line 11163 of file regs.h.

#define TPIU_CPS_CPS_03_MASK   (0x00000004u)

Definition at line 11161 of file regs.h.

#define TPIU_CPS_CPS_04   (0x00000008u)

Definition at line 11155 of file regs.h.

#define TPIU_CPS_CPS_04_BIT   (3)

Definition at line 11157 of file regs.h.

#define TPIU_CPS_CPS_04_BITS   (1)

Definition at line 11158 of file regs.h.

#define TPIU_CPS_CPS_04_MASK   (0x00000008u)

Definition at line 11156 of file regs.h.

#define TPIU_CPS_REG   *((volatile int32u *)0xE0040004u)

Definition at line 11151 of file regs.h.

#define TPIU_CPS_RESET   (0x00000001u)

Definition at line 11153 of file regs.h.

#define TPIU_FFC   *((volatile int32u *)0xE0040304u)

Definition at line 11220 of file regs.h.

#define TPIU_FFC_ADDR   (0xE0040304u)

Definition at line 11222 of file regs.h.

#define TPIU_FFC_ENFCONT   (0x00000002u)

Definition at line 11230 of file regs.h.

#define TPIU_FFC_ENFCONT_BIT   (1)

Definition at line 11232 of file regs.h.

#define TPIU_FFC_ENFCONT_BITS   (1)

Definition at line 11233 of file regs.h.

#define TPIU_FFC_ENFCONT_MASK   (0x00000002u)

Definition at line 11231 of file regs.h.

#define TPIU_FFC_REG   *((volatile int32u *)0xE0040304u)

Definition at line 11221 of file regs.h.

#define TPIU_FFC_RESET   (0x00000102u)

Definition at line 11223 of file regs.h.

#define TPIU_FFC_TRIGIN   (0x00000100u)

Definition at line 11225 of file regs.h.

#define TPIU_FFC_TRIGIN_BIT   (8)

Definition at line 11227 of file regs.h.

#define TPIU_FFC_TRIGIN_BITS   (1)

Definition at line 11228 of file regs.h.

#define TPIU_FFC_TRIGIN_MASK   (0x00000100u)

Definition at line 11226 of file regs.h.

#define TPIU_FFS   *((volatile int32u *)0xE0040300u)

Definition at line 11195 of file regs.h.

#define TPIU_FFS_ADDR   (0xE0040300u)

Definition at line 11197 of file regs.h.

#define TPIU_FFS_FLINPROG   (0x00000001u)

Definition at line 11215 of file regs.h.

#define TPIU_FFS_FLINPROG_BIT   (0)

Definition at line 11217 of file regs.h.

#define TPIU_FFS_FLINPROG_BITS   (1)

Definition at line 11218 of file regs.h.

#define TPIU_FFS_FLINPROG_MASK   (0x00000001u)

Definition at line 11216 of file regs.h.

#define TPIU_FFS_FTNONSTOP   (0x00000008u)

Definition at line 11200 of file regs.h.

#define TPIU_FFS_FTNONSTOP_BIT   (3)

Definition at line 11202 of file regs.h.

#define TPIU_FFS_FTNONSTOP_BITS   (1)

Definition at line 11203 of file regs.h.

#define TPIU_FFS_FTNONSTOP_MASK   (0x00000008u)

Definition at line 11201 of file regs.h.

#define TPIU_FFS_FTSTOPPED   (0x00000002u)

Definition at line 11210 of file regs.h.

#define TPIU_FFS_FTSTOPPED_BIT   (1)

Definition at line 11212 of file regs.h.

#define TPIU_FFS_FTSTOPPED_BITS   (1)

Definition at line 11213 of file regs.h.

#define TPIU_FFS_FTSTOPPED_MASK   (0x00000002u)

Definition at line 11211 of file regs.h.

#define TPIU_FFS_REG   *((volatile int32u *)0xE0040300u)

Definition at line 11196 of file regs.h.

#define TPIU_FFS_RESET   (0x00000008u)

Definition at line 11198 of file regs.h.

#define TPIU_FFS_TCPRESENT   (0x00000004u)

Definition at line 11205 of file regs.h.

#define TPIU_FFS_TCPRESENT_BIT   (2)

Definition at line 11207 of file regs.h.

#define TPIU_FFS_TCPRESENT_BITS   (1)

Definition at line 11208 of file regs.h.

#define TPIU_FFS_TCPRESENT_MASK   (0x00000004u)

Definition at line 11206 of file regs.h.

#define TPIU_FSC   *((volatile int32u *)0xE0040308u)

Definition at line 11235 of file regs.h.

#define TPIU_FSC_ADDR   (0xE0040308u)

Definition at line 11237 of file regs.h.

#define TPIU_FSC_FSC   (0xFFFFFFFFu)

Definition at line 11240 of file regs.h.

#define TPIU_FSC_FSC_BIT   (0)

Definition at line 11242 of file regs.h.

#define TPIU_FSC_FSC_BITS   (32)

Definition at line 11243 of file regs.h.

#define TPIU_FSC_FSC_MASK   (0xFFFFFFFFu)

Definition at line 11241 of file regs.h.

#define TPIU_FSC_REG   *((volatile int32u *)0xE0040308u)

Definition at line 11236 of file regs.h.

#define TPIU_FSC_RESET   (0x00000000u)

Definition at line 11238 of file regs.h.

#define TPIU_ITATBCTR0   *((volatile int32u *)0xE0040EF8u)

Definition at line 11255 of file regs.h.

#define TPIU_ITATBCTR0_ADDR   (0xE0040EF8u)

Definition at line 11257 of file regs.h.

#define TPIU_ITATBCTR0_ATREADY1   (0x00000001u)

Definition at line 11260 of file regs.h.

#define TPIU_ITATBCTR0_ATREADY1_BIT   (0)

Definition at line 11262 of file regs.h.

#define TPIU_ITATBCTR0_ATREADY1_BITS   (1)

Definition at line 11263 of file regs.h.

#define TPIU_ITATBCTR0_ATREADY1_MASK   (0x00000001u)

Definition at line 11261 of file regs.h.

#define TPIU_ITATBCTR0_REG   *((volatile int32u *)0xE0040EF8u)

Definition at line 11256 of file regs.h.

#define TPIU_ITATBCTR0_RESET   (0x00000000u)

Definition at line 11258 of file regs.h.

#define TPIU_ITATBCTR2   *((volatile int32u *)0xE0040EF0u)

Definition at line 11245 of file regs.h.

#define TPIU_ITATBCTR2_ADDR   (0xE0040EF0u)

Definition at line 11247 of file regs.h.

#define TPIU_ITATBCTR2_ATREADY1   (0x00000001u)

Definition at line 11250 of file regs.h.

#define TPIU_ITATBCTR2_ATREADY1_BIT   (0)

Definition at line 11252 of file regs.h.

#define TPIU_ITATBCTR2_ATREADY1_BITS   (1)

Definition at line 11253 of file regs.h.

#define TPIU_ITATBCTR2_ATREADY1_MASK   (0x00000001u)

Definition at line 11251 of file regs.h.

#define TPIU_ITATBCTR2_REG   *((volatile int32u *)0xE0040EF0u)

Definition at line 11246 of file regs.h.

#define TPIU_ITATBCTR2_RESET   (0x00000000u)

Definition at line 11248 of file regs.h.

#define TPIU_SPP   *((volatile int32u *)0xE00400F0u)

Definition at line 11185 of file regs.h.

#define TPIU_SPP_ADDR   (0xE00400F0u)

Definition at line 11187 of file regs.h.

#define TPIU_SPP_PROTOCOL   (0x00000003u)

Definition at line 11190 of file regs.h.

#define TPIU_SPP_PROTOCOL_BIT   (0)

Definition at line 11192 of file regs.h.

#define TPIU_SPP_PROTOCOL_BITS   (2)

Definition at line 11193 of file regs.h.

#define TPIU_SPP_PROTOCOL_MASK   (0x00000003u)

Definition at line 11191 of file regs.h.

#define TPIU_SPP_REG   *((volatile int32u *)0xE00400F0u)

Definition at line 11186 of file regs.h.

#define TPIU_SPP_RESET   (0x00000001u)

Definition at line 11188 of file regs.h.

#define TPIU_SPS   *((volatile int32u *)0xE0040000u)

Definition at line 11125 of file regs.h.

#define TPIU_SPS_ADDR   (0xE0040000u)

Definition at line 11127 of file regs.h.

#define TPIU_SPS_REG   *((volatile int32u *)0xE0040000u)

Definition at line 11126 of file regs.h.

#define TPIU_SPS_RESET   (0x00000000u)

Definition at line 11128 of file regs.h.

#define TPIU_SPS_SPS_01   (0x00000001u)

Definition at line 11145 of file regs.h.

#define TPIU_SPS_SPS_01_BIT   (0)

Definition at line 11147 of file regs.h.

#define TPIU_SPS_SPS_01_BITS   (1)

Definition at line 11148 of file regs.h.

#define TPIU_SPS_SPS_01_MASK   (0x00000001u)

Definition at line 11146 of file regs.h.

#define TPIU_SPS_SPS_02   (0x00000002u)

Definition at line 11140 of file regs.h.

#define TPIU_SPS_SPS_02_BIT   (1)

Definition at line 11142 of file regs.h.

#define TPIU_SPS_SPS_02_BITS   (1)

Definition at line 11143 of file regs.h.

#define TPIU_SPS_SPS_02_MASK   (0x00000002u)

Definition at line 11141 of file regs.h.

#define TPIU_SPS_SPS_03   (0x00000004u)

Definition at line 11135 of file regs.h.

#define TPIU_SPS_SPS_03_BIT   (2)

Definition at line 11137 of file regs.h.

#define TPIU_SPS_SPS_03_BITS   (1)

Definition at line 11138 of file regs.h.

#define TPIU_SPS_SPS_03_MASK   (0x00000004u)

Definition at line 11136 of file regs.h.

#define TPIU_SPS_SPS_04   (0x00000008u)

Definition at line 11130 of file regs.h.

#define TPIU_SPS_SPS_04_BIT   (3)

Definition at line 11132 of file regs.h.

#define TPIU_SPS_SPS_04_BITS   (1)

Definition at line 11133 of file regs.h.

#define TPIU_SPS_SPS_04_MASK   (0x00000008u)

Definition at line 11131 of file regs.h.

#define TUNE_FILTER_CTRL   *((volatile int32u *)0x40001110u)

Definition at line 1425 of file regs.h.

#define TUNE_FILTER_CTRL_ADDR   (0x40001110u)

Definition at line 1427 of file regs.h.

#define TUNE_FILTER_CTRL_REG   *((volatile int32u *)0x40001110u)

Definition at line 1426 of file regs.h.

#define TUNE_FILTER_CTRL_RESET   (0x00000000u)

Definition at line 1428 of file regs.h.

#define TUNE_FILTER_CTRL_TUNE_FILTER_EN   (0x00000002u)

Definition at line 1430 of file regs.h.

#define TUNE_FILTER_CTRL_TUNE_FILTER_EN_BIT   (1)

Definition at line 1432 of file regs.h.

#define TUNE_FILTER_CTRL_TUNE_FILTER_EN_BITS   (1)

Definition at line 1433 of file regs.h.

#define TUNE_FILTER_CTRL_TUNE_FILTER_EN_MASK   (0x00000002u)

Definition at line 1431 of file regs.h.

#define TUNE_FILTER_CTRL_TUNE_FILTER_RESET   (0x00000001u)

Definition at line 1435 of file regs.h.

#define TUNE_FILTER_CTRL_TUNE_FILTER_RESET_BIT   (0)

Definition at line 1437 of file regs.h.

#define TUNE_FILTER_CTRL_TUNE_FILTER_RESET_BITS   (1)

Definition at line 1438 of file regs.h.

#define TUNE_FILTER_CTRL_TUNE_FILTER_RESET_MASK   (0x00000001u)

Definition at line 1436 of file regs.h.

#define TX_COUNT   *((volatile int32u *)0x40002028u)

Definition at line 1595 of file regs.h.

#define TX_COUNT_ADDR   (0x40002028u)

Definition at line 1597 of file regs.h.

#define TX_COUNT_REG   *((volatile int32u *)0x40002028u)

Definition at line 1596 of file regs.h.

#define TX_COUNT_RESET   (0x00000000u)

Definition at line 1598 of file regs.h.

#define TX_COUNT_TX_COUNT   (0x000007FFu)

Definition at line 1600 of file regs.h.

#define TX_COUNT_TX_COUNT_BIT   (0)

Definition at line 1602 of file regs.h.

#define TX_COUNT_TX_COUNT_BITS   (11)

Definition at line 1603 of file regs.h.

#define TX_COUNT_TX_COUNT_MASK   (0x000007FFu)

Definition at line 1601 of file regs.h.

#define TX_CRC   *((volatile int32u *)0x4000206Cu)

Definition at line 1860 of file regs.h.

#define TX_CRC_ADDR   (0x4000206Cu)

Definition at line 1862 of file regs.h.

#define TX_CRC_REG   *((volatile int32u *)0x4000206Cu)

Definition at line 1861 of file regs.h.

#define TX_CRC_RESET   (0x00000000u)

Definition at line 1863 of file regs.h.

#define TX_CRC_TX_CRC   (0x0000FFFFu)

Definition at line 1865 of file regs.h.

#define TX_CRC_TX_CRC_BIT   (0)

Definition at line 1867 of file regs.h.

#define TX_CRC_TX_CRC_BITS   (16)

Definition at line 1868 of file regs.h.

#define TX_CRC_TX_CRC_MASK   (0x0000FFFFu)

Definition at line 1866 of file regs.h.

#define TX_POWER_MAX   *((volatile int32u *)0x400010C0u)

Definition at line 1065 of file regs.h.

#define TX_POWER_MAX_ADDR   (0x400010C0u)

Definition at line 1067 of file regs.h.

#define TX_POWER_MAX_MANUAL_POWER   (0x00008000u)

Definition at line 1070 of file regs.h.

#define TX_POWER_MAX_MANUAL_POWER_BIT   (15)

Definition at line 1072 of file regs.h.

#define TX_POWER_MAX_MANUAL_POWER_BITS   (1)

Definition at line 1073 of file regs.h.

#define TX_POWER_MAX_MANUAL_POWER_MASK   (0x00008000u)

Definition at line 1071 of file regs.h.

#define TX_POWER_MAX_REG   *((volatile int32u *)0x400010C0u)

Definition at line 1066 of file regs.h.

#define TX_POWER_MAX_RESET   (0x00000000u)

Definition at line 1068 of file regs.h.

#define TX_POWER_MAX_TX_POWER_MAX   (0x0000001Fu)

Definition at line 1075 of file regs.h.

#define TX_POWER_MAX_TX_POWER_MAX_BIT   (0)

Definition at line 1077 of file regs.h.

#define TX_POWER_MAX_TX_POWER_MAX_BITS   (5)

Definition at line 1078 of file regs.h.

#define TX_POWER_MAX_TX_POWER_MAX_MASK   (0x0000001Fu)

Definition at line 1076 of file regs.h.

#define TX_STATE   *((volatile int32u *)0x400020B0u)

Definition at line 2185 of file regs.h.

#define TX_STATE_ADDR   (0x400020B0u)

Definition at line 2187 of file regs.h.

#define TX_STATE_REG   *((volatile int32u *)0x400020B0u)

Definition at line 2186 of file regs.h.

#define TX_STATE_RESET   (0x00000000u)

Definition at line 2188 of file regs.h.

#define TX_STATE_TX_BUFFER_STATE   (0x000000F0u)

Definition at line 2190 of file regs.h.

#define TX_STATE_TX_BUFFER_STATE_BIT   (4)

Definition at line 2192 of file regs.h.

#define TX_STATE_TX_BUFFER_STATE_BITS   (4)

Definition at line 2193 of file regs.h.

#define TX_STATE_TX_BUFFER_STATE_MASK   (0x000000F0u)

Definition at line 2191 of file regs.h.

#define TX_STATE_TX_TOP_STATE   (0x0000000Fu)

Definition at line 2195 of file regs.h.

#define TX_STATE_TX_TOP_STATE_BIT   (0)

Definition at line 2197 of file regs.h.

#define TX_STATE_TX_TOP_STATE_BITS   (4)

Definition at line 2198 of file regs.h.

#define TX_STATE_TX_TOP_STATE_MASK   (0x0000000Fu)

Definition at line 2196 of file regs.h.

#define TX_STEP_TIME   *((volatile int32u *)0x40001064u)

Definition at line 710 of file regs.h.

#define TX_STEP_TIME_ADDR   (0x40001064u)

Definition at line 712 of file regs.h.

#define TX_STEP_TIME_REG   *((volatile int32u *)0x40001064u)

Definition at line 711 of file regs.h.

#define TX_STEP_TIME_RESET   (0x00000000u)

Definition at line 713 of file regs.h.

#define TX_STEP_TIME_TX_STEP_TIME   (0x000000FFu)

Definition at line 715 of file regs.h.

#define TX_STEP_TIME_TX_STEP_TIME_BIT   (0)

Definition at line 717 of file regs.h.

#define TX_STEP_TIME_TX_STEP_TIME_BITS   (8)

Definition at line 718 of file regs.h.

#define TX_STEP_TIME_TX_STEP_TIME_MASK   (0x000000FFu)

Definition at line 716 of file regs.h.

#define VREG   *((volatile int32u *)0x40000018u)

Definition at line 110 of file regs.h.

#define VREG_ADDR   (0x40000018u)

Definition at line 112 of file regs.h.

#define VREG_REG   *((volatile int32u *)0x40000018u)

Definition at line 111 of file regs.h.

#define VREG_RESET   (0x00000207u)

Definition at line 113 of file regs.h.

#define VREG_VREF_EN   (0x00008000u)

Definition at line 115 of file regs.h.

#define VREG_VREF_EN_BIT   (15)

Definition at line 117 of file regs.h.

#define VREG_VREF_EN_BITS   (1)

Definition at line 118 of file regs.h.

#define VREG_VREF_EN_MASK   (0x00008000u)

Definition at line 116 of file regs.h.

#define VREG_VREF_TEST   (0x00004000u)

Definition at line 120 of file regs.h.

#define VREG_VREF_TEST_BIT   (14)

Definition at line 122 of file regs.h.

#define VREG_VREF_TEST_BITS   (1)

Definition at line 123 of file regs.h.

#define VREG_VREF_TEST_MASK   (0x00004000u)

Definition at line 121 of file regs.h.

#define VREG_VREG_1V2_EN   (0x00000010u)

Definition at line 140 of file regs.h.

#define VREG_VREG_1V2_EN_BIT   (4)

Definition at line 142 of file regs.h.

#define VREG_VREG_1V2_EN_BITS   (1)

Definition at line 143 of file regs.h.

#define VREG_VREG_1V2_EN_MASK   (0x00000010u)

Definition at line 141 of file regs.h.

#define VREG_VREG_1V2_TEST   (0x00000008u)

Definition at line 145 of file regs.h.

#define VREG_VREG_1V2_TEST_BIT   (3)

Definition at line 147 of file regs.h.

#define VREG_VREG_1V2_TEST_BITS   (1)

Definition at line 148 of file regs.h.

#define VREG_VREG_1V2_TEST_MASK   (0x00000008u)

Definition at line 146 of file regs.h.

#define VREG_VREG_1V2_TRIM   (0x00000007u)

Definition at line 150 of file regs.h.

#define VREG_VREG_1V2_TRIM_BIT   (0)

Definition at line 152 of file regs.h.

#define VREG_VREG_1V2_TRIM_BITS   (3)

Definition at line 153 of file regs.h.

#define VREG_VREG_1V2_TRIM_MASK   (0x00000007u)

Definition at line 151 of file regs.h.

#define VREG_VREG_1V8_EN   (0x00000800u)

Definition at line 125 of file regs.h.

#define VREG_VREG_1V8_EN_BIT   (11)

Definition at line 127 of file regs.h.

#define VREG_VREG_1V8_EN_BITS   (1)

Definition at line 128 of file regs.h.

#define VREG_VREG_1V8_EN_MASK   (0x00000800u)

Definition at line 126 of file regs.h.

#define VREG_VREG_1V8_TEST   (0x00000400u)

Definition at line 130 of file regs.h.

#define VREG_VREG_1V8_TEST_BIT   (10)

Definition at line 132 of file regs.h.

#define VREG_VREG_1V8_TEST_BITS   (1)

Definition at line 133 of file regs.h.

#define VREG_VREG_1V8_TEST_MASK   (0x00000400u)

Definition at line 131 of file regs.h.

#define VREG_VREG_1V8_TRIM   (0x00000380u)

Definition at line 135 of file regs.h.

#define VREG_VREG_1V8_TRIM_BIT   (7)

Definition at line 137 of file regs.h.

#define VREG_VREG_1V8_TRIM_BITS   (3)

Definition at line 138 of file regs.h.

#define VREG_VREG_1V8_TRIM_MASK   (0x00000380u)

Definition at line 136 of file regs.h.

#define WAKE_CDBGPWRUPREQ   (0x00000100u)

Definition at line 165 of file regs.h.

#define WAKE_CDBGPWRUPREQ_BIT   (8)

Definition at line 167 of file regs.h.

#define WAKE_CDBGPWRUPREQ_BITS   (1)

Definition at line 168 of file regs.h.

#define WAKE_CDBGPWRUPREQ_MASK   (0x00000100u)

Definition at line 166 of file regs.h.

#define WAKE_CORE   *((volatile int32u *)0x40000024u)

Definition at line 210 of file regs.h.

#define WAKE_CORE_ADDR   (0x40000024u)

Definition at line 212 of file regs.h.

#define WAKE_CORE_FIELD   (0x00000020u)

Definition at line 215 of file regs.h.

#define WAKE_CORE_FIELD_BIT   (5)

Definition at line 217 of file regs.h.

#define WAKE_CORE_FIELD_BITS   (1)

Definition at line 218 of file regs.h.

#define WAKE_CORE_FIELD_MASK   (0x00000020u)

Definition at line 216 of file regs.h.

#define WAKE_CORE_REG   *((volatile int32u *)0x40000024u)

Definition at line 211 of file regs.h.

#define WAKE_CORE_RESET   (0x00000000u)

Definition at line 213 of file regs.h.

#define WAKE_CSYSPWRUPREQ   (0x00000200u)

Definition at line 160 of file regs.h.

#define WAKE_CSYSPWRUPREQ_BIT   (9)

Definition at line 162 of file regs.h.

#define WAKE_CSYSPWRUPREQ_BITS   (1)

Definition at line 163 of file regs.h.

#define WAKE_CSYSPWRUPREQ_MASK   (0x00000200u)

Definition at line 161 of file regs.h.

#define WAKE_IRQD   (0x00000008u)

Definition at line 190 of file regs.h.

#define WAKE_IRQD_BIT   (3)

Definition at line 192 of file regs.h.

#define WAKE_IRQD_BITS   (1)

Definition at line 193 of file regs.h.

#define WAKE_IRQD_MASK   (0x00000008u)

Definition at line 191 of file regs.h.

#define WAKE_SC1   (0x00000002u)

Definition at line 200 of file regs.h.

#define WAKE_SC1_BIT   (1)

Definition at line 202 of file regs.h.

#define WAKE_SC1_BITS   (1)

Definition at line 203 of file regs.h.

#define WAKE_SC1_MASK   (0x00000002u)

Definition at line 201 of file regs.h.

#define WAKE_SC2   (0x00000004u)

Definition at line 195 of file regs.h.

#define WAKE_SC2_BIT   (2)

Definition at line 197 of file regs.h.

#define WAKE_SC2_BITS   (1)

Definition at line 198 of file regs.h.

#define WAKE_SC2_MASK   (0x00000004u)

Definition at line 196 of file regs.h.

#define WAKE_SEL   *((volatile int32u *)0x40000020u)

Definition at line 155 of file regs.h.

#define WAKE_SEL_ADDR   (0x40000020u)

Definition at line 157 of file regs.h.

#define WAKE_SEL_REG   *((volatile int32u *)0x40000020u)

Definition at line 156 of file regs.h.

#define WAKE_SEL_RESET   (0x00000200u)

Definition at line 158 of file regs.h.

#define WAKE_SLEEPTMRCMPA   (0x00000010u)

Definition at line 185 of file regs.h.

#define WAKE_SLEEPTMRCMPA_BIT   (4)

Definition at line 187 of file regs.h.

#define WAKE_SLEEPTMRCMPA_BITS   (1)

Definition at line 188 of file regs.h.

#define WAKE_SLEEPTMRCMPA_MASK   (0x00000010u)

Definition at line 186 of file regs.h.

#define WAKE_SLEEPTMRCMPB   (0x00000020u)

Definition at line 180 of file regs.h.

#define WAKE_SLEEPTMRCMPB_BIT   (5)

Definition at line 182 of file regs.h.

#define WAKE_SLEEPTMRCMPB_BITS   (1)

Definition at line 183 of file regs.h.

#define WAKE_SLEEPTMRCMPB_MASK   (0x00000020u)

Definition at line 181 of file regs.h.

#define WAKE_SLEEPTMRWRAP   (0x00000040u)

Definition at line 175 of file regs.h.

#define WAKE_SLEEPTMRWRAP_BIT   (6)

Definition at line 177 of file regs.h.

#define WAKE_SLEEPTMRWRAP_BITS   (1)

Definition at line 178 of file regs.h.

#define WAKE_SLEEPTMRWRAP_MASK   (0x00000040u)

Definition at line 176 of file regs.h.

#define WAKE_WAKE_CORE   (0x00000080u)

Definition at line 170 of file regs.h.

#define WAKE_WAKE_CORE_BIT   (7)

Definition at line 172 of file regs.h.

#define WAKE_WAKE_CORE_BITS   (1)

Definition at line 173 of file regs.h.

#define WAKE_WAKE_CORE_MASK   (0x00000080u)

Definition at line 171 of file regs.h.

#define WDOG_CFG   *((volatile int32u *)0x40006000u)

Definition at line 2770 of file regs.h.

#define WDOG_CFG_ADDR   (0x40006000u)

Definition at line 2772 of file regs.h.

#define WDOG_CFG_REG   *((volatile int32u *)0x40006000u)

Definition at line 2771 of file regs.h.

#define WDOG_CFG_RESET   (0x00000002u)

Definition at line 2773 of file regs.h.

#define WDOG_DISABLE   (0x00000002u)

Definition at line 2775 of file regs.h.

#define WDOG_DISABLE_BIT   (1)

Definition at line 2777 of file regs.h.

#define WDOG_DISABLE_BITS   (1)

Definition at line 2778 of file regs.h.

#define WDOG_DISABLE_MASK   (0x00000002u)

Definition at line 2776 of file regs.h.

#define WDOG_ENABLE   (0x00000001u)

Definition at line 2780 of file regs.h.

#define WDOG_ENABLE_BIT   (0)

Definition at line 2782 of file regs.h.

#define WDOG_ENABLE_BITS   (1)

Definition at line 2783 of file regs.h.

#define WDOG_ENABLE_MASK   (0x00000001u)

Definition at line 2781 of file regs.h.

#define WDOG_KEY   *((volatile int32u *)0x40006004u)

Definition at line 2785 of file regs.h.

#define WDOG_KEY_ADDR   (0x40006004u)

Definition at line 2787 of file regs.h.

#define WDOG_KEY_FIELD   (0x0000FFFFu)

Definition at line 2790 of file regs.h.

#define WDOG_KEY_FIELD_BIT   (0)

Definition at line 2792 of file regs.h.

#define WDOG_KEY_FIELD_BITS   (16)

Definition at line 2793 of file regs.h.

#define WDOG_KEY_FIELD_MASK   (0x0000FFFFu)

Definition at line 2791 of file regs.h.

#define WDOG_KEY_REG   *((volatile int32u *)0x40006004u)

Definition at line 2786 of file regs.h.

#define WDOG_KEY_RESET   (0x00000000u)

Definition at line 2788 of file regs.h.

#define WDOG_RESET   *((volatile int32u *)0x40006008u)

Definition at line 2795 of file regs.h.

#define WDOG_RESET_ADDR   (0x40006008u)

Definition at line 2797 of file regs.h.

#define WDOG_RESET_REG   *((volatile int32u *)0x40006008u)

Definition at line 2796 of file regs.h.

#define WDOG_RESET_RESET   (0x00000000u)

Definition at line 2798 of file regs.h.

#define WRPROT   *((volatile int32u *)0x40008020u)

Definition at line 3125 of file regs.h.

#define WRPROT_ADDR   (0x40008020u)

Definition at line 3127 of file regs.h.

#define WRPROT_REG   *((volatile int32u *)0x40008020u)

Definition at line 3126 of file regs.h.

#define WRPROT_RESET   (0xFFFFFFFFu)

Definition at line 3128 of file regs.h.

#define WRPROT_WRP   (0xFFFFFFFFu)

Definition at line 3130 of file regs.h.

#define WRPROT_WRP_BIT   (0)

Definition at line 3132 of file regs.h.

#define WRPROT_WRP_BITS   (32)

Definition at line 3133 of file regs.h.

#define WRPROT_WRP_MASK   (0xFFFFFFFFu)

Definition at line 3131 of file regs.h.